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AgeCommit message (Expand)AuthorFilesLines
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich2-0/+4
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu4-2/+27
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson2-0/+15
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson3-1/+69
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson8-0/+304
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson3-0/+41
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson3-0/+41
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson15-0/+544
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson7-0/+350
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich7-54/+22
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich11-201/+61
2019-10-31i386; Add .code16gcc fldenv testsH.J. Lu2-2/+15
2019-10-31Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu4-0/+25
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv4-29/+45
2019-10-30x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich7-0/+385
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2-0/+13
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz13-0/+57
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich8-10/+231
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina3-0/+11
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ins...Srinath Parvathaneni4-1/+76
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich2-2/+14
2019-09-10Enhance the disassembler so that it will reliably determine whether a reloc a...Nick Clifton2-0/+35
2019-09-10[PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni5-0/+136
2019-08-30[PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction correc...Srinath Parvathaneni2-0/+79
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This instruct...Srinath Parvathaneni3-200/+231
2019-08-25RISC-V: Improve li expansion for better code density.Kito Cheng4-0/+75
2019-08-22Arm: Add support for missing CPUsDennis Zhang3-0/+18
2019-08-22Fix the assembler's floating point number parser so that it can correctly han...Bosco Garc?a3-0/+7
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point n...Barnaby Wilks3-0/+41
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov1-10/+10
2019-08-20Remove test files for a different patch accidentally committed with patch for...Nick Clifton2-35/+0
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77...Dennis Zhang8-0/+66
2019-08-19MIPS/gas: Retain ISA mode bit for labels with .insn annotationFaraz Shahbazker3-0/+31
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni4-6/+22
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating poi...Barnaby Wilks15-0/+124
2019-08-09x86-64: generalize SIMD test expectationsJan Beulich6-927/+201
2019-08-08Change the output of readelf's note display so that the "Data size" column he...Nick Clifton4-4/+4
2019-08-08Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location.Yoshinori Sato4-50/+49
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks10-2710/+38
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson4-1/+61
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu1-1/+1
2019-07-24Complain about mbind, ifunc, and unique in final_writeAlan Modra2-2/+2
2019-07-24Define ELF_OSABI for visiumAlan Modra3-5/+10
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov3-0/+3
2019-07-23SHF_GNU_MBIND requires ELFOSABI_GNUAlan Modra4-3/+7
2019-07-23gas "mbind sections" testAlan Modra1-2/+0
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline specification,...Barnaby Wilks8-132/+124
2019-07-19x86: Pass -O0 to assembler in noextreg.dH.J. Lu1-0/+1
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi6-52/+52
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford5-5/+5
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