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AgeCommit message (Expand)AuthorFilesLines
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao5-205/+566
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra4-0/+15
2022-10-14PowerPC SPE disassembly and testsAlan Modra4-14/+11
2022-10-14e200 LSP supportAlan Modra3-7/+3
2022-10-14RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI1-0/+6
2022-10-14RISC-V: Test DWARF register number for "fp"Tsukasa OI2-0/+4
2022-10-05x86/gas: support quoted address scale factor in AT&T syntaxJan Beulich3-0/+16
2022-10-05Arm64: support CLEARBHB aliasJan Beulich2-1/+3
2022-10-04RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich6-4/+56
2022-10-03RISC-V: Assign DWARF numbers to vector registersTsukasa OI2-2/+70
2022-10-03RISC-V: Add testcase for DWARF register numbersTsukasa OI2-0/+296
2022-09-30RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI6-0/+6
2022-09-30RISC-V: Reorganize and enhance 'Zfinx' testsTsukasa OI6-106/+207
2022-09-30RISC-V: fallout from "re-arrange opcode table for consistent alias handling"Jan Beulich4-14/+14
2022-09-30RISC-V: drop stray INSN_ALIAS flagsJan Beulich2-0/+35
2022-09-30RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich21-159/+375
2022-09-30x86: improve match_template()'s diagnosticsJan Beulich6-36/+36
2022-09-30x86/Intel: restrict suffix derivationJan Beulich4-0/+145
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner3-0/+25
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner5-0/+83
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner5-0/+132
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner5-0/+80
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2-0/+22
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2-0/+14
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner15-0/+126
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner5-0/+35
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner5-0/+99
2022-09-21RISC-V: Implement Ztso extensionShihua1-0/+8
2022-09-21RISC-V: Always generate R_RISCV_CALL_PLT reloc for call in assembler.Nelson Chu2-2/+2
2022-09-21ppc/svp64: test setvl ms operandDmitry Selyutin2-0/+2
2022-09-16RISC-V: Make g imply zmmul extension.Nelson Chu8-8/+8
2022-09-10Re: PR29466, APP/NO_APP with linefileAlan Modra1-1/+1
2022-09-09RISC-V: Fix vector CSR requirementsTsukasa OI4-56/+56
2022-09-08Gas generated incorrect debug info (top-level DW_TAG_unspecified_type DIE)Nick Clifton4-16/+16
2022-09-07LoongArch: fix gas BFD_RELOC_8/16/24 bugmengqinggang2-0/+17
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI6-0/+71
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI4-1/+135
2022-09-02RISC-V: Add address printer tests with ADDIWTsukasa OI3-0/+64
2022-08-30Add a testcase for PR 29494.Nick Clifton2-0/+9995
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI15-2/+143
2022-08-25GAS: Add a return type tag to DWARF DIEs generated for function symbols.Nick Clifton4-0/+24
2022-08-25GAS: Allow AArch64 pseudo-ops to accept the command line separator character.Nick Clifton2-0/+15
2022-08-24gas: arm: handle multiple .directives on a single line (PR29519)Richard Earnshaw2-0/+29
2022-08-22LoongArch: gas: add support using constant variable in instructions.tangxiaolin9-0/+332
2022-08-16i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu3-0/+14
2022-08-13readelf: print 0x0 as 0, and remove trailing spacesAlan Modra54-154/+153
2022-08-11ppc/svp64: support svindex instructionDmitry Selyutin3-0/+25
2022-08-11ppc/svp64: support svremap instructionDmitry Selyutin3-0/+25
2022-08-11ppc/svp64: support svshape instructionDmitry Selyutin3-0/+19
2022-08-11ppc/svp64: support svstep instructionsDmitry Selyutin3-0/+19
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