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2018-04-04i386: Clear vex instead of vex.evexH.J. Lu2-0/+7
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li24-0/+216
2018-03-28x86: drop VecESizeJan Beulich6-0/+18
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich2-0/+278
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich2-16/+16
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2-0/+38
2018-03-22ix86: allow HLE store of accumulator to absolute addressJan Beulich3-0/+9
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich5-0/+24
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich3-0/+231
2018-03-22x86: fold a few XOP templatesJan Beulich3-0/+135
2018-03-16RISC-V: Emit better warning for unknown CSR.Jim Wilson3-0/+6
2018-03-14Missing testcase files for last commit.Jim Wilson2-0/+90
2018-03-09x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu2-24/+24
2018-03-09x86: Strip whitespace in check_VecOperationsH.J. Lu2-2/+2
2018-03-08x86: Optimize with EVEX128 encoding for AVX512VLH.J. Lu11-48/+428
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu2-0/+4
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu7-33/+21
2018-03-08x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich3-0/+47
2018-03-08x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich17-1/+144
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich14-125/+63
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2-0/+711
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich2-18/+18
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich3-6/+0
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu61-3206/+2144
2018-03-07XCOFF disassemblerAlan Modra3-74/+75
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu4-0/+104
2018-02-27gas: Rename .nop directive to .nopsH.J. Lu20-32/+32
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu17-0/+475
2018-02-26BFD messagesAlan Modra1-1/+1
2018-02-26MIPS messagesAlan Modra1-1/+1
2018-02-22Diagnose when trying to assemble conditional FP16 vmovx and vinsAndre Simoes Dias Vieira2-205/+265
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu2-0/+52
2018-02-20MIPS16/GAS/testsuite: Add cross-section R_MIPS16_PC16_S1 relocation testsMaciej W. Rozycki5-0/+114
2018-02-20gas: xtensa: limit size of auto litpoolsMax Filippov5-3/+19
2018-02-17Add .nop assembler directiveH.J. Lu21-0/+459
2018-02-15Fix AArch32 build attributes for Armv8.4-A.Tamar Christina1-0/+17
2018-02-13Fix ARm assembler so that it rejects invalid immediate values for the Thumb O...Nick Clifton3-0/+14
2018-02-13x86-64: Generate branch with PLT32 relocationH.J. Lu8-22/+22
2018-02-13MIPS/GAS/testsuite: Correct duplicate `Loongson-3A tests' test nameMaciej W. Rozycki1-1/+1
2018-02-12MIPS/GAS/test: Fix an n32 `.reginfo' size test failureMaciej W. Rozycki1-1/+1
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong3-6/+6
2018-02-08PR22819, powerpc gas "instruction address is not a multiple of 4"Alan Modra6-0/+29
2018-02-05MIPS/BFD: Correctly report unsupported `.reginfo' section sizeMaciej W. Rozycki5-0/+16
2018-01-24[GAS][AARCH64]Add group relocations to create PC-relative offset.Renlin Li14-0/+155
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist7-0/+58
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist7-0/+58
2018-01-22Fix the RX assembler so that it can handle escaped double quote characters, i...Oleg Endo3-0/+17
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist9-0/+44
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-2/+4
2018-01-15[ARM] Enable conditional Armv8-M instructionsThomas Preud'homme1-2/+11
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