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2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili4-0/+34
2020-04-02Add support for intel SERIALIZE instructionLiliCui4-0/+31
2020-04-02ld: Disable ifunc tests on SolarisRainer Orth4-4/+4
2020-04-01x86: Force relocation against local absolute symbolH.J. Lu5-3/+13
2020-04-01gas: Fix some x86_64 testcases for Solaris not using R_X86_64_PLT32 [PR25732]Rainer Orth7-47/+77
2020-03-30RISC-V: Update CSR to privileged spec 1.11.Nelson Chu17-384/+426
2020-03-22s12z disassembler tidyAlan Modra1-5/+1
2020-03-17Fix a small set of Z80 problems.Sergey Belyashov13-97/+353
2020-03-13gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVEAndre Vieira6-0/+88
2020-03-11i386: Add tests for lfence with load/indirect branch/retH.J. Lu26-0/+711
2020-03-11Add support for generating DWARF-5 format directory and file name tables from...Nick Clifton3-14/+33
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich4-0/+448
2020-03-07Re: Add support for a ".file 0" directive if supporting DWARF 5 or higher.Alan Modra1-9/+8
2020-03-06Add support for a ".file 0" directive if supporting DWARF 5 or higher.Nick Clifton3-0/+25
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich6-50/+50
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich3-0/+159
2020-03-06x86: add missing IgnoreSizeJan Beulich30-22/+253
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich6-12/+51
2020-03-04RISC-V: Support assembler modifier %got_pcrel_hi.Nelson Chu4-7/+18
2020-03-04Generate a warning in the ARM assembler if a PC-relative thumb load instructi...Alexandre Oliva5-6/+8
2020-03-04x86: support VMGEXITJan Beulich4-3/+7
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov4-2/+42
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu7-24/+48
2020-03-03x86: Improve -malign-branchHongtao Liu5-0/+243
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson3-22/+34
2020-02-20RISC-V: Support the read-only CSR checking.Nelson Chu6-0/+459
2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu2-2/+2
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu6-2/+78
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2-0/+14
2020-02-19Various fixes for the Z80 support.Sergey Belyashov21-23/+24
2020-02-19x86: Mark cvtpi2ps and cvtpi2pd as MMXH.J. Lu4-0/+23
2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich7-0/+105
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich8-5/+62
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich27-68/+1596
2020-02-14x86: adjust segment override prefix emissionJan Beulich2-1/+14
2020-02-14x86: optimize away pointless segment overridesJan Beulich2-0/+14
2020-02-14x86: extend LEA's segment override warningJan Beulich4-0/+20
2020-02-13x86: Resolve PLT32 reloc aganst local symbol to sectionH.J. Lu5-0/+50
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich4-2/+22
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich7-0/+54
2020-02-12x86: also disallow non-byte/-word registers with byte/word suffixJan Beulich5-26/+39
2020-02-10[binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson11-0/+1103
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson7-0/+960
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu2-1/+7
2020-02-10gas: error for section type, attr, or entsize changeAlan Modra2-5/+6
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ...Sergey Belyashov6-0/+3499
2020-02-06ELF: Support the section flag 'o' in .section directiveH.J. Lu10-0/+98
2020-02-06x86: Run unique tests only for ELF targetsH.J. Lu3-4/+2
2020-02-06xfail x86 gas unique testAlan Modra2-0/+2
2020-02-06mbind gas tests and supports_gnu_osabi testsuite infrastructureAlan Modra4-12/+8
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