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AgeCommit message (Expand)AuthorFilesLines
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2-0/+15
2016-09-29Add .cfi_val_offset GAS command.Andreas Krebbel3-0/+30
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra2-3/+3
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford14-9611/+9611
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford4-76/+76
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford9-44/+178
2016-09-21Fix misplaced ChangeLogRichard Sandiford1-11/+0
2016-09-21[AArch64][SVE 32/32] Add SVE testsRichard Sandiford15-0/+79428
2016-09-21[AArch64][SVE 12/32] Remove boolean parameters from parse_address_mainRichard Sandiford2-0/+20
2016-09-21[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interfaceRichard Sandiford3-233/+238
2016-09-21[AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford2-0/+9
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu2-0/+22
2016-09-15gas: run the sparc test dcti-couples-v9 only in ELF targets.Jose E. Marchesi1-1/+1
2016-09-14Modify POWER9 support to match final ISA 3.0 documentation.Peter Bergner2-65/+11
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi7-0/+45
2016-09-14[ARC] Fix parsing dtpoff relocation expression.Claudiu Zissulescu2-0/+22
2016-09-12S/390: Fix kmctr instruction type.Patrick Steuer1-1/+1
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu9-9/+32
2016-08-26opcodes, gas: fix mnemonic of sparc camellia_flJose E. Marchesi2-2/+2
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme4-48/+296
2016-08-25Remove _S version of ARM MSR/MRS special registersThomas Preud'homme4-32/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu7-0/+115
2016-08-19ARM: Issue a warning when the MRRC and MRRC2 instructions are used with the s...Tamar Christina3-0/+36
2016-08-19Place .shstrtab section after .symtab and .strtab, thus restoring monotonical...Nick Clifton21-85/+85
2016-08-11[AArch64] Reject -0.0 as an 8-bit FP immediateRichard Sandiford2-1/+25
2016-08-05Ensure ARM VPUSH and VPOP instructions do not affect more than 16 registers.Nick Clifton3-0/+27
2016-08-05Fix the generation of alignment frags in code sections for AArch64.Nick Clifton2-0/+41
2016-07-29gas: avoid spurious failures in non-ELF targets in the SPARC testsuite.Jose E. Marchesi2-48/+43
2016-07-27MIPS/GAS: Implement microMIPS branch/jump compactionMaciej W. Rozycki43-589/+8268
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall2-0/+163
2016-07-26MIPS/GAS: Respect the `insn32' mode in branch relaxationMaciej W. Rozycki8-21/+1134
2016-07-20Add support to the ARC disassembler for selecting instruction classes.Claudiu Zissulescu8-4/+243
2016-07-19MIPS: Convert cross-mode BAL to JALXMaciej W. Rozycki11-16/+206
2016-07-19MIPS: Verify the ISA mode and alignment of branch and jump targetsMaciej W. Rozycki68-42/+4547
2016-07-14MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbolsMaciej W. Rozycki10-60/+132
2016-07-14MIPS/GAS: Keep the ISA bit in the addend of branch relocationsMaciej W. Rozycki6-46/+47
2016-07-14BFD: Let targets handle relocations against absolute symbolsMaciej W. Rozycki21-5/+528
2016-07-13MIPS/opcodes: Address issues with NAL disassemblyMaciej W. Rozycki6-0/+66
2016-07-13opcodes,gas: support for the ldtxa SPARC instructions.Jose E. Marchesi3-0/+60
2016-07-05x86: fix register check in check_qword_reg()Jan Beulich2-0/+9
2016-07-02MIPS/GAS/testsuite: Remove remnants of a.out/ECOFF supportMaciej W. Rozycki26-1822/+1036
2016-07-02MIPS/GAS/testsuite: Split `branch-misc-2' tests into twoMaciej W. Rozycki23-148/+286
2016-07-02MIPS/GAS/testsuite: Reenable disabled external BEQ testsMaciej W. Rozycki4-8/+19
2016-07-02MIPS/GAS/testsuite: Restrict 64-bit `branch-mips' tests to NewABI targetsMaciej W. Rozycki1-3/+8
2016-07-02MIPS/GAS/testsuite: Group `branch-misc' tests togetherMaciej W. Rozycki1-3/+2
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy3-0/+12
2016-07-01x86-64/MPX: relax no-RIP-relative-addressing testcaseJan Beulich1-4/+4
2016-07-01x86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich2-132/+202
2016-07-01x86/MPX: fix address size handlingJan Beulich3-0/+206
2016-07-01x86/Intel: don't accept bogus instructionsJan Beulich3-0/+35
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