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AgeCommit message (Expand)AuthorFilesLines
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist11-0/+136
2018-04-26x86: also optimize zeroing-masking variants of insnsJan Beulich6-72/+72
2018-04-26x86: properly force / avoid forcing EVEX encodingJan Beulich5-0/+60
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich3-0/+49
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich5-0/+89
2018-04-26x86: don't recognize bnd<N> as registers without CpuMPXJan Beulich3-0/+19
2018-04-26x86: x87-related adjustmentsJan Beulich5-0/+42
2018-04-25[ARM] Add FDPIC relocations definitionsChristophe Lyon2-0/+29
2018-04-25Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina3-125/+10058
2018-04-25Remove arm-aout and arm-coff supportAlan Modra151-152/+148
2018-04-20RISC-V: Add new option -mrelax/-mno-relax.Jim Wilson4-0/+45
2018-04-17Fix tests to avoid cldemote encoding.Igor Tsimbalist5-4/+10
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist12-10/+96
2018-04-16Remove arm-epoc-pe supportAlan Modra4-4/+3
2018-04-16Remove sparc-aout and sparc-coff supportAlan Modra3-47/+0
2018-04-16Remove m68k-aout and m68k-coff supportAlan Modra18-310/+2
2018-04-16Remove sh5 and sh64 supportAlan Modra144-6069/+7
2018-04-16Remove sh-symbianelf supportAlan Modra2-2/+0
2018-04-16Remove i370 supportAlan Modra3-13/+2
2018-04-16Remove h8300-coff supportAlan Modra7-380/+0
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu3-8/+20
2018-04-12Stop the assembler from overwriting its output file.John Darrington1-0/+2
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist7-0/+93
2018-04-11Remove i860, i960, bout and aout-adobe targetsAlan Modra85-5725/+3
2018-04-04i386: Clear vex instead of vex.evexH.J. Lu2-0/+7
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li24-0/+216
2018-03-28x86: drop VecESizeJan Beulich6-0/+18
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich2-0/+278
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich2-16/+16
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2-0/+38
2018-03-22ix86: allow HLE store of accumulator to absolute addressJan Beulich3-0/+9
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich5-0/+24
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich3-0/+231
2018-03-22x86: fold a few XOP templatesJan Beulich3-0/+135
2018-03-16RISC-V: Emit better warning for unknown CSR.Jim Wilson3-0/+6
2018-03-14Missing testcase files for last commit.Jim Wilson2-0/+90
2018-03-09x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu2-24/+24
2018-03-09x86: Strip whitespace in check_VecOperationsH.J. Lu2-2/+2
2018-03-08x86: Optimize with EVEX128 encoding for AVX512VLH.J. Lu11-48/+428
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu2-0/+4
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu7-33/+21
2018-03-08x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich3-0/+47
2018-03-08x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich17-1/+144
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich14-125/+63
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2-0/+711
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich2-18/+18
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich3-6/+0
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu61-3206/+2144
2018-03-07XCOFF disassemblerAlan Modra3-74/+75
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu4-0/+104
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