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AgeCommit message (Expand)AuthorFilesLines
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu10-188/+228
2017-09-05Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelfAlexander Fedotov-B556131-2/+2
2017-08-30MIPS/BFD: Correct microMIPS cross-mode BAL to JALX relaxationMaciej W. Rozycki5-0/+106
2017-08-30MIPS/GAS: Also respect `-mignore-branch-isa' with MIPS16 codeMaciej W. Rozycki21-0/+383
2017-08-30MIPS/GAS/testsuite: Deduplicate error lists of branch local testsMaciej W. Rozycki8-20/+4
2017-08-29Improve MSP430 section placement.Jozef Lawrynowicz3-0/+27
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov14-0/+2500
2017-08-23Assemble powerpc vle lsp tests with -a32Alan Modra2-2/+2
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov6-0/+1593
2017-08-15[Patch AArch64] Turn lr, fp, ip0 and ip1 into proper aliasesRamana Radhakrishnan4-0/+28
2017-08-11Also disallow global alias of common symbolH.J. Lu11-0/+38
2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang7-14/+52
2017-08-02Fix gas and binutils testsuite failures for am33_2.0-linux target.Nick Clifton13-23/+27
2017-08-01x86: Update segment register check in Intel syntaxH.J. Lu5-11/+43
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton1-1/+1
2017-07-21This patch introduces support for specifing views in .loc directives, so that...Alexandre Oliva53-37/+953
2017-07-19[ARC] Add JLI support.John Eric Martin3-0/+37
2017-07-19Fix gas crash on missing seh_endproc.Tristan Gingold3-0/+13
2017-07-18Fix spelling typos.Yuri Chornovian4-39/+39
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov4-0/+30
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan5-0/+17
2017-07-03Disable symver test on hppa64-hpuxAlan Modra1-0/+1
2017-07-01MIPS/GAS: Use non-zero frag offset directly in PIC branch relaxationMaciej W. Rozycki8-0/+123
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay6-0/+359
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki2-4/+28
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki2-1/+10
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki8-2/+39
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki2-42/+13
2017-06-30MIPS/GAS: Clear the ASE_MIPS16E2_MT flag for recalculationMaciej W. Rozycki4-0/+21
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina2-0/+1088
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang8-0/+672
2017-06-28MIPS: Add new Imagination interAptiv MR2 GAS and LD testsMaciej W. Rozycki32-9/+576
2017-06-28MIPS: Add Imagination interAptiv MR2 GAS test infrastructureMaciej W. Rozycki31-6/+535
2017-06-27MIPS/GAS/testsuite: Drop the `mips16e-' prefix from SAVE/RESTORE testsMaciej W. Rozycki6-4/+4
2017-06-27MIPS/GAS/testsuite: Run SAVE/RESTORE tests across all MIPS16e architecturesMaciej W. Rozycki5-7/+7
2017-06-27MIPS/GAS/testsuite: Convert `mips16e-save-err' list test to a dump testMaciej W. Rozycki2-1/+4
2017-06-27MIPS/GAS/testsuite: Capitalize the name of the `mips16e-save' testMaciej W. Rozycki1-1/+1
2017-06-26Check unsupported .symver with common symbolH.J. Lu4-0/+10
2017-06-26Update check conditions for illegal placed instructions.claziss3-0/+23
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme37-126/+637
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme6-6/+0
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu6-30/+30
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu6-12/+12
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu10-74/+203
2017-06-21[ARM] Allow Thumb division as an extension for ARMv7Thomas Preud'homme2-0/+7
2017-06-15i386-dis: Add 2 tests with invalid bnd registerH.J. Lu4-0/+32
2017-06-07Add support for AArch64 system register names IP0, IP1, FP and LR.Michael Collison2-2/+1
2017-06-06[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-AJiong Wang10-3/+273
2017-06-01S/390: idte/ipte fixesAndreas Krebbel8-27/+17
2017-05-30S/390: Fix instruction types of csdtr and csxtrAndreas Krebbel2-4/+4
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