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AgeCommit message (Expand)AuthorFilesLines
2024-07-05x86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili2-3/+12
2024-07-05x86: Add {load}/{store} tests for apx instructions.Cui, Lili3-0/+204
2024-07-04RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issueSun Sunny3-39/+110
2024-07-04mve: Fix encoding for vcvt[bt] single-half float conversion instructionsAndre Vieira1-68/+68
2024-07-04gas: User readable warnings if SFrame FDE is not generatedJens Remus3-3/+3
2024-07-04gas: Warn if SFrame FDE is skipped due to non-default return columnJens Remus1-0/+1
2024-07-04gas: Print DWARF call frame insn name in SFrame warning messageJens Remus2-2/+2
2024-07-04readelf/objdump: Display SFrame fixed RA offset as 'f' in dumpJens Remus8-23/+23
2024-07-04readelf/objdump: Dump SFrame CFA fixed FP and RA offsetsJens Remus14-0/+25
2024-07-04Support APX CFCMOVCui, Lili6-4/+400
2024-07-03RISC-V: Tidy and complete testing of all architecture imply rules.Nelson Chu21-97/+177
2024-07-03x86-64: Support APX NF TLS IE with 2 operandsLingling Kong2-0/+14
2024-07-01x86-64: Verify that TLS IE works with APX NFkonglin12-2/+10
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas9-3/+29
2024-06-28x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich2-0/+32
2024-06-28x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich3-16/+110
2024-06-28x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich3-0/+182
2024-06-28x86-64: restrict by-imm31 optimizationJan Beulich3-6/+6
2024-06-28x86/APX: optimize certain {nf}-form insns to LEAJan Beulich4-0/+1576
2024-06-28x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich2-0/+52
2024-06-28x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich5-1/+1545
2024-06-28RISC-V: Add Zabha extension CAS instructions.Jiawei3-2/+26
2024-06-26aarch64: FP8 scale and convert - Implement minor improvementsVictor Do Nascimento6-201/+166
2024-06-25aarch64: Fix FEAT_B16B16 sve2 instruction constraints.Srinath Parvathaneni12-26/+456
2024-06-25aarch64: Add extra tests for sve2p1 min max instructions.Srinath Parvathaneni6-201/+524
2024-06-25arch64: Fix the wrong constraint used for sve2p1 instructions.Srinath Parvathaneni3-0/+131
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni12-115/+629
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni8-18/+86
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni6-7/+129
2024-06-25aarch64: Enable mandatory feature bits for v9.4-A.Srinath Parvathaneni5-2/+9
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti31-6/+1073
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti19-4/+479
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com8-7/+239
2024-06-23aarch64: Enable +cssc for armv8.9-aAndrew Carlotti1-0/+1
2024-06-21x86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich9-0/+120
2024-06-21x86: optimize left-shift-by-1Jan Beulich5-0/+135
2024-06-21x86: %riz, %rip, and %eip don't require REXJan Beulich2-0/+5
2024-06-21x86: don't suppress errors when optimizingJan Beulich3-0/+11
2024-06-18RISC-V: Fixed typo from smscrind to smcsrind in riscv_implicit_subsets.Nelson Chu1-0/+6
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu3-0/+8
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida9-0/+137
2024-06-18Support APX CCMP and CTESTCui, Lili8-16/+720
2024-06-18LoongArch: add .option directiveLulu Cai5-0/+60
2024-06-17GAS/testsuite: Make a copy of none.s before operating on it as outputMaciej W. Rozycki1-2/+11
2024-06-17GAS/testsuite: Add a helper for paths outside the source dirMaciej W. Rozycki1-0/+13
2024-06-14aarch64: add SPMU system registers missed in f01ae0392edMatthieu Longo3-1/+539
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas9-0/+54
2024-06-12RISC-V: Support S[sm]csrind extension csrs.Jiawei8-36/+525
2024-06-11MIPS/opcodes: Add MIPS Allegrex DBREAK instructionDavid Guillen Fandos2-1/+3
2024-06-11MIPS/opcodes: Exclude trap instructions for MIPS AllegrexDavid Guillen Fandos4-0/+30
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