| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-08-21 | PR binutils/18257: Properly decode x86/Intel mask instructions. | Alexander Fomin | 5 | -2/+1002 |
| 2015-08-19 | [AArch64][5/6] GAS support TLSLD load/store relocation types | Jiong Wang | 17 | -0/+146 |
| 2015-08-19 | [AArch64][3/6] GAS support TLSLD move/add relocation types | Jiong Wang | 21 | -0/+167 |
| 2015-08-19 | [AArch64][1/6] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC | Jiong Wang | 5 | -0/+36 |
| 2015-08-13 | Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp. | Andre Vieira | 4 | -16/+39 |
| 2015-08-12 | xtensa: add --auto-litpools option | Max Filippov | 4 | -0/+34 |
| 2015-08-12 | [MIPS] Map 'move' to 'or'. | Simon Dardis | 36 | -171/+227 |
| 2015-08-11 | [AArch64][7/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 | Jiong Wang | 5 | -0/+36 |
| 2015-08-11 | [AArch64][5/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC | Jiong Wang | 5 | -0/+38 |
| 2015-08-11 | [AArch64][2/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 | Jiong Wang | 5 | -0/+41 |
| 2015-08-10 | Add SIGRIE instruction for MIPS R6 | Robert Suchanek | 5 | -0/+16 |
| 2015-07-30 | Properly disassemble movnti in Intel mode | H.J. Lu | 4 | -0/+334 |
| 2015-07-24 | Fix the evaluation of RL78 complex relocs, by making immediate values be comp... | Nick Clifton | 5 | -1/+21 |
| 2015-07-24 | Remove leading/trailing white spaces in ChangeLog | H.J. Lu | 1 | -1/+1 |
| 2015-07-22 | Fix memory operand size for vcvtt?ps2u?qq instructions | H.J. Lu | 13 | -240/+331 |
| 2015-07-21 | [ARM] Support correctly spelled ARMv6KZ architecture names | Matthew Wahab | 3 | -0/+33 |
| 2015-07-16 | Updates the ARM disassembler's output of floating point constants to include ... | Alessandro Marzocchi | 1 | -2/+2 |
| 2015-07-16 | [AArch64][2/3] GAS support BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 | Jiong Wang | 5 | -0/+40 |
| 2015-07-16 | [ARM] Make human parsing of "processor does not support instruction in mode" ... | James Greenhalgh | 7 | -137/+146 |
| 2015-07-10 | Updated to accept .debug_* sections | H.J. Lu | 2 | -2/+6 |
| 2015-07-10 | Add missing changelog entries | Alan Modra | 1 | -0/+6 |
| 2015-07-08 | Define DIFF_EXPR_OK for avr target to allow PC relative difference relocation. | Denis Chertykov | 3 | -0/+59 |
| 2015-07-03 | Remove ppc860, ppc750cl, ppc7450 insns from common ppc. | Alan Modra | 2 | -2/+6 |
| 2015-07-01 | Assembler tests for Nios II R2 | Sandra Loosemore | 123 | -0/+3862 |
| 2015-06-30 | Add support for monitorx/mwaitx instructions | Amit Pawar | 16 | -4/+304 |
| 2015-06-27 | Update ia64 gas tests | H.J. Lu | 3 | -2/+7 |
| 2015-06-25 | Update .strtab section sizes in mmix tests | H.J. Lu | 3 | -2/+7 |
| 2015-06-25 | Use strtab with GC and suffix merging for .strtab | H.J. Lu | 4 | -0/+24 |
| 2015-06-22 | PPC sync instruction accepts invalid and incompatible operands | Peter Bergner | 3 | -4/+9 |
| 2015-06-22 | Stop "objdump -d" from disassembling past a symbolic address. | Nick Clifton | 7 | -36/+48 |
| 2015-06-19 | Allow for optional operands with non-zero default values. | Peter Bergner | 4 | -5/+11 |
| 2015-06-18 | Add support for using the ADR alias in Thumb mode against nearby symbols. | Nick Clifton | 4 | -0/+27 |
| 2015-06-18 | Fix the computation of the addends for an ARM_TLS_LE32 reloc. | Nick Clifton | 3 | -0/+48 |
| 2015-06-17 | Add support for converting LDR Rx,=<imm> to MOV or MVN in Thumb2 mode. | Alessandro Marzocchi | 5 | -0/+66 |
| 2015-06-17 | Add support for converting VLDR <reg>,=<constant> to a VMOV instruction when ... | Alessandro Marzocchi | 7 | -0/+278 |
| 2015-06-16 | [AArch64] Support id_mmfr4 system register | Matthew Wahab | 3 | -11/+18 |
| 2015-06-15 | [AArch64] Gas add BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 support | Renlin Li | 3 | -15/+24 |
| 2015-06-15 | gas: Don't use frag_align but use plain padding to align .debug_aranges. | Mark Wielaard | 3 | -0/+38 |
| 2015-06-04 | Add hwsync extended mnemonic. | Peter Bergner | 3 | -4/+18 |
| 2015-06-03 | [ARM] Commit approaved testcases missed in previous commit | Matthew Wahab | 3 | -0/+142 |
| 2015-06-02 | [ARM] Add support for ARMv8.1 PAN extension | Matthew Wahab | 3 | -9/+39 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Adv.SIMD instructions | Matthew Wahab | 4 | -0/+223 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Limited Ordering Regions extension | Matthew Wahab | 4 | -0/+97 |
| 2015-06-01 | [AArch64][GAS] Add support for PAN architecture extension | Matthew Wahab | 4 | -0/+65 |
| 2015-06-01 | [AArch64] GAS support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 | Jiong Wang | 3 | -0/+8 |
| 2015-06-01 | [AArch64] GAS Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 | Jiong Wang | 3 | -15/+25 |
| 2015-06-01 | x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order | Jan Beulich | 7 | -432/+439 |
| 2015-06-01 | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 3 | -72/+81 |
| 2015-05-28 | Compact EH Support | Catherine Moore | 27 | -1/+783 |
| 2015-05-15 | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 8 | -2/+61 |
