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AgeCommit message (Expand)AuthorFilesLines
2022-01-12gas: add visibility support using GNU syntax on XCOFFClément Chigot4-0/+47
2022-01-12gas: add visibility support for XCOFFClément Chigot6-32/+253
2022-01-12objdump, readelf: Emit "CU:" format only when wide output is requestedHans-Peter Nilsson1-1/+1
2022-01-10XCOFF: add support for TLS relocations on hidden symbolsClément Chigot7-84/+289
2022-01-07RISC-V: Updated the default ISA spec to 20191213.Nelson Chu6-6/+6
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford2-0/+56
2022-01-05Adjust quoted-sym-names testAlan Modra2-6/+6
2022-01-04x86/Intel: correct VFPCLASSP{S,D} handling when displacement is presentJan Beulich3-4/+4
2022-01-04gas: rework handling of backslashes in quoted symbol namesJan Beulich4-7/+27
2022-01-02Update year range in copyright notice of binutils filesAlan Modra191-191/+191
2021-12-24RISC-V: Rewrite the csr testcases.Nelson Chu42-1521/+3567
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta4-0/+308
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta9-90/+0
2021-12-22RISC-V: Update Scalar Crypto testcases.jiawei18-144/+144
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev8-420/+420
2021-12-16Fix AVR assembler so that it creates relocs that will work with linker relaxa...Nick Clifton4-6/+6
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford9-0/+81
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford6-0/+54
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford15-0/+88
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2-0/+20
2021-12-09RISC-V: Clarify the behavior of .option arch directive.Nelson Chu8-9/+13
2021-12-02aarch64: Add BC instructionRichard Sandiford5-0/+86
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford3-0/+174
2021-12-02aarch64: Add support for +mopsRichard Sandiford5-0/+1557
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford5-0/+46
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford5-0/+8
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford2-0/+7
2021-12-02aarch64: Provide line info for unclosed sequencesRichard Sandiford3-3/+3
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford9-39/+66
2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford10-6/+877
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford4-1/+13
2021-11-30aarch64: Remove ZIDR_EL1Richard Sandiford3-7/+0
2021-11-30aarch64: Allow writes to MFAR_EL3Richard Sandiford5-20/+13
2021-11-30aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford5-3/+8
2021-11-30aarch64: Remove duplicate system register entriesRichard Sandiford2-4/+0
2021-11-30aarch64: Check for register aliases before mnemonicsRichard Sandiford5-1/+9
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2-0/+13
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2-68/+28
2021-11-29PR28629 NIOS2 falloutAlan Modra1-1/+1
2021-11-26gas: Update commit 4780e5e4933H.J. Lu1-1/+1
2021-11-26[gas] Fix file 0 dir with -gdwarf-5Tom de Vries1-1/+1
2021-11-22RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu15-18/+18
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu10-0/+80
2021-11-19Re: Add multibyte character warning option to the assembler.Alan Modra1-10/+10
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu4-0/+42
2021-11-18Add multibyte character warning option to the assembler.Nick Clifton6-0/+30
2021-11-18RISC-V: Add testcases for z[fdq]inxjiawei6-0/+222
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus5-0/+270
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus5-0/+61
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus5-0/+74
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