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2016-04-14gas/arc: Unify tests run on big/little endian arc assemblerAndrew Burgess3-3/+2
We were running a slightly different set of assembler tests on big and little endian arc targets. This commit unifies the set of tests run. gas/ChangeLog: * testsuite/gas/arc/add_s-err.s: Update target pattern. * testsuite/gas/arc/warn.s: Likewise. * testsuite/gas/elf/elf.exp: Run test for arc.
2016-04-14Fix copying Solaris binaries with objcopy.Nick Clifton2-4/+4
PR target/19938 bfd * elf-bbfd.h (struct elf_backend_data): New field: elf_strtab_flags. New field: elf_backend_set_special_section_info_and_link * elfxx-target.h (elf_backend_strtab_flags): Define if not already defined. (elf_backend_set_special_section_info_and_link): Define if not already defined. (elfNN_bed): Use elf_backend_set_special_section_info_and_link and elf_backend_strtab_flags macros to initialise fields in structure. * elf.c (_bfd_elf_make_section_from_shdr): Check for SHF_STRINGS being set even if SHF_MERGE is not set. (elf_fake_sections): Likewise. (section_match): New function. Matches two ELF sections based upon fixed characteristics. (find_link): New function. Locates a section in a BFD that matches a section in a different BFD. (_bfd_elf_copy_private_bfd_data): Copy the sh_info and sh_link fields of reserved sections. (bfd_elf_compute_section_file_positions): Set the flags for the .shstrtab section based upon the elf_strtab_flags field in the elf_backend_data structure. (swap_out_syms): Likewise for the .strtab section. * elflink.c (bfd_elf_final_link): Set the flags for the .strtab section based upon the elf_strtab_flags field in the elf_backend_data structure. * elf32-i386.c (elf32_i386_set_special_info_link): New function. (elf_backend_strtab_flags): Set to SHF_STRINGS for Solaris targets. (elf_backend_set_special_section_info_and_link): Define for Solaris targets. * elf32-sparc.c: Likewise. * elf64-x86-64.c: Likewise. binutils* testsuite/binutils-all/i386/compressed-1b.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/binutils-all/i386/compressed-1c.d: Likewise. * testsuite/binutils-all/readelf.s: Likewise. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/x86-64/compressed-1b.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1c.d: Likewise. gas * testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/gas/i386/x86-64-unwind.d: Likewise.
2016-04-13Fix disassembly of the V850's LD.BU instruction.Nick Clifton3-0/+33
PR target/19937 opcode * v850-opc.c (v850_opcodes): Correct masks for long versions of the LD.B and LD.BU instructions. gas * testsuite/gas/v850/pr19937.s: New test. * testsuite/gas/v850/pr19937.d: New test control file. * testsuite/gas/v850/basic.exp: Run the new test.
2016-04-13MIPS/GAS: Correct branch relaxation for weak symbolsMaciej W. Rozycki8-0/+103
Weak symbols can be preempted at link time so always choose the longer sequence in branch relaxation, according to the relaxation level chosen, so that any symbol finally used as the branch target is reachable. 2016-04-13 Maciej W. Rozycki <macro@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> gas/ * config/tc-mips.c (relaxed_branch_length): Use the long sequence where the target is a weak symbol. (relaxed_micromips_32bit_branch_length): Likewise. (relaxed_micromips_16bit_branch_length): Likewise. * testsuite/gas/mips/branch-weak-1.d: New test. * testsuite/gas/mips/branch-weak-2.d: New test. * testsuite/gas/mips/branch-weak-3.d: New test. * testsuite/gas/mips/branch-weak-4.d: New test. * testsuite/gas/mips/branch-weak-5.d: New test. * testsuite/gas/mips/branch-weak.l: New stderr output. * testsuite/gas/mips/branch-weak.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-13MIPS/GAS: Relax branches to symbols resolved at link timeMaciej W. Rozycki13-0/+170
Where branch relaxation is enabled emit the long sequence for branches whose distance cannot be determined, i.e. to symbols that are undefined or in a different segment. These symbols are only resolved at link time and therefore the longer sequence ensures the branch target is in range, which cannot be guaranteed with a direct branch. This is the opposite to the current implementation, originally proposed here: <https://sourceware.org/ml/binutils/2002-09/msg00218.html>. The proposal was then extensively discussed before the final version was posted here: <https://sourceware.org/ml/binutils/2002-10/msg00191.html> and eventually committed: commit 4a6a3df43dbb37853a7b88b10ae97d9ec5daf987 Author: Alexandre Oliva <aoliva@redhat.com> Date: Sat Oct 12 05:23:33 2002 +0000 The case considered here was not commented in the review however and the original version remains. With branch relaxation enabled it makes more sense to do it consistently, so that all code impure with respect to branch distances can be linked. Direct branches are still produced for the cases concerned where branch relaxation is disabled, which is the default. gas/ * config/tc-mips.c (relaxed_branch_length): Use the long sequence where the distance cannot be determined. (relaxed_micromips_32bit_branch_length): Likewise. * testsuite/gas/mips/branch-extern-1.d: New test. * testsuite/gas/mips/branch-extern-2.d: New test. * testsuite/gas/mips/branch-extern-3.d: New test. * testsuite/gas/mips/branch-extern-4.d: New test. * testsuite/gas/mips/branch-extern.l: New stderr output. * testsuite/gas/mips/branch-extern.s: New test source. * testsuite/gas/mips/branch-section-1.d: New test. * testsuite/gas/mips/branch-section-2.d: New test. * testsuite/gas/mips/branch-section-3.d: New test. * testsuite/gas/mips/branch-section-4.d: New test. * testsuite/gas/mips/branch-section.l: New stderr output. * testsuite/gas/mips/branch-section.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu11-3/+92
gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister.d: New file. * testsuite/gas/arc/textauxregister.s: Likewise. * testsuite/gas/arc/textcondcode.d: Likewise. * testsuite/gas/arc/textcondcode.s: Likewise. * testsuite/gas/arc/textcoreregister.d: Likewise. * testsuite/gas/arc/textcoreregister.s: Likewise. * testsuite/gas/arc/textpseudoop.d: Likewise. * testsuite/gas/arc/textpseudoop.s: Likewise. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/taux.d: Likewise. * doc/c-arc.texi (ARC Directives): Add .extCondCode, .extCoreRegister and .extAuxRegister documentation. * config/tc-arc.c (arc_extcorereg): New function. (md_pseudo_table): Add .extCondCode, .extCoreRegister and .extAuxRegister pseudo-ops. (extRegister_t): New type. (ext_condcode, arc_aux_hash): New global variable. (find_opcode_match): Check for extensions. (preprocess_operands): Likewise. (md_begin): Add aux registers in a hash. (assemble_insn): Update use arc_flags member. (tokenize_extregister): New function. (create_extcore_section): Likewise. * config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10. (arc_flags): Delete code, add flgp. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (flag_class_t): Update. (ARC_OPCODE_NONE): Define. (ARC_OPCODE_ARCALL): Likewise. (ARC_OPCODE_ARCFPX): Likewise. (ARC_REGISTER_READONLY): Likewise. (ARC_REGISTER_WRITEONLY): Likewise. (ARC_REGISTER_NOSHORT_CUT): Likewise. (arc_aux_reg): Add cpu. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format): Check for extension flags. (print_flags): New function. (print_insn_arc): Update for .extCondCode, .extCoreRegister and .extAuxRegister. * arc-ext.c (arcExtMap_coreRegName): Use LAST_EXTENSION_CORE_REGISTER. (arcExtMap_coreReadWrite): Likewise. (dump_ARC_extmap): Update printing. * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. (arc_aux_regs): Add cpu field. * arc-regs.h: Add cpu field, lower case name aux registers. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Update ARC instruction data-base.Claudiu Zissulescu4-0/+63
gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/noargs_a7.d: New file. * testsuite/gas/arc/noargs_a7.s: Likewise. * testsuite/gas/arc/noargs_hs.d: Likewise. * testsuite/gas/arc/noargs_hs.s: Likewise. opcode/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h: Add rtsc, sleep with no arguments. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu9-0/+230
gas/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textinsn-errors.d: New File. * testsuite/gas/arc/textinsn-errors.err: Likewise. * testsuite/gas/arc/textinsn-errors.s: Likewise. * testsuite/gas/arc/textinsn2op.d: Likewise. * testsuite/gas/arc/textinsn2op.s: Likewise. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * doc/c-arc.texi (ARC Directives): Add .extInstruction documentation. * config/tc-arc.c (arcext_section): New variable. (arc_extinsn): New function. (md_pseudo_table): Add .extInstruction pseudo op. (attributes_t): New type. (suffixclass, syntaxclass, syntaxclassmod): New constant structures. (find_opcode_match): Remove arc_num_opcodes. (md_begin): Likewise. (tokenize_extinsn): New function. (arc_set_ext_seg): Likewise. (create_extinst_section): Likewise. include/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (arc_num_opcodes): Remove. (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM) (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND) (ARC_SUFFIX_FLAG): Define. (flags_none, flags_f, flags_cc, flags_ccf): Declare. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. opcodes/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): Initialize. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. (arc_opcode arc_opcodes): Null terminate the array. (arc_num_opcodes): Remove. * arc-ext.h (INSERT_XOP): Define. (extInstruction_t): Likewise. (arcExtMap_instName): Delete. (arcExtMap_insn): New function. (arcExtMap_genOpcode): Likewise. * arc-ext.c (ExtInstruction): Remove. (create_map): Zero initialize instruction fields. (arcExtMap_instName): Remove. (arcExtMap_insn): New function. (dump_ARC_extmap): More info while debuging. (arcExtMap_genOpcode): New function. * arc-dis.c (find_format): New function. (print_insn_arc): Use find_format. (arc_get_disassembler): Enable dump_ARC_extmap only when debugging. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Remove unneeded AUX register symbols.Claudiu Zissulescu2-0/+379
gas/ 2016-03-31 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (preprocess_operands): Mark AUX symbol. (arc_adjust_symtab): New function. * config/tc-arc.h (ARC_FLAG_AUX): Define. (obj_adjust_symtab): Likewise. * testsuite/gas/arc/taux.d: New file. * testsuite/gas/arc/taux.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-09MIPS/GAS: Sanitize `.option picX' pseudo-opMaciej W. Rozycki5-0/+45
gas/ * config/tc-mips.c (s_option): Sanitize `.option picX' pseudo-op. * testsuite/gas/mips/option-pic-1.d: New test. * testsuite/gas/mips/option-pic-2.l: New list test. * testsuite/gas/mips/option-pic-1.s: New test source. * testsuite/gas/mips/option-pic-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09MIPS/GAS: Disallow `.option picX' with VxWorks PICMaciej W. Rozycki5-0/+20
gas/ * config/tc-mips.c (s_option): Reject `.option picX' if VxWorks PIC. * testsuite/gas/mips/option-pic-vxworks-1.l: New list test. * testsuite/gas/mips/option-pic-vxworks-2.l: New list test. * testsuite/gas/mips/option-pic-vxworks-1.s: New test source. * testsuite/gas/mips/option-pic-vxworks-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-08Fix regexps in PR19910 test to cope with COFF and AOUT sparc targets.Nick Clifton1-3/+4
PR target/19910 * testsuite/gas/sparc/pr19910-1.d: Adjust regexps to work with COFF and AOUT sparc targets.
2016-04-07arc/nps400: Add new instructionsAndrew Burgess2-0/+34
Add some new control instructions to the opcodes library, and a new test for these new instructions to the assembler. The new instructions use an instruction flag longer than any seen before (on arc), and so the max flag length is extended to accommodate this. gas/ChangeLog: * config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7. * testsuite/gas/arc/nps400-2.d: New file. * testsuite/gas/arc/nps400-2.s: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. * arc-opc.c (arc_flag_operands): Add new flags. (arc_flag_classes): Add new classes.
2016-04-07Allow integer contants to have a U suffix. Improve error reporting for ↵Nick Clifton6-2/+32
missing closing parentheses. PR gas/19910 * config/tc-sparc.c (sparc_ip): Report an error if the expression inside a %-macro could not be fully parsed. * expr.c (integer_constant): Accept and ignore U suffixes to integers. (operand): When a missing closing parenthesis is encountered, report the character that was found instead. * testsuite/gas/mips/tls-ill.l: Update expected error message. * testsuite/gas/sparc/pr19910-1.d: New test driver. * testsuite/gas/sparc/pr19910-1.s: New test. * testsuite/gas/sparc/pr19910-2.l: Expected error output. * testsuite/gas/sparc/pr19910-2.s: New test. * testsuite/gas/sparc/sparc.exp: Run the new tests.
2016-04-06Fix MSP430 assembler's detection of NOP and EINT.Nick Clifton2-6/+14
* config/tc-msp430.c (msp430_operands): Check for a NOP preceding an EINT instruction. Warn/fix as necessary. * testsuite/gas/msp430/bad.s: Add test of EINT without preceding NOP. * testsuite/gas/msp430/bad.l: Update expected messages.
2016-04-05arc/nps400: Add additional instructionsAndrew Burgess2-5/+133
Adds the movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16, and crc32 instructions for the nps400 arc machine type. gas/ChangeLog: * testsuite/gas/arc/nps400-1.d: Update expected results. * testsuite/gas/arc/nps400-1.s: Additional test cases. opcodes/ChangeLog: * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16, and crc32 instructions. * arc-opc.c (arc_flag_operands): Add F_NPS_R. (arc_flag_classes): Add C_NPS_R. (insert_nps_bitop_size_2b): New function. (extract_nps_bitop_size_2b): Likewise. (insert_nps_bitop_uimm8): Likewise. (extract_nps_bitop_uimm8): Likewise. (arc_operands): Add new operand entries.
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu3-0/+78
opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Add a new subclass field. Add double assist accumulator register values. * arc-tbl.h: Use DPA subclass to mark the double assist instructions. Use DPX/SPX subclas to mark the FPX instructions. * arc-opc.c (RSP): Define instead of SP. (arc_aux_regs): Add the subclass field. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (DPA, DPX, SPX): New subclass enums. (ARC_FPUDA): Define. (arc_aux_reg): Add new field. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (is_code_density_p): Compare directly the subclass field. (is_spfp_p, is_dpfp_p, is_spfp_p): Define. (check_cpu_feature): New function. (find_opcode_match): Use check_cpu_feature function. (preprocess_operands): Likewise. (md_parse_option): Use mfpuda, mdpfp, mspfp options. * testsuite/gas/arc/tdpfp.d: New file. * testsuite/gas/arc/tfpuda.d: Likewise. * testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05[ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar)Jiong Wang8-0/+145
gas/ * config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16. * testsuite/gas/arm/armv8-2-fp16-simd.s: New tests. * testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results. * testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results. * testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source. * testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase. * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise for Thumb. * testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results. opcodes/ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
2016-04-05[ARC] Don't allow pc-rel relocations for J* instructions.Claudiu Zissulescu3-0/+15
gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for JUMP instructions type. * testsuite/gas/arc/relocs-errors.d: New file. * testsuite/gas/arc/relocs-errors.err: Likewise. * testsuite/gas/arc/relocs-errors.s: Likewise.
2016-04-04Don't use vec_disp8 encoding with the .d32 suffixH.J. Lu4-8/+19
Since the .d32 suffix prefers 32-bit displacement in encoding, try vec_disp8 encoding only if i.disp_encoding != disp_encoding_32bit. PR gas/19909 * config/tc-i386.c (check_VecOperands): Try vec_disp8 encoding only if i.disp_encoding != disp_encoding_32bit. * gas/testsuite/gas/i386/disp32.s: Add tests for vmovdqu64.d32. * gas/testsuite/gas/i386/x86-64-disp32.s: Likewise. * gas/testsuite/gas/i386/disp32.d: Updated. * gas/testsuite/gas/i386/x86-64-disp32.d: Likewise.
2016-04-04Add a testcase for PR gas/19498H.J. Lu3-0/+22
PR gas/19498 * testsuite/gas/i386/i386.exp: Run pr19498. * testsuite/gas/i386/pr19498.d: New file. * testsuite/gas/i386/pr19498.s: Likewise.
2016-03-30[ARC] Allow equ redefintion tests for ARC.Claudiu Zissulescu3-3/+3
gas/ 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/all/gas.exp: Don't xfail on ARC. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/all/redef3.d: Allow execution for ARC.
2016-03-30[ARC] Fix warn.exp test error.Claudiu Zissulescu1-1/+1
gas/ 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/warn.exp: Fix matching pattern.
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu4-0/+175
gas/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/ext2op.d: New file. * testsuite/gas/arc/ext2op.s: Likewise. * testsuite/gas/arc/ext3op.d: Likewise. * testsuite/gas/arc/ext3op.s: Likewise. opcodes/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (invld07): Remove. * arc-ext-tbl.h: New file. * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. * arc-opc.c (arc_opcodes): Add ext-tbl include. include/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass. (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP) (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL) (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU) (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS) (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL) (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC) (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC) (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU) (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS) (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL) (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C) (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL) (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess4-0/+47
Adds the first few nps400 instructions. gas/ChangeLog: * testsuite/gas/arc/nps400-0.d: New file. * testsuite/gas/arc/nps400-0.s: New file. * testsuite/gas/arc/nps400-1.d: New file. * testsuite/gas/arc/nps400-1.s: New file. include/ChangeLog: * opcodes/arc.h (insn_class_t): Add BITOP type. opcodes/ChangeLog: * arc-nps400-tbl.h: New file. * arc-opc.c: Add top level comment. (insert_nps_3bit_dst): New function. (extract_nps_3bit_dst): New function. (insert_nps_3bit_src2): New function. (extract_nps_3bit_src2): New function. (insert_nps_bitop_size): New function. (extract_nps_bitop_size): New function. (arc_flag_operands): Add nps400 entries. (arc_flag_classes): Add nps400 entries. (arc_operands): Add nps400 entries. (arc_opcodes): Add nps400 include.
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess3-0/+10
When parsing the operand instruction flags we don't currently detect the case where multiple flags are provided from the same class set, these will be accepted and the bit values merged together, resulting in the wrong instruction being assembled. For example: adc.n.eq r0,r0,r2 Will assemble without error, yet, upon disassembly, the instruction will actually be: adc.c r0,r0,r2 In a later commit the concept of required flags will be introduced. Required flags are just like normal instruction flags, except that they must be present for the instruction to match. Adding this will allow for simpler instructions in the instruction table, and allow for more sharing of operand extraction and insertion functions. To solve both of the above issues (multiple flags being invalid, and required flags), this commit reworks the flag class mechanism. Currently the flag class is never used. Each instruction can reference multiple flag classes, each flag class has a class type and a set of flags. However, at present, the class type is never used. The current values identify the type of instruction that the flag will be used in, but this is not required information. Instead, this commit discards the old flag classes, and introduces 3 new classes. The first F_CLASS_NONE, is just a NULL marker value, and is only used in the NULL marker flag class. The other two flag classes are F_FLAG_OPTIONAL, and F_FLAG_REQUIRED. The class F_FLAG_OPTIONAL has the property that at most one of the flags in the flag set for that class must be present in the instruction. The "at most" one means that no flags being present is fine. The class F_FLAG_REQUIRED is not currently used, but will be soon. With this class, exactly one of the flags from this class must be present in the instruction. If the flag class contains a single flag, then of course that flag must be present. However, if the flag class contained two or more, then one, and only one of them must be present. gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Move lnflg, and i declarations to start of block. Reset code on all flags before attempting to match them. Handle multiple hits on the same flag. Handle flag class. * testsuite/gas/arc/asm-errors.d: New file. * testsuite/gas/arc/asm-errors.err: New file. * testsuite/gas/arc/asm-errors.s: New file. include/ChangeLog: * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3 new classes instead. opcodes/ChangeLog: * arc-opc.c (arc_flag_classes): Convert all flag classes to use the new class enum values.
2016-03-21gas/arc: Fix test for big-endian arcAndrew Burgess2-0/+10
The inline-data test checks the specific bytes laid down by the assembler, and so relies on the endianness of the target. I could change the expected results to be endian agnostic, however, I worried that a bug in the assembler that gets the endianness wrong would then slip through. Instead I add a new test for big-endian arc, and restrict the existing test to little-endian arc. gas/ChangeLog: * testsuite/gas/arc/inline-data-1.d: Add target restriction. * testsuite/gas/arc/inline-data-2.d: New file.
2016-03-18Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.Nick Clifton2-0/+15
PR target/19721 opcodes * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand of MOV insn that aliases an ORR insn. gas * testsuite/gas/aarch64/pr19721.s: New test source file. * testsuite/gas/aarch64/pr19721.d: New test driver file.
2016-03-17testsuite/ChangeLog is no longer supposed to existAlan Modra1-13/+0
move entries to main ChangeLog
2016-03-16[ARM] Support ARMv8.2 FP16 simd instructionsJiong Wang6-0/+663
gas/ * config/tc-arm.c (N_S_32): New. (N_F_16_32): Likewise. (N_SUF_32): Support N_F16. (N_IF_32): Likewise. (neon_dyadic_misc): Likewise. (do_neon_cmp): Likewise. (do_neon_cmp_inv): Likewise. (do_neon_mul): Likewise. (do_neon_fcmp_absolute): Likewise. (do_neon_step): Likewise. (do_neon_abs_neg): Likewise. (CVT_FLAVOR_VAR): Likewise. (do_neon_cvt_1): Likewise. (do_neon_recip_est): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (neon_check_type): Check architecture support for FP16 extension. (insns): Update comments. * testsuite/gas/arm/armv8-2-fp16-simd.s: New test source. * testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection error file. opcode/ * arm-dis.c (neon_opcodes): Support new FP16 instructions.
2016-03-16Fix checking bignum values that are being inserted into byte sized containers.Nick Clifton3-4/+42
* read.c (emit_expr_with_reloc): Add code check a bignum with nbytes == 1. * config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes other than 32-bits. * testsuite/gas/elf/bignum.s: New test source file. * testsuite/gas/elf/bignum.d: New test driver file. * testsuite/gas/elf/elf.exp: Run the new test.
2016-03-10PR gas/19744: Thumb-1 pcrop relocations don't work on Thumb-2 targetsMickael Guene5-0/+66
gas/ * config/tc-arm.c (do_arit): Protect against bad relocations usage. (do_mov): Likewise. (do_t_add_sub): Allow pcrop relocations for Thumb-2 targets. (do_t_mov_cmp): Likewise. (do_t_add_sub): Protect against bad relocations usage. (do_t_mov_cmp): Likewise. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local-armv7-m.s: New. * gas/arm/adds-thumb1-reloc-local-armv7-m.d: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.s: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.d: New. ld/ * testsuite/ld-arm/arm-elf.exp: New tests. * testsuite/ld-arm/thumb1-adds-armv7-m.s: New. * testsuite/ld-arm/thumb1-movs-armv7-m.s: New.
2016-03-08[ARC] Allow non-instruction relocations within .text sectionsClaudiu Zissulescu2-0/+11
bfd/ 2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com> Andrew Burgess <andrew.burgess@embecosm.com> * elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32. (arc_bfd_put_32): Becomes an alias for bfd_put_32. (arc_elf_howto_init): Added assert to validate relocations. (get_middle_endian_relocation): Delete. (middle_endian_convert): New function. (ME): Redefine, now does nothing. (IS_ME): New define. (arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO' definition to call middle_endian_convert. Add a new local variable and make use of this throughout. Added call to arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations. gas/ 2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com> * testsuite/gas/arc/inline-data-1.d: New file. * testsuite/gas/arc/inline-data-1.s: New file. include/ 2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com> Andrew Burgess <andrew.burgess@embecosm.com> * elf/arc-reloc.def: Add a call to ME within the formula for each relocation that requires middle-endian correction.
2016-03-04[ARM] Build attributes for ARMv8.1-A AdvSIMDMatthew Wahab2-0/+36
binutils/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * readelf.c (arm_attry_tag_FP_arch): Add "NEON for ARMv8.1". gas/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (aeabi_set_public_attributes): Emit attribute for ARMv8.1 AdvSIMD use. * testsuite/gas/arm/attr-march-armv8-a+rdma.d: New. * testsuite/gas/arm/attr-march-armv8_1-a+simd.d: New. Change-Id: I3c356e0681b97df2f9c0dabd7c0fd1b441cc2755
2016-03-04[ARM] Add feature check for ARMv8.1 AdvSIMD instructions.Matthew Wahab5-33/+182
gas/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA feature. (record_feature_use): New. (mark_feature_used): Use record_feature_use. (do_neon_qrdmlah): New. (insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and variants. (arm_extensions): Put into alphabetical order. Re-indent "simd" and "rdma" entries. Fix the incorrect merge value for "+rdma". * testsuite/gas/arm/armv8-a+rdma-warning.d: New. * testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options. Make source file explicit. * testsuite/gas/arm/armv8-a+rdma.l: New. * testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension directives. Fix white-space. * testsuite/gas/arm/armv8_1-a+simd.d: New. include/opcode 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA. (ARM_CPU_HAS_FEATURE): Add comment. Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
2016-03-02Adjust testsuite/gas/i386/x86_64-intel.d for COFFH.J. Lu1-1/+1
* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
2016-02-29[ARC] Local symbols relocation cleanupClaudiu Zissulescu4-35/+33
bfd/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> * elf32-arc.c (elf_arc_relocate_section): Added rules to fix the relocation addend when sections get merged. gas/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> * config/tc-arc.c (arc_extra_reloc): Change size to 0. (tc_arc_fix_adjustable): Changed default return value to 1. * testsuite/gas/arc/j.d: Updated expected symbol * testsuite/gas/arc/jl.d: Likewise * testsuite/gas/arc/relax-avoid1.d: Likewise * testsuite/gas/arc/st.d: Likewise ld/ 2016-02-29 Cupertino Miranda <cmiranda@synopsys.com> * testsuite/ld-elf/merge.d: Removed xfail for ARC. * testsuite/ld-elf/merge2.d: Likewise. * testsuite/ld-elf/merge3.d: Likewise.
2016-02-26Properly implement STT_COMMONH.J. Lu12-6/+251
The BFD configure option, --enable-elf-stt-common, can't be to used to verify STT_COMMON implementation with the normal binutils build. Instead, this patch removes it from BFD. It adds --elf-stt-common=[no|yes] to ELF assembler/objcopy and adds -z common/-z nocommon to ld. A configure option, --enable-elf-stt-common, is added to gas to specify whether ELF assembler should generate common symbols with the STT_COMMON type by default. Since BSF_KEEP_G is never used, it is renamed to BSF_ELF_COMMON for ELF common symbols. bfd/ PR ld/19645 * bfd.c (bfd): Change flags to 20 bits. (BFD_CONVERT_ELF_COMMON): New. (BFD_USE_ELF_STT_COMMON): Likewise. (BFD_FLAGS_SAVED): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. (BFD_FLAGS_FOR_BFD_USE_MASK): Likewise. * configure.ac: Remove --enable-elf-stt-common. * elf.c (swap_out_syms): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. * elfcode.h (elf_slurp_symbol_table): Set BSF_ELF_COMMON for STT_COMMON. * elflink.c (bfd_elf_link_mark_dynamic_symbol): Also check STT_COMMON. (elf_link_convert_common_type): New function. (elf_link_output_extsym): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. Set sym.st_info after sym.st_shndx. * elfxx-target.h (TARGET_BIG_SYM): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON to object_flags. (TARGET_LITTLE_SYM): Likewise. * syms.c (BSF_KEEP_G): Renamed to ... (BSF_ELF_COMMON): This. * bfd-in2.h: Regenerated. * config.in: Likewise. * configure: Likewise. binutils/ PR ld/19645 * NEWS: Mention --elf-stt-common= for objcopy. * doc/binutils.texi: Document --elf-stt-common= for objcopy. * objcopy.c (do_elf_stt_common): New. (command_line_switch): Add OPTION_ELF_STT_COMMON. (copy_options): Add --elf-stt-common=. (copy_usage): Add --elf-stt-common=. (copy_object): Also check do_elf_stt_common for ELF targets. (copy_file): Handle do_elf_stt_common. (copy_main): Handle OPTION_ELF_STT_COMMON. * readelf.c (apply_relocations): Support STT_COMMON. * testsuite/binutils-all/common-1.s: New file. * testsuite/binutils-all/common-1a.d: Likewise. * testsuite/binutils-all/common-1b.d: Likewise. * testsuite/binutils-all/common-1c.d: Likewise. * testsuite/binutils-all/common-1d.d: Likewise. * testsuite/binutils-all/common-1e.d: Likewise. * testsuite/binutils-all/common-1f.d: Likewise. * testsuite/binutils-all/common-2.s: Likewise. * testsuite/binutils-all/common-2a.d: Likewise. * testsuite/binutils-all/common-2b.d: Likewise. * testsuite/binutils-all/common-2c.d: Likewise. * testsuite/binutils-all/common-2d.d: Likewise. * testsuite/binutils-all/common-2e.d: Likewise. * testsuite/binutils-all/common-2f.d: Likewise. * testsuite/binutils-all/objcopy.exp (objcopy_test_elf_common_symbols): New proc. Run objcopy_test_elf_common_symbols for ELF targets gas/ PR ld/19645 * NEWS: Mention --enable-elf-stt-common and --elf-stt-common= for ELF assemblers. * as.c (flag_use_elf_stt_common): New. (show_usage): Add --elf-stt-common=. (option_values): Add OPTION_ELF_STT_COMMON. (std_longopts): Add --elf-stt-common=. (parse_args): Handle --elf-stt-common=. * as.h (flag_use_elf_stt_common): New. * config.in: Regenerated. * configure: Likewise. * configure.ac: Add --enable-elf-stt-common and define DEFAULT_GENERATE_ELF_STT_COMMON. * gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set. * doc/as.texinfo: Document --elf-stt-common=. * testsuite/gas/elf/common3.s: New file. * testsuite/gas/elf/common3a.d: Likewise. * testsuite/gas/elf/common3b.d: Likewise. * testsuite/gas/elf/common4.s: Likewise. * testsuite/gas/elf/common4a.d: Likewise. * testsuite/gas/elf/common4b.d: Likewise. * testsuite/gas/i386/dw2-compress-3b.d: Likewise. * testsuite/gas/i386/dw2-compressed-3b.d: Likewise. * testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a and common4b. * testsuite/gas/i386/dw2-compress-3.d: Renamed to ... * testsuite/gas/i386/dw2-compress-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/dw2-compressed-3.d: Renamed to ... * testsuite/gas/i386/dw2-compressed-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/i386.exp: Run dw2-compress-3a, dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead of dw2-compress-3 and dw2-compressed-3. include/ PR ld/19645 * bfdlink.h (bfd_link_elf_stt_common): New enum. (bfd_link_info): Add elf_stt_common. ld/ PR ld/19645 * NEWS: Mention -z common/-z nocommon for ELF targets. * emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle -z common and -z nocommon. * ld.texinfo: Document -z common/-z nocommon. * lexsup.c (elf_shlib_list_options): Add -z common/-z nocommon. * testsuite/ld-elf/tls_common.exp: Test --elf-stt-common=no and --elf-stt-common=yes with assembler. * testsuite/ld-elfcomm/common-1.s: New file. * testsuite/ld-elfcomm/common-1a.d: Likewise. * testsuite/ld-elfcomm/common-1b.d: Likewise. * testsuite/ld-elfcomm/common-1c.d: Likewise. * testsuite/ld-elfcomm/common-1d.d: Likewise. * testsuite/ld-elfcomm/common-1e.d: Likewise. * testsuite/ld-elfcomm/common-1f.d: Likewise. * testsuite/ld-elfcomm/common-2.s: Likewise. * testsuite/ld-elfcomm/common-2a.d: Likewise. * testsuite/ld-elfcomm/common-2b.d: Likewise. * testsuite/ld-elfcomm/common-2c.d: Likewise. * testsuite/ld-elfcomm/common-2d.d: Likewise. * testsuite/ld-elfcomm/common-2e.d: Likewise. * testsuite/ld-elfcomm/common-2f.d: Likewise. * testsuite/ld-elfcomm/common-3a.rd: Likewise. * testsuite/ld-elfcomm/common-3b.rd: Likewise. * testsuite/ld-i386/pr19645.d: Likewise. * testsuite/ld-i386/pr19645.s: Likewise. * testsuite/ld-x86-64/largecomm-1.s: Likewise. * testsuite/ld-x86-64/largecomm-1a.d: Likewise. * testsuite/ld-x86-64/largecomm-1b.d: Likewise. * testsuite/ld-x86-64/largecomm-1c.d: Likewise. * testsuite/ld-x86-64/largecomm-1d.d: Likewise. * testsuite/ld-x86-64/largecomm-1e.d: Likewise. * testsuite/ld-x86-64/largecomm-1f.d: Likewise. * testsuite/ld-x86-64/pr19645.d: Likewise. * testsuite/ld-x86-64/pr19645.s: Likewise. * testsuite/ld-elfcomm/elfcomm.exp: Test --elf-stt-common=yes with assembler. (assembler_generates_commons): Removed. Run -z common/-z nocommon tests. Run *.d tests. * testsuite/ld-i386/i386.exp: Run pr19645. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/dwarfreloc.exp: Test --elf-stt-common with assembler. Test STT_COMMON with readelf.
2016-02-25gas: Update tests for big-endian arc targetsAndrew Burgess3-3/+3
Some gas tests are excluded for arc targets using the pattern arc-*-*, however this only covers little endian arc targets. This commit extends the patter to cover big endian arc targets, the pattern is now arc*-*-*. gas/ChangeLog: * testsuite/gas/all/gas.exp: Change target pattern to cover arceb-*. * testsuite/gas/all/redef3.d: Likewise. * testsuite/gas/elf/elf.exp: Likewise.
2016-02-24[GAS][ARM][3/3]Add armv8.2 fp16 scalar instruction support. Based on SE_H ↵Renlin Li6-0/+532
instruction shape. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (BAD_FP16): New error message macro. (do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2 fp16 scalar instructions. (neon_check_type): Allow different size from key. (do_vfp_nsyn_add_sub): Add support SE_H shape support. (try_vfp_nsyn): Likewise. (do_vfp_nsyn_mla_mls): Likewise. (do_vfp_nsyn_fma_fms): Likewise. (do_vfp_nsyn_ldm_stm): Likewise (do_vfp_nsyn_sqrt): Likewise (do_vfp_nsyn_div): Likewise (do_vfp_nsyn_nmul): Likewise. (do_vfp_nsyn_cmp): Likewise. (do_neon_shll): Likewise. (do_vfp_nsyn_cvt_fpv8): Likewise. (do_neon_cvttb_2): Likewise. (do_neon_mov): Likewise. (do_neon_rshift_round_imm): Likewise. (do_neon_ldr_str): Likewise. (do_vfp_nsyn_fpv8): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (insns): New entry for vins, vmovx. (md_apply_fix): Left shift 1 bit for fp16 vldr/vstr. * testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New. * testsuite/gas/arm/armv8-2-fp16-scalar.d: New. * testsuite/gas/arm/armv8-2-fp16-scalar.s: New. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New * testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
2016-02-24[OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.Renlin Li2-3/+3
opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. (print_insn_coprocessor): Support fp16 instruction. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.d: Adjust output. * testsuite/gas/arm/copro.s: Adjust co-processor num.
2016-02-24[OPCODES][ARM]Fix mask for a few coprocessor opcodes.Renlin Li2-0/+45
opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm, vrint(mpna). gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/mask_1.d: New. * testsuite/gas/arm/mask_1.s: New.
2016-02-24[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ↵Renlin Li2-2/+3
ldc/ldc2, stc/stc2 opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (print_insn_coprocessor): Check co-processor number for cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11. * testsuite/gas/arm/copro.d: Update.
2016-02-23Skip tests for common directive on hpuxH.J. Lu1-2/+5
hpux has a non-standard common directive. * testsuite/gas/elf/elf.exp: Skip tests for common directive on hpux.
2016-02-20[i386] Check RegVRex in register_numberH.J. Lu3-0/+6
Increment register number by 16 if RegVRex is set. * config/tc-i386.c (register_number): Check RegVRex. * testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd with %zmm19 and %zmm3. * testsuite/gas/i386/x86-64-avx512f-intel.d: Updated. * testsuite/gas/i386/x86-64-avx512f.d: Likewise.
2016-02-17xtensa: fix .init/.fini literals movingMax Filippov3-0/+44
Despite the documentation and the comment in xtensa_move_literals, in the presence of --text-section-literals and --auto-litpools literals are moved from the separate literal sections into .init and .fini, because the check in the xtensa_move_literals is incorrect. This moving was broken with introduction of auto litpools: some literals now may be lost. This happens because literal frags emitted from .init and .fini are not closed when new .literal_position marks new literal pool. Then frag_align(2, 0, 0) changes type of the last literal frag to rs_align. rs_align frags are skipped in the xtensa_move_literals. As a result fixups against such literals are not moved out of .init.literal/ .fini.literal sections producing the following assembler error: test.S: Warning: fixes not all moved from .init.literal test.S: Internal error! Fix check for .init.literal/.fini.literal in the xtensa_move_literals and don't let it move literals from there in the presence of --text-section-literals or --auto-litpools. 2016-02-17 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (xtensa_move_literals): Fix check for .init.literal/.fini.literal section name. * testsuite/gas/xtensa/all.exp: Add init-fini-literals to the list of xtensa tests. * testsuite/gas/xtensa/init-fini-literals.d: New file: init-fini-literals test result patterns. * testsuite/gas/xtensa/init-fini-literals.s: New file: init-fini-literals test.
2016-02-16[ARC] Enable .cfi_* pseudo-ops.Claudiu Zissulescu4-1/+58
gas/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (tc_arc_frame_initial_instructions): New function. (tc_arc_regname_to_dw2regnum): Likewise. * config/tc-arc.h (TARGET_USE_CFIPOP): Define (tc_cfi_frame_initial_instructions): Likewise. (tc_regname_to_dw2regnum): Likewise. gas/testsuite 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * gas/cfi/cfi-arc-1.d: New file. * gas/cfi/cfi-arc-1.s: Likewise. * gas/cfi/cfi.exp: Allow running tests for arc. binutils/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (is_32bit_pcrel_reloc): Add R_ARC_32_PCREL.
2016-02-16[PR19620][GAS][AArch64]Remove mov[z,k,n] relocation symbol name restriction.Renlin Li2-0/+32
In AArch64 gas, register name or string starts with valid register name is not allowed as symbol name for mov[z,k,n] instruction. This patch removes the restriction. gas/ PR gas/19620 * config/tc-aarch64.c (parse_half): Remove restrictions on symbol name. * testsuite/gas/aarch64/movw_label.d: New. * testsuite/gas/aarch64/movw_label.s: New.
2016-02-15Correct opcode generated for RX indirect MOVs without an offset.Vinay Kumar G4-5/+52
PR gas/19665 * config/rx-parse.y (MOV): Opcode generation for index register addressing mode. * testsuite/gas/rx/rx.exp: Updated for new testcase. * testsuite/gas/rx/pr19665.s: New file. * testsuite/gas/rx/pr19665.s: New file. * testsuite/gas/rx/mov.d: Update expected output.
2016-02-15Enhance GAS's .section directive so that it can take numeric values for the ↵Nick Clifton6-10/+77
flags and type fields. (ELF only) gas * doc/as.texinfo (.section): Document that numeric values can now be used for the flags and type fields of the ELF target's .section directive. Add notes about the restrictions on setting flags and types. * config/obj-elf.c (obj_elf_change_section): Allow known sections to be given processor specific section types. Allow processor and application specific flags of a section to be set after definition. (obj_elf_parse_section_letters): Handle parsing numeric values. (obj_elf_section_type): Handle parsing numeric values. (obj_elf_section): Allow numeric type values. * config/obj-elf.h (obj_elf_change_section): Update prototype. * testsuite/gas/elf/section10.d: New test. * testsuite/gas/elf/section10.s: Source file for new test. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise. * NEWS: Mention the new feature. bfd * elf-bfd.h (struct bfd_elf_special_section): Use unsigned values for length and type fields. Use a signed value for the suffix_length field. binutils* readelf.c (get_section_type_name): Add hex prefix to offsets printed for LOPROC and LOOS values. Ensure that a result is always returned for the V850 target, even when an unrecognised processor specific value is encountered. (process_section_headers): Display key values in the order in which they appear to the user. Add the "C (compressed)" value to the list. ld * testsuite/ld-i386/pr12718.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/ld-i386/pr12921.d: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic.rd: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-sh/tlsbin-2.d: Likewise. * testsuite/ld-sh/tlspic-2.d: Likewise. * testsuite/ld-tic6x/common.d: Likewise. * testsuite/ld-tic6x/shlib-1.rd: Likewise. * testsuite/ld-tic6x/shlib-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-noindex.rd: Likewise. * testsuite/ld-tic6x/static-app-1.rd: Likewise. * testsuite/ld-tic6x/static-app-1b.rd: Likewise. * testsuite/ld-tic6x/static-app-1r.rd: Likewise. * testsuite/ld-tic6x/static-app-1rb.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/ilp32-4.d: Likewise. * testsuite/ld-x86-64/pr12718.d: Likewise. * testsuite/ld-x86-64/pr12921.d: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/split-by-file.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic.rd: Likewise. * testsuite/ld-xtensa/tlsbin.rd: Likewise. * testsuite/ld-xtensa/tlspic.rd: Likewise.
generated by cgit v1.1 at 2025-02-02 18:33:36 +0000