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AgeCommit message (Expand)AuthorFilesLines
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig2-0/+611
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AA...Nick Clifton1-2/+2
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu5-0/+258
2017-03-08Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner1-2/+2
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner2-2/+4
2017-03-06Add support for Intel CET instructionsH.J. Lu7-0/+197
2017-03-06Update x86-64-mpx-inval-2 test for COFFH.J. Lu2-4/+7
2017-03-05gas: Emit name, comp_dir and producer strings in .debug_str.Mark Wielaard1-3/+4
2017-03-02GAS: Fix bogus "attempt to move .org backwards" relaxation errorsMaciej W. Rozycki46-0/+353
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich13-192/+244
2017-02-28MIPS/BFD: Also handle `jalr $0, $25' with R_MIPS_JALRMaciej W. Rozycki6-6/+137
2017-02-25Testsuite fixes for hppa64-hpuxAlan Modra1-7/+13
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford4-3/+5053
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford2-0/+49
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich6-0/+23
2017-02-24gas: test cases for the architecture level aware SPARC ASI work.Sheldon Lobo5-0/+13
2017-02-23MIPS/BFD: Discard ineligible JALR relocations right awayMaciej W. Rozycki5-0/+148
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel4-6/+401
2017-02-23gas: slightly relax .startof.()/.sizeof.() testcaseJan Beulich1-5/+2
2017-02-23x86: extend 64-bit invalid MPX insn forms testcaseJan Beulich2-171/+219
2017-02-22GAS: Consistently fix labels at the `.end' pseudo-opMaciej W. Rozycki5-0/+81
2017-02-22Fix gas/all/err-sizeof.s for cris*-*-*Hans-Peter Nilsson1-1/+1
2017-02-22Skip ARM vcmp-noprefix-imm test on non-ELF targetsNick Clifton1-0/+1
2017-02-22gas: require an operand to .startof.()/.sizeof.()Jan Beulich1-0/+21
2017-02-17GAS: Add ECOFF `.aent' pseudo-op supportMaciej W. Rozycki4-1/+47
2017-02-15[AArch64] Add SVE system registersRichard Sandiford4-0/+78
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu26-0/+290
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta1-1/+1
2017-02-14Fix powerpc testsuite source errorsAlan Modra3-22/+22
2017-02-13[ARM] Allow immediate without prefix in unified syntax for VCMPThomas Preud'homme2-0/+15
2017-02-10POWER9 add scv/rfscv instruction supportNicholas Piggin2-0/+6
2017-01-30MIPS: Add options to control branch ISA checksMaciej W. Rozycki7-0/+174
2017-01-30MIPS/GAS/testsuite: Convert branch local list tests to dump testsMaciej W. Rozycki7-12/+24
2017-01-27Fix disassembling of TIC6X parallel instructions where the previous fetch pac...Alexis Deruell2-0/+85
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton1-3/+3
2017-01-18PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sectionsMaciej W. Rozycki3-0/+71
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy2-0/+26
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist7-0/+402
2017-01-10Fix sleb128-8 regressions.Tristan Gingold2-2/+2
2017-01-10This patch ensure same output for sleb128 with large number.Tristan Gingold3-0/+10
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy3-0/+21
2017-01-02Update year range in copyright notice of all files.Alan Modra177-177/+177
2016-12-31PRU GAS PortDimitar Dimitrov22-0/+478
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki5-0/+71
2016-12-23MIPS16/GAS: Clean up invalid unextended operand handlingMaciej W. Rozycki7-0/+222
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki23-43/+1096
2016-12-23MIPS16/GAS: Fix forced size suffixes with argumentless instructionsMaciej W. Rozycki3-0/+27
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki3-0/+44
2016-12-21Remove high bit set charactersAlan Modra1-5/+5
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki14-0/+1664
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