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AgeCommit message (Expand)AuthorFilesLines
2016-12-02[ARC] Sync cpu names with the ones accepted by GCC.Claudiu Zissulescu6-0/+27
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu2-1/+10
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar3-0/+29
2016-11-27Fix spelling in comments in Expect scripts (gas)Ambrogino Modigliani7-11/+11
2016-11-27Fix spelling in comments in Assembler files (gas)Ambrogino Modigliani12-13/+13
2016-11-27Fix spelling in comments in C source files (gas)Ambrogino Modigliani2-6/+6
2016-11-25gas: fix CBCOND diagnostics for invalid immediate operands.Jose E. Marchesi3-0/+9
2016-11-23gas: run the hwcaps-bump tests with 64-bit sparc objects only.Jose E. Marchesi1-1/+1
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi3-0/+8
2016-11-22[ARC] Fix printing 'b' mnemonics.Claudiu Zissulescu1-2/+2
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra1-73/+73
2016-11-21[GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL s...Renlin Li2-0/+16
2016-11-18[ARC] Fix and extend features of .cpu directive.Claudiu Zissulescu6-0/+43
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy5-0/+113
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy5-0/+85
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy8-0/+50
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy5-0/+126
2016-11-11Accept L and LL suffixes to integer constants.Nick Clifton3-0/+18
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy2-0/+35
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2-0/+5
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy2-0/+68
2016-11-11[AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy4-0/+73
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy3-13/+88
2016-11-11[AArch64] Fix feature dependencies for +simd and +cryptoSzabolcs Nagy5-0/+37
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu7-72/+5
2016-11-09X86: Update opcode-suffix.dH.J. Lu1-0/+8
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu3-0/+16
2016-11-04arc/nps400: Validate address type operands correctlyAndrew Burgess2-0/+46
2016-11-04S/390: Fix 16 bit pc relative relocs.Andreas Krebbel2-3/+13
2016-11-03[ARC] Fix ldbit test on 32-bit systemsGraham Markall2-7/+7
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall2-0/+95
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu3-0/+25
2016-11-03[ARM] Allow MOV/MOV.W to accept all possible immediatesJiong Wang8-1/+23
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist13-0/+736
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist21-0/+1069
2016-11-01Add support for RISC-V architecture.Nick Clifton5-4/+42
2016-10-27gas/arc: Don't rely on bfd list of cpu type for cpu selectionAndrew Burgess1-0/+1
2016-10-21X86: Remove pcommit instructionH.J. Lu7-80/+0
2016-10-20Check invalid mask registersH.J. Lu3-0/+23
2016-10-19[GAS][ARM]Generate unpredictable warning for pc used in data processing instr...Renlin Li3-0/+80
2016-10-17Fixed matching in newly added test.Cupertino Miranda1-1/+1
2016-10-17Removed pseudo invalid instructions opcodes.Cupertino Miranda2-0/+16
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu4-0/+40
2016-10-11Enhance objdump so that it will use .got, .plt and .plt.got section symbols w...Nick Clifton1-2/+2
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang1-17/+17
2016-10-10MIPS64: Adjust cfi* testcases.Andreas Krebbel9-17/+17
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang2-0/+155
2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu4-0/+58
2016-10-06Refine .cfi_sections check to only consider compact eh_frameMatthew Fortune3-0/+28
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2-0/+15
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