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2008-09-11gas/testsuite/H.J. Lu5-32/+2519
2008-09-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse2avx.s: Remove pclmulXXX tests. Add tests for Intel syntax. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/sse2avx.d: Updated. * gas/i386/x86-64-sse2avx.d: Likewise. opcodes/ 2008-09-11 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd]. * i386-tbl.h: Regenerated.
2008-09-09gas/Peter Bergner8-1/+511
* config/tc-ppc.c (ppc_setup_opcodes): Simplify POWER4/NOPOWER4 test. Remove POWER5 and POWER6 tests. gas/testsuite/ * gas/ppc/common.s: New test. * gas/ppc/common.d: Likewise. * gas/ppc/power4_32.s: Likewise. * gas/ppc/power4_32.d: Likewise. * gas/ppc/power6.s: Add attn, mtcr, mtcrf, mfcr, dcbz. * gas/ppc/power6.d: Likewise. * gas/ppc/ppc.exp: Run power4_32 test.
2008-09-06gas/Richard Sandiford4-0/+24
* config/tc-mips.h (DWARF2_FDE_RELOC_SIZE): Define. gas/testsuite/ * gas/mips/cfi-n64-1.s, gas/mips/cfi-n64-1.d: New test. * gas/mips/mips.exp: Run it.
2008-09-05 * gas/arm/abs12.d: Update expected disassembly.Nick Clifton15-17/+35
* gas/arm/tls_vxworks.d: Likewise. * gas/arm/unwind_vxworks.d: Likewise. * gas/arm/group-reloc-alu-encoding-bad.d: Skip for vxworks targets. * gas/arm/group-reloc-alu.d: Likewise. * gas/arm/group-reloc-ldc-encoding-bad.d: Likewise. * gas/arm/group-reloc-ldc.d: Likewise. * gas/arm/group-reloc-ldr-encoding-bad.d: Likewise. * gas/arm/group-reloc-ldr.d: Likewise. * gas/arm/group-reloc-ldrs-encoding-bad.d: Likewise. * gas/arm/group-reloc-ldrs.d: Likewise. * gas/arm/local_function.d: Likewise. * gas/arm/mapshort-elf.d: Likewise. * gas/arm/undefined.d: Likewise.
2008-09-05 * lib/gas-defs.exp (run_dump_test): If the test expects an error,Nick Clifton2-0/+9
fail the test if gas doesn't report an error.
2008-08-28gas/testsuite/Jan Beulich5-634/+648
2008-08-28 Jan Beulich <jbeulich@novell.com> * gas/i386/intel.s: Add retf. * gas/i386/intel.{d,e}: Adjust. * gas/i386/opcode-intel.d: Replace lret with retf. opcodes/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (dis386): Adjust far return mnemonics. * i386-opc.tbl: Add retf. * i386-tbl.h: Re-generate.
2008-08-28gas/testsuite/Jan Beulich2-32/+36
2008-08-28 Jan Beulich <jbeulich@novell.com> * gas/i386/gas/i386/opcode-suffix.d: Add suffixes to cmovXX. opcodes/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
2008-08-28gas/H.J. Lu7-472/+516
2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (CR_IIB0): New. (CR_IIB1): Likewise. (cr): Add cr.iib0 and cr.iib1. (specify_resource): Handle IA64_RS_CR_IIB and CR_IIB0/CR_IIB1. gas/testsuite/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/dv-raw-err.s: Add tests for cr.iib0 and cr.iib1. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/regs.s: Likewise. * gas/ia64/dv-raw-err.l: Updated. * gas/ia64/dv-waw-err.l: Likewise. * gas/ia64/regs.d: Likewise. include/opcode/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update IA64_RS_CR. opcodes/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1. * ia64-gen.c (lookup_specifier): Likewise. * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1. * ia64-raw.tbl: Likewise. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerated.
2008-08-28gas/Jan Beulich7-0/+252
2008-08-28 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (md_assemble): Force number of displacement operands to zero when processing string instruction. (i386_index_check): Special-case string instruction operands. Don't fudge address prefix if there already was a memory operand. Fix error message to correctly reflect the addressing mode used. (i386_att_operand): Fix comment. (i386_intel_operand): Snapshot, clear, and restore base and index reg for each operand processed. Increment count of memory operands later. gas/testsuite/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * gas/i386/string-bad.{l,s}, gas/i386/string-ok.{d,e,s}: New. * gas/i386/i386.exp: Run new tests.
2008-08-27gas/testsuite/H.J. Lu3-0/+11
2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.s: Add tests for fidivr. * gas/i386/intel.d: Updated. opcodes/ 2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Correct fidivr operand size. * i386-tbl.h: Regenerated.
2008-08-26 * config/bfin-parse.y (check_macfunc_option): Fix instructionJie Zhang6-0/+207
mode checking. (asm_1): Check mode for 16-bit multiply instructions. testsuite/ * gas/bfin/arith_mode.d: New test. * gas/bfin/arith_mode.s: New test. * gas/bfin/invalid_arith_mode.l: New test. * gas/bfin/invalid_arith_mode.s: New test. * gas/bfin/bfin.exp: Add arith_mode and invalid_arith_mode.
2008-08-22 * config/bfin-lex.l (NUMBER): Protect special `.'.Jie Zhang4-0/+22
testsuite/ * gas/bfin/misc.s: New test. * gas/bfin/misc.d: New test. * gas/bfin/bfin.exp: Add misc test.
2008-08-21 * gas/cfi/cfi-common-1.d: Allow for differing offsets, andRichard Henderson4-16/+29
for DW_CFA_offset_extended_sf results. Allow for differing nops. * gas/cfi/cfi-hppa-1.d: Invert data alignment sign. Change offsets to match 64-bit offsets. * gas/cfi/cfi.exp: Don't run common tests on hppa64.
2008-08-202008-08-20 Bob Wilson <bob.wilson@acm.org>Bob Wilson2-1/+5
* gas/all/gas.exp: Expect the redef test to fail on Xtensa.
2008-08-20gas/H.J. Lu26-156/+669
2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * config/tc-i386.c (CPU_FLAGS_AES_MATCH): New. (CPU_FLAGS_AVX_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Updated. (cpu_flags_match): Likewise. gas/testsuite/ 2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * gas/i386/avx.s: Add AES + AVX tests. * gas/i386/arch-10.s: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/i386.exp: Run arch-avx-1, arch-avx-1-1 and arch-avx-1-2. * gas/i386/arch-avx-1.d: New. * gas/i386/arch-avx-1.s: Likewise. * gas/i386/arch-avx-1-1.l: Likewise. * gas/i386/arch-avx-1-1.s: Likewise. * gas/i386/arch-avx-1-2.l: Likewise. * gas/i386/arch-avx-1-2.s: Likewise. opcodes/ 2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * i386-dis.c (PREFIX_VEX_38DB): New. (PREFIX_VEX_38DC): Likewise. (PREFIX_VEX_38DD): Likewise. (PREFIX_VEX_38DE): Likewise. (PREFIX_VEX_38DF): Likewise. (PREFIX_VEX_3ADF): Likewise. (VEX_LEN_38DB_P_2): Likewise. (VEX_LEN_38DC_P_2): Likewise. (VEX_LEN_38DD_P_2): Likewise. (VEX_LEN_38DE_P_2): Likewise. (VEX_LEN_38DF_P_2): Likewise. (VEX_LEN_3ADF_P_2): Likewise. (PREFIX_VEX_3A04): Updated. (VEX_LEN_3A06_P_2): Likewise. (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC, PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF. (x86_64_table): Likewise. (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2, VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and VEX_LEN_3ADF_P_2. * i386-opc.tbl: Add AES + AVX instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-08-152008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel5-6/+14
* s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format. * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format. 2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: lxr operands are floating point. * gas/s390/esa-g5.s: Likewise. * gas/testsuite/gas/s390/zarch-z9-ec.d: rrdtr, rrxtr third operands is gpr. * gas/testsuite/gas/s390/zarch-z9-ec.s: Likewise.
2008-08-12gas/testsuite/H.J. Lu8-295/+329
2008-08-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/amd.s: Add syscall and sysret. Remove padding. * gas/i386/amd.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/i386.exp: Run x86-64-intel64. * gas/i386/x86-64-intel64.d: New. * gas/i386/x86-64-intel64.s: Likewise. * gas/i386/x86-64-opcode.s: Add syscall and sysret. opcodes/ 2008-08-12 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add syscall and sysret for Cpu64. * i386-tbl.h: Regenerated.
2008-08-082008-08-08 Richard Sandiford <rdsandiford@googlemail.com>Daniel Jacobowitz4-0/+24
Daniel Jacobowitz <dan@codesourcery.com> Catherine Moore <clm@codesourcery.com> Mark Shinwell <shinwell@codesourcery.com> Maxim Kuvyrkov <maxim@codesourcery.com> * elf32-mips.c (mips_vxworks_copy_howto_rela): Replace with... (elf_mips_copy_howto): ...this howto. Clear the size fields. (mips_vxworks_jump_slot_howto_rela): Replace with... (elf_mips_jump_slot_howto): ...this howto. (bfd_elf32_bfd_reloc_type_lookup): Handle BFD_RELOC_MIPS_COPY and BFD_RELOC_MIPS_JUMP_SLOT. (bfd_elf32_bfd_reloc_name_lookup): Handle "R_MIPS_COPY" and "R_MIPS_JUMP_SLOT". (mips_elf32_rtype_to_howto): Handle R_MIPS_COPY and R_MIPS_JUMP_SLOT. (elf_backend_plt_readonly): Define. (elf_backend_plt_sym_val): Define for non-VxWorks targets. (mips_vxworks_bfd_reloc_type_lookup): Delete. (mips_vxworks_bfd_reloc_name_lookup): Likewise. (mips_vxworks_rtype_to_howto): Likewise. (elf_backend_want_dynbss): Don't define for VxWorks. (elf_backend_plt_readonly): Likewise. (bfd_elf32_bfd_reloc_type_lookup): Likewise. (bfd_elf32_bfd_reloc_name_lookup): Likewise. (elf_backend_mips_rtype_to_howto): Likewise. (elf_backend_adjust_dynamic_symbol): Likewise. (elf_backend_got_symbol_offset): Don't define. * elfn32-mips.c (elf_mips_copy_howto, elf_mips_jump_slot_howto): New. (bfd_elf32_bfd_reloc_type_lookup): Handle BFD_RELOC_MIPS_COPY and BFD_RELOC_MIPS_JUMP_SLOT. (bfd_elf32_bfd_reloc_name_lookup): Handle "R_MIPS_COPY" and "R_MIPS_JUMP_SLOT". (mips_elf32_n32_rtype_to_howto): Handle R_MIPS_COPY and R_MIPS_JUMP_SLOT. (elf_backend_rela_plts_and_copies_p, elf_backend_plt_readonly) (elf_backend_plt_sym_val): Define. * elf64-mips.c (elf_mips_copy_howto, elf_mips_jump_slot_howto): New. (bfd_elf64_bfd_reloc_type_lookup): Handle BFD_RELOC_MIPS_COPY and BFD_RELOC_MIPS_JUMP_SLOT. (bfd_elf64_bfd_reloc_name_lookup): Handle "R_MIPS_COPY" and "R_MIPS_JUMP_SLOT". (mips_elf64_rtype_to_howto): Handle R_MIPS_COPY and R_MIPS_JUMP_SLOT. (elf_backend_rela_plts_and_copies_p, elf_backend_plt_readonly) (elf_backend_plt_sym_val): Define. * elfxx-mips.h (_bfd_mips_vxworks_adjust_dynamic_symbol): Delete. (_bfd_mips_elf_use_plts_and_copy_relocs, _bfd_mips_elf_init_stubs) (_bfd_mips_elf_plt_sym_val, _bfd_mips_post_process_headers): Declare. * elfxx-mips.c (mips_elf_la25_stub): New structure. (LA25_LUI, LA25_J, LA25_ADDIU): New macros. (mips_elf_link_hash_entry): Add "la25_stubs", "has_static_relocs" and "has_nonpic_branches" fields. Remove "is_relocation_target" and "is_branch_target". (mips_elf_link_hash_table): Add blank lines. Add "use_plts_and_copy_relocs", "reserved_gotno", "strampoline", "la25_stubs" and "add_stub_section" fields. (mips_htab_traverse_info): New structure. (PIC_OBJECT_P, MIPS_ELF_LOAD_WORD): New macros. (MIPS_RESERVED_GOTNO): Delete. (mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry) (mips_n64_exec_plt0_entry, mips_exec_plt_entry): New tables. (mips_elf_link_hash_newfunc): Update after the changes to mips_elf_link_hash_entry. (mips_elf_check_mips16_stubs): Replace the DATA parameter with an INFO parameter. Don't look through warnings symbols here; do it in mips_elf_check_symbols instead. (mips_elf_create_stub_symbol): New function. (mips_elf_la25_stub_hash, mips_elf_la25_stub_eq): New functions. (_bfd_mips_elf_init_stubs, mips_elf_local_pic_function_p): Likewise. (mips_elf_add_la25_intro, mips_elf_add_la25_trampoline): Likewise. (mips_elf_add_la25_stub, mips_elf_check_symbols): New functions. (mips_elf_gotplt_index): Check for VxWorks. (mips_elf_output_dynamic_relocation): Take the relocation index as an extra parameter. Do not increment reloc_count here. (mips_elf_initialize_tls_slots): Update the calls to mips_elf_output_dynamic_relocation accordingly. (mips_elf_multi_got): Use htab->reserved_gotno instead of MIPS_RESERVED_GOTNO. (mips_elf_create_got_section): Don't allocate reserved GOT entries here. Unconditionally create .got.plt, but don't set its alignment here. (mips_elf_relocation_needs_la25_stub): New function. (mips_elf_calculate_relocation): Redirect branches and jumps to a non-PIC stub if one exists. Check !h->has_static_relocs instead of !htab->is_vxworks when deciding whether to create dynamic relocations for R_MIPS_32, R_MIPS_REL32 and R_MIPS_64. (_bfd_mips_elf_create_dynamic_sections): Unconditionally call _bfd_elf_create_dynamic_sections. Unconditionally set up htab->splt and htab->sdynbss. Set htab->srelplt to ".rel.plt" if !htab->is_vxworks. Add non-VxWorks values of htab->plt_header_size and htab->plt_entry_size. (_bfd_mips_elf_check_relocs): Set pointer_equality_needed for non-branch static relocations. Set has_nonpic_branches when an la25 stub might be required. Set can_make_dynamic_p to TRUE if R_MIPS_32, R_MIPS_REL32 and R_MIPS_64 relocations can be made dynamic, rather than duplicating the condition. Do not make them dynamic for read-only sections in non-PIC executable objects. Do not protect this code with dynobj == NULL || htab->sgot == NULL; handle each group of cases separately. Add a default case that sets has_static_relocs for non-GOT relocations that cannot be made dynamic. Don't set is_relocation_target and is_branch_target. Reject non-PIC static relocations in shared objects. (_bfd_mips_vxworks_adjust_dynamic_symbol): Fold into... (_bfd_mips_elf_adjust_dynamic_symbol): ...here, using htab->use_plts_and_copy_relocs instead of htab->is_vxworks to select PLT and copy-reloc handling. Set the alignment of .plt and .got.plt when allocating the first entry. Generalize code to handle REL as well as RELA sections and 64-bit as well as 32-bit GOT entries. Complain if we find a static-only reloc against an externally-defined symbol and if we cannot create dynamic relocations for it. Allocate copy relocs using mips_elf_allocate_dynamic_relocations on non-VxWorks targets. Set possibly_dynamic_relocs to 0 when using PLTs or copy relocs. Skip reserved .got.plt entries. (_bfd_mips_elf_always_size_sections): Use mips_elf_check_symbols instead of mips_elf_check_mips16_stubs to process each symbol. Do the traversal for relocatable objects too. (mips_elf_lay_out_got): Use htab->reserved_gotno instead of MIPS_RESERVED_GOTNO. (_bfd_mips_elf_size_dynamic_sections): Exclude sdynbss if it is empty. Extend the DT_PLTREL, DT_JMPREL and DT_PLTRELSZ handling to non-VxWorks targets. Only add DT_REL{,A}, DT_REL{,A}SZ and DT_REL{,A}ENT if .rel.dyn is nonempty. Create a symbol for the PLT. Allocate a nop at the end of the PLT. Allocate DT_MIPS_PLTGOT. (mips_elf_create_la25_stub_info): New function. (_bfd_mips_elf_finish_dynamic_symbol): Write out PLT entries and copy relocs where necessary. Check pointer_equality_needed. (mips_finish_exec_plt): New function. (_bfd_mips_elf_finish_dynamic_sections): Always set DT_PLTGOT to the beginning of htab->sgot. Use htab->reserved_gotno instead of MIPS_RESERVED_GOTNO. Assert htab->use_plts_and_copy_relocs instead of htab->is_vxworks for DT_PLTREL, DT_PLTRELSZ and DT_JMPREL. Set DT_PLTREL to DT_REL instead of DT_RELA on non-VxWorks targets. Use mips_finish_exec_plt to create non-VxWorks PLT headers. Set DT_MIPS_PLTGOT. (_bfd_mips_elf_copy_indirect_symbol): Copy has_static_relocs from the indirect symbol to the direct symbol. Also copy has_nonpic_branches for indirect symbols. (_bfd_mips_elf_get_target_dtag): Handle DT_MIPS_PLTGOT and DT_MIPS_RWPLT. (_bfd_mips_elf_link_hash_table_create): Initialize the new mips_elf_link_hash_table fields. (_bfd_mips_vxworks_link_hash_table_create): Set use_plts_and_copy_relocs to TRUE. Use TRUE rather than 1 when setting is_vxworks. (_bfd_mips_elf_use_plts_and_copy_relocs): New function. (_bfd_mips_elf_final_link): Call mips_elf_create_la25_stub for each la25_stub. (_bfd_mips_elf_merge_private_bfd_data): Treat dynamic objects as PIC. Generalize message about linking PIC and non-PIC. (_bfd_mips_elf_plt_sym_val, _bfd_mips_post_process_headers): New functions. * reloc.c: Update comment near BFD_RELOC_MIPS_JUMP_SLOT. * bfd-in2.h: Regenerated. 2008-08-08 Richard Sandiford <rdsandiford@googlemail.com> Daniel Jacobowitz <dan@codesourcery.com> Catherine Moore <clm@codesourcery.com> Mark Shinwell <shinwell@codesourcery.com> * readelf.c (get_mips_symbol_other): Handle STO_MIPS_PLT and STO_MIPS_PIC. (slurp_rela_relocs, slurp_rel_relocs): Handle MIPS ELF64 here. (dump_relocations, debug_apply_relocations): Don't handle it here. (get_mips_dynamic_type): Handle DT_MIPS_PLTGOT and DT_MIPS_RWPLT. (print_mips_pltgot_entry): New function. (process_mips_specific): Dump the PLT GOT. 2008-08-08 Richard Sandiford <rdsandiford@googlemail.com> Daniel Jacobowitz <dan@codesourcery.com> * config/tc-mips.c (OPTION_CALL_NONPIC): New macro. (OPTION_NON_SHARED, OPTION_XGOT, OPTION_MABI, OPTION_32) (OPTION_N32, OPTION_64, OPTION_MDEBUG, OPTION_NO_MDEBUG) (OPTION_PDR, OPTION_NO_PDR, OPTION_MVXWORKS_PIC): Bump by 1. (md_longopts): Add -call_nonpic. (md_parse_option): Handle OPTION_CALL_NONPIC. (md_show_usage): Add -call_nonpic. 2008-08-08 Richard Sandiford <rdsandiford@googlemail.com> * gas/mips/call-nonpic-1.s, gas/mips/call-nonpic-1.d: New test. * gas/mips/mips.exp: Run it. 2008-08-08 Richard Sandiford <rdsandiford@googlemail.com> Daniel Jacobowitz <dan@codesourcery.com> Catherine Moore <clm@codesourcery.com> Mark Shinwell <shinwell@codesourcery.com> * mips.h (STO_MIPS_PLT, ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT) (STO_MIPS_PIC, DT_MIPS_PLTGOT, DT_MIPS_RWPLT): New macros. 2008-08-08 Richard Sandiford <rdsandiford@googlemail.com> Daniel Jacobowitz <dan@codesourcery.com> * emulparams/elf32bmip.sh (GOT): Define, moving .got.plt to... (OTHER_RELRO_SECTIONS, OTHER_READWRITE_SECTIONS): ...one of these two variables. * emulparams/elf32bmipn32-defs.sh: Likewise. * emultempl/mipself.em: Include ldctor.h, elf/mips.h and elfxx-mips.h. (is_mips_elf): New macro. (stub_file, stub_bfd): New variables. (hook_stub_info): New structure. (hook_in_stub): New function. (mips_add_stub_section): Likewise. (mips_create_output_section_statements): Likewise. (mips_before_allocation): Likewise. (real_func): New variable. (mips_for_each_input_file_wrapper): New function. (mips_lang_for_each_input_file): Likewise. (lang_for_each_input_file): Define. (LDEMUL_BEFORE_ALLOCATION): Likewise. (LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): Likewise. 2008-08-08 Richard Sandiford <rdsandiford@googlemail.com> Daniel Jacobowitz <dan@codesourcery.com> * ld-mips-elf/mips16-pic-3a.s, ld-mips-elf/mips16-pic-3b.s, ld-mips-elf/mips16-pic-3.dd, ld-mips-elf/mips16-pic-3.gd, ld-mips-elf/mips16-pic-3.rd, ld-mips-elf/mips16-pic-3.inc, ld-mips-elf/pic-and-nonpic-1a.s, ld-mips-elf/pic-and-nonpic-1b.s, ld-mips-elf/pic-and-nonpic-1.ld, ld-mips-elf/pic-and-nonpic-1.dd, ld-mips-elf/pic-and-nonpic-1.nd, ld-mips-elf/pic-and-nonpic-1-rel.dd, ld-mips-elf/pic-and-nonpic-1-rel.nd, ld-mips-elf/pic-and-nonpic-2a.s, ld-mips-elf/pic-and-nonpic-2b.s, ld-mips-elf/pic-and-nonpic-2.d, ld-mips-elf/pic-and-nonpic-3a.s, ld-mips-elf/pic-and-nonpic-3a.ld, ld-mips-elf/pic-and-nonpic-3a.dd, ld-mips-elf/pic-and-nonpic-3a.gd, ld-mips-elf/pic-and-nonpic-3a.sd, ld-mips-elf/pic-and-nonpic-3b.s, ld-mips-elf/pic-and-nonpic-3b.ld, ld-mips-elf/pic-and-nonpic-3b.ad, ld-mips-elf/pic-and-nonpic-3b.dd, ld-mips-elf/pic-and-nonpic-3b.gd, ld-mips-elf/pic-and-nonpic-3b.nd, ld-mips-elf/pic-and-nonpic-3b.pd, ld-mips-elf/pic-and-nonpic-3b.rd, ld-mips-elf/pic-and-nonpic-3b.sd, ld-mips-elf/pic-and-nonpic-3-error.d, ld-mips-elf/pic-and-nonpic-4a.s, ld-mips-elf/pic-and-nonpic-4b.s, ld-mips-elf/pic-and-nonpic-4b.ld, ld-mips-elf/pic-and-nonpic-4b.ad, ld-mips-elf/pic-and-nonpic-4b.dd, ld-mips-elf/pic-and-nonpic-4b.gd, ld-mips-elf/pic-and-nonpic-4b.nd, ld-mips-elf/pic-and-nonpic-4b.rd, ld-mips-elf/pic-and-nonpic-4b.sd, ld-mips-elf/pic-and-nonpic-4-error.d, ld-mips-elf/pic-and-nonpic-5a.s, ld-mips-elf/pic-and-nonpic-5b.s, ld-mips-elf/pic-and-nonpic-5b.ld, ld-mips-elf/pic-and-nonpic-5b.ad, ld-mips-elf/pic-and-nonpic-5b.dd, ld-mips-elf/pic-and-nonpic-5b.gd, ld-mips-elf/pic-and-nonpic-5b.nd, ld-mips-elf/pic-and-nonpic-5b.rd, ld-mips-elf/pic-and-nonpic-5b.sd, ld-mips-elf/pic-and-nonpic-5b.pd, ld-mips-elf/pic-and-nonpic-6.ld, ld-mips-elf/pic-and-nonpic-6-o32a.s, ld-mips-elf/pic-and-nonpic-6-o32b.s, ld-mips-elf/pic-and-nonpic-6-o32c.s, ld-mips-elf/pic-and-nonpic-6-o32.ad, ld-mips-elf/pic-and-nonpic-6-o32.dd, ld-mips-elf/pic-and-nonpic-6-o32.gd, ld-mips-elf/pic-and-nonpic-6-o32.nd, ld-mips-elf/pic-and-nonpic-6-o32.pd, ld-mips-elf/pic-and-nonpic-6-o32.rd, ld-mips-elf/pic-and-nonpic-6-o32.sd, ld-mips-elf/pic-and-nonpic-6-n32a.s, ld-mips-elf/pic-and-nonpic-6-n32b.s, ld-mips-elf/pic-and-nonpic-6-n32c.s, ld-mips-elf/pic-and-nonpic-6-n32.ad, ld-mips-elf/pic-and-nonpic-6-n32.dd, ld-mips-elf/pic-and-nonpic-6-n32.gd, ld-mips-elf/pic-and-nonpic-6-n32.nd, ld-mips-elf/pic-and-nonpic-6-n32.pd, ld-mips-elf/pic-and-nonpic-6-n32.rd, ld-mips-elf/pic-and-nonpic-6-n32.sd, ld-mips-elf/pic-and-nonpic-6-n64a.s, ld-mips-elf/pic-and-nonpic-6-n64b.s, ld-mips-elf/pic-and-nonpic-6-n64c.s, ld-mips-elf/pic-and-nonpic-6-n64.ad, ld-mips-elf/pic-and-nonpic-6-n64.dd, ld-mips-elf/pic-and-nonpic-6-n64.gd, ld-mips-elf/pic-and-nonpic-6-n64.nd, ld-mips-elf/pic-and-nonpic-6-n64.pd, ld-mips-elf/pic-and-nonpic-6-n64.rd, ld-mips-elf/pic-and-nonpic-6-n64.sd: New tests. * ld-mips-elf/mips-elf.exp: Run them.
2008-08-06bfd/Richard Sandiford8-0/+257
* reloc.c (BFD_RELOC_MIPS16_GOT16, BFD_RELOC_MIPS16_CALL16): Declare. * libbfd.h, bfd-in2.h: Regenerate. * elf32-mips.c (elf_mips16_howto_table_rel): Fill in reserved R_MIPS16_GOT16 and R_MIPS16_CALL16 entries. (mips16_reloc_map): Add mappings. * elf64-mips.c (mips16_elf64_howto_table_rel): Fill in reserved R_MIPS16_GOT16 and R_MIPS16_CALL16 entries. (mips16_elf64_howto_table_rela): Likewise. (mips16_reloc_map): Add mappings. * elfn32-mips.c (elf_mips16_howto_table_rel): Fill in reserved R_MIPS16_GOT16 and R_MIPS16_CALL16 entries. (elf_mips16_howto_table_rela): Likewise. (mips16_reloc_map): Add mappings. * elfxx-mips.c (mips_elf_create_shadow_symbol): New function. (section_allows_mips16_refs_p): Likewise. (mips16_stub_symndx): Likewise. (mips_elf_check_mips16_stubs): Treat the data argument as a bfd_link_info. Mark every dynamic symbol as needing MIPS16 stubs and create a "shadow" symbol for the original MIPS16 definition. (mips16_reloc_p, got16_reloc_p, call16_reloc_p, hi16_reloc_p) (lo16_reloc_p, mips16_call_reloc_p): New functions. (_bfd_mips16_elf_reloc_unshuffle): Use mips16_reloc_p to generalize relocation checks. (_bfd_mips16_elf_reloc_shuffle): Likewise. (_bfd_mips_elf_lo16_reloc): Handle R_MIPS16_GOT16. (mips_elf_got16_entry): Add comment. (mips_elf_calculate_relocation): Use hi16_reloc_p, lo16_reloc_p, mips16_call_reloc_p, call16_reloc_p and got16_reloc_p to generalize relocation checks. Use section_allows_mips16_refs_p instead of mips16_stub_section_p. Handle R_MIPS16_CALL16 and R_MIPS16_GOT16, allowing the former to refer directly to a MIPS16 function if its stub is not needed. (mips16_stub_section_p): Delete. (_bfd_mips_elf_symbol_processing): Convert odd-valued function symbols into even MIPS16 symbols. (mips_elf_add_lo16_rel_addend): Use mips16_reloc_p to generalize a relocation check. (_bfd_mips_elf_check_relocs): Calculate "bed" and "rel_end" earlier in the function. Use mips16_stub_symndx to identify the target function. Avoid out-of-bounds accesses when the stub has no relocations; report an error instead. Use section_allows_mips16_refs_p instead of mips16_stub_section_p. Use mips16_call_reloc_p and got16_reloc_p to generalize relocation checks. Handle R_MIPS16_CALL16 and R_MIPS16_GOT16. Don't create dynamic relocations for absolute references to __gnu_local_gp. (_bfd_mips_elf_always_size_sections): Pass a bfd_link_info as the argument to mips_elf_check_mips16_stubs. Generalize comment. (_bfd_mips_elf_relocate_section): Use hi16_reloc_p and got16_reloc_p to generalize relocation checks. (_bfd_mips_elf_finish_dynamic_symbol): If a dynamic MIPS16 function symbol has a non-MIPS16 stub, redirect the symbol to the stub. Fix an overly long line. Don't give dynamic symbols type STO_MIPS16. (_bfd_mips_elf_gc_sweep_hook): Handle R_MIPS16_CALL16 and R_MIPS16_GOT16. gas/ * config/tc-mips.c (mips16_reloc_p, got16_reloc_p, hi16_reloc_p) (lo16_reloc_p): New functions. (reloc_needs_lo_p): Use hi16_reloc_p and got16_reloc_p to generalize relocation checks. (matching_lo_reloc): New function. (fixup_has_matching_lo_p): Use it. (mips16_mark_labels): Don't clobber a symbol's visibility. (append_insn): Use hi16_reloc_p and lo16_reloc_p. (mips16_ip): Handle BFD_RELOC_MIPS16_GOT16 and BFD_RELOC_MIPS16_CALL16. (md_apply_fix): Likewise. (mips16_percent_op): Add %got and %call16. (mips_frob_file): Use got16_reloc_p to generalize relocation checks. Use matching_lo_reloc. (mips_force_relocation): Use hi16_reloc_p and lo16_reloc_p to generalize relocation checks. (mips_fix_adjustable): Use lo16_reloc_p to generalize relocation checks. gas/testsuite/ * gas/mips/elf-rel8-mips16.d, gas/mips/elf-rel8-mips16.s, * gas/mips/elf-rel9-mips16.d, gas/mips/elf-rel9-mips16.s, * gas/mips/elf-rel13-mips16.d, gas/mips/elf-rel13-mips16.s: New tests. * gas/mips/mips.exp: Run them. ld/testsuite/ * ld-mips-elf/mips16-local-stubs-1.d: Remove stub_for_h3, which was only referenced by the .pdr section, and was not actually needed by code. * ld-mips-elf/mips16-intermix.d: Remove unused static function stubs. * ld-mips-elf/mips16-pic-1a.s, ld-mips-elf/mips16-pic-1b.s, ld-mips-elf/mips16-pic-1-dummy.s, ld-mips-elf/mips16-pic-1.dd, ld-mips-elf/mips16-pic-1.gd, ld-mips-elf/mips16-pic-1.inc, ld-mips-elf/mips16-pic-1.ld, ld-mips-elf/mips16-pic-2a.s, ld-mips-elf/mips16-pic-2b.s, ld-mips-elf/mips16-pic-2.ad, ld-mips-elf/mips16-pic-2.dd, ld-mips-elf/mips16-pic-2.gd, ld-mips-elf/mips16-pic-2.nd, ld-mips-elf/mips16-pic-2.rd: New tests. * ld-mips-elf/mips-elf.exp: Run them.
2008-08-02gas/Peter Bergner4-0/+122
* config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7. (md_show_usage): Document -mpower7 and -mvsx. * doc/as.texinfo (Target PowerPC): Document -mvsx. * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7. gas/testsuite/ * gas/ppc/power7.d: New. * gas/ppc/power7.s: Likewise. * gas/ppc/ppc.exp: Run power7 test. include/opcode/ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. (print_insn_powerpc): Prepend 'vs' when printing VSX registers. (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. * ppc-opc.c (insert_xt6): New static function. (extract_xt6): Likewise. (insert_xa6): Likewise. (extract_xa6: Likewise. (insert_xb6): Likewise. (extract_xb6): Likewise. (insert_xb6s): Likewise. (extract_xb6s): Likewise. (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, XX3DM_MASK, PPCVSX): New. (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
2008-08-01binutils/H.J. Lu5-78/+10
2008-08-01 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Remove AVX registers. (dwarf_regnames_x86_64): Likewise. gas/testsuite/ 2008-08-01 H.J. Lu <hongjiu.lu@intel.com> * gas/cfi/cfi-i386.s: Remove tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. opcodes/ 2008-08-01 H.J. Lu <hongjiu.lu@intel.com> * i386-reg.tbl: Use Dw2Inval on AVX registers. * i386-tbl.h: Regenerated.
2008-08-01gas/Peter Bergner6-3/+82
* config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions. <cell>: Likewise. gas/testsuite/ * gas/ppc/cell.s: Add altivec instructions. * gas/ppc/cell.d: Update expected output. * gas/ppc/power6.d: New. * gas/ppc/power6.s: Likewise. * gas/ppc/ppc.exp (powerpc64*-*-*): Move cell from here to... (powerpc*-*-*): Here. Run power6 test.
2008-07-242008-07-24 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu8-0/+18
* gas/i386/nops-1.d: Add -mtune=generic32. * gas/i386/nops-2.d: Likewise. * gas/i386/nops-3.d: Likewise. * gas/i386/x86-64-nops-1.d: Add -mtune=generic64. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise.
2008-07-22 * config/tc-mips.c (mips_ip): Reset s to argsStart.Nick Clifton3-6/+11
* gas/mips/tls-ill.l: Update error message. * gas/mips/octeon-ill.l: Likewise.
2008-07-14 * gas/bfin/{bit2.s, cache2.s, control_code2.s, event2.s,Jie Zhang14-2075/+2082
logical2.s, move2.s, parallel.s, parallel2.s, parallel3.s, parallel4.s, shift2.s, stack2.s, video2.s}: Remove DOS line endings.
2008-07-10include/elf/Richard Sandiford4-0/+17
* mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros. bfd/ * elfxx-mips.c (mips_elf_check_mips16_stubs): Use ELF_ST_IS_MIPS16. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_add_symbol_hook): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. opcodes/ * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16. gas/ * config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16. (mips_fix_adjustable): Likewise. (mips_frob_file_after_relocs): Likewise. gas/testsuite/ * gas/mips/mips16-vis-1.d, gas/mips/mips16-vis-1.s: New tests. * gas/mips/mips.exp: Run them.
2008-07-092008-07-09 Kai Tietz <kai.tietz@onevision.com>Kai Tietz3-4/+41
* gas/i386/i386.exp (x86-64-pcrel): Disable for w64. (x86-64-sse5): Likewise. (x86-64-opcode-inval): Likewise. (x86-64-opcode-inval-intel): Likewise. (x86-64-w64-pcrel): New. * gas/i386/x86-64-w64-pcrel.d: New.
2008-07-07 * gas/mips/mips32.s: Move out coprocessor2 insns from here ...Adam Nemet18-127/+286
* gas/mips/mips32-cp2.s: ... to here. * gas/mips/mips32.d: Update. * gas/mips/mips32-cp2.d: New file. * gas/mips/mips32r2.s: Move out coprocessor2 insns from here ... * gas/mips/mips32r2-cp2.s: ... to here. * gas/mips/mips32r2.d: Update. * gas/mips/mips32r2-cp2.d: New file. * gas/mips/mips64.s: Move out coprocessor2 insns from here ... * gas/mips/mips64-cp2.s: ... to here. * gas/mips/mips64.d: Update. * gas/mips/mips64-cp2.d: New file. * gas/mips/mips.exp: Run mips32-cp2, mips32r2-cp2 and mips64-cp except for Octeon. * gas/mips/octeon.s: Add supported coprocessor insns. Move pop down to keep alphabetical order. * gas/mips/octeon.d: Update. * gas/mips/octeon-ill.s: Add unsupported coprocessor insns. * gas/mips/octeon-ill.l: Update.
2008-07-07gas/Carlos O'Donell3-0/+34
2008-07-07 Paul Brook <paul@codesourcery.com> * config/tc-arm.c (arm_fix_adjustable): Don't adjust MOVW/MOVT relocations. gas/testsuite/ 2008-07-07 Paul Brook <paul@codesourcery.com> * gas/arm/movw-local.d: New test. * gas/arm/movw-local.s: New test.
2008-06-27* gas/mips/odd-float.d: Replace ... with #pass.Chao-ying Fu5-3/+11
* gas/mips/ldstla-32-shared.d: Add -march=mips1 for as. * gas/mips/ldstla-32.d: Likewise. * gas/mips/mips16-hilo-match.d: Add -mabi=32 -march=mips1 for as.
2008-06-20* gas/mips/e32-rel2.d: Add -march=mips1 for as.Chao-ying Fu2-1/+5
2008-06-16 PR gas/6607Hans-Peter Nilsson7-0/+49
* gas/mmix/err-loc-10.s, gas/mmix/err-loc-9.s, gas/mmix/loc-6.d, gas/mmix/loc-6.s, gas/mmix/loc-7.d, gas/mmix/loc-7.s: New tests.
2008-06-12 * mips.h: Document new field descriptors +Q.Nick Clifton5-0/+70
(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptor +Q. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, seqi, sne and snei. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q. (mips_ip): Likewise. (macro_build): Likewise. (CPU_HAS_SEQ): New macro. (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi and snei.
2008-06-12include/opcode/Nick Clifton6-3/+161
* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. Update comment before MIPS16 field descriptors to mention MIPS16. (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for BBIT. (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): New bit masks and shift counts for cins and exts. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptors +x, +X, +p, +P, +s, +S. (mips_ip): Likewise. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, +s, +S. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test. * gas/mips/mips.exp: Run it. Run octeon test with run_dump_test_arches.
2008-06-03gas/H.J. Lu5-0/+65
2008-06-03 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (set_sse_check): New. (md_pseudo_table): Add "sse_check". gas/testsuite/ 2008-06-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run sse-check-none and x86-64-sse-check-none. * gas/i386/sse-check-none.d: New. * gas/i386/sse-check-none.s: Likewise. * gas/i386/x86-64-sse-check-none.d: Likewise.
2008-06-032008-06-03 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+6
gas/ * config/tc-arm.c (do_t_rbit): Populate both rm fields. gas/testsuite/ * gas/arm/thumb32.d: Update expected output.
2008-05-30gas/testsuite/H.J. Lu6-76/+109
2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-avx.s: Add tests for vmovd on 64bit operands. * gas/i386/x86-64-sse2avx.s: Add tests for movd on 64bit operands. * gas/testsuite/gas/i386/x86-64-avx.d: Updated. * gas/testsuite/gas/i386/x86-64-avx-intel.d: Likewise. * gas/testsuite/gas/i386/x86-64-sse2avx.d: Likewise. opcodes/ 2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add vmovd with 64bit operand. * i386-tbl.h: Regenerated.
2008-05-272008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>Martin Schwidefsky3-2/+6
* s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format. 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com> * gas/s390/zarch-z990.d (idte): Fix operand format.
2008-05-23gas/testsuite/H.J. Lu5-0/+21
2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and cvttpd2pi. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi. * i386-tbl.h: Regenerated.
2008-05-22gas/testsuite/H.J. Lu11-46/+3673
2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * gas/i386/avx.s: Add tests for unspecified memory operand size in Intel syntax. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/simd.s: Add tests for cvtsi2ss and cvtsi2sd with unspecified memory operand size in Intel syntax. * gas/i386/avx.d: Updated. * gas/i386/avx-intel.d: Likewise. * gas/i386/simd.d: Likewise. * gas/i386/simd-intel.d: Likewise. * gas/i386/simd-suffix.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss into 32bit and 64bit. Remove Reg64|Qword and add IgnoreSize|No_qSuf on 32bit version. * i386-tbl.h: Regenerated.
2008-05-21gas/testsuite/H.J. Lu5-0/+16
2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. * i386-tbl.h: Regenerated.
2008-05-09 gas/Catherine Moore4-0/+194
* config/tc-mips.c (mips_frob_file): Don't match MIPS16 relocs with non-MIPS16 relocs. gas/testsuite/ * gas/mips/mips16-hilo-match.s: New test. * gas/mips/mip16-hilo-match.d: New test output.Index: config/tc-mips.c
2008-05-02gas/H.J. Lu30-58/+560
2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE, EPT and MOVBE. * config/tc-i386.c (cpu_arch): Add .movbe and .ept. (md_show_usage): Add .movbe and .ept. * doc/c-i386.texi: Add movbe and ept to -march=. Document .movbe and .ept. gas/testsuite/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept, ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel, x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and x86-64-inval-ept. * gas/i386/arch-10.s: Add movbe and invept. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/ept.d: New file * gas/i386/ept-intel.d: Likewise. * gas/i386/ept.s: Likewise. * gas/i386/inval-ept.l: Likewise. * gas/i386/inval-ept.s: Likewise. * gas/i386/inval-movbe.l: Likewise. * gas/i386/inval-movbe.s: Likewise. * gas/i386/movbe.d: Likewise. * gas/i386/movbe-intel.d: Likewise. * gas/i386/movbe.s: Likewise. * gas/i386/x86-64-inval-ept.l: Likewise. * gas/i386/x86-64-inval-ept.s: Likewise. * gas/i386/x86-64-inval-movbe.l: Likewise. * gas/i386/x86-64-inval-movbe.s: Likewise. * gas/i386/x86-64-ept.d: Likewise. * gas/i386/x86-64-ept-intel.d: Likewise. * gas/i386/x86-64-ept.s: Likewise. * gas/i386/x86-64-movbe.d: Likewise. * gas/i386/x86-64-movbe-intel.d: Likewise. * gas/i386/x86-64-movbe.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOVBE_Fixup): New. (Mo): Likewise. (PREFIX_0F3880): Likewise. (PREFIX_0F3881): Likewise. (PREFIX_0F38F0): Updated. (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and CPU_EPT_FLAGS. (cpu_flags): Add CpuMovbe and CpuEPT. * i386-opc.h (CpuMovbe): New. (CpuEPT): Likewise. (CpuLM): Updated. (i386_cpu_flags): Add cpumovbe and cpuept. * i386-opc.tbl: Add entries for movbe and EPT instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-04-30missed from 20080414 commit for e500mc supportAlan Modra1-0/+1
2008-04-28 * gas/mips/mips4.s: Split out fp instruction from here ...Adam Nemet23-98/+423
* gas/mips/mips4-fp.s: ... to here. * gas/mips/mips4.d: Update. * gas/mips/mips4-fp.l: New file. Check error messages with -msoft-float. * gas/mips/mips4-fp.d: New file. Check disassembly with hard-float. * gas/mips/mips32r2.s: Split out fp instructions from here ... * gas/mips/mips32r2-fp32.s: ... to here. * gas/mips/mips32r2.d: Update. * gas/mips/mips32r2-fp32.l: New file. Check error messages with -msoft-float. * gas/mips/mips32r2-fp32.d: New file. Check disassembly with hard-float. * gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New test derived from mips32r2-ill. * gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check error messages for soft-float targets. * gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l: New test for -msingle-float. * gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l: New test for -msoft-float. * gas/mips/mips-hard-float-flag.s, gas/mips/mips-hard-float-flag.l: New test for -mhard-float. * gas/mips/mips-double-float-flag.s, gas/mips/mips-double-float-flag.l: New test for -mdouble-float. * gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests. Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list test with -msoft-float. Run new mips-macro-ill-sfp test with -msingle-float. Run new mips-macro-ill-nofp test with -msoft-float. Run new mips-hard-float-flag and mips-double-float-flag tests.
2008-04-232008-04-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu6-0/+229
* gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx. * gas/i386/sse-noavx.d: New. * gas/i386/sse-noavx.s: Likewise. * gas/i386/x86-64-sse-noavx.d: Likewise. * gas/i386/x86-64-sse-noavx.s: Likewise.
2008-04-232008-04-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu7-249/+376
* gas/i386/sse2.s: Add tests for pmuludq, paddq and psubq. * gas/i386/x86-64-simd.s: Likewise. * gas/i386/sse2.d: Updated. * gas/i386/x86-64-simd.d: Likewise. * gas/i386/x86-64-simd-intel.d: Likewise. * gas/i386/x86-64-simd-suffix.d: Likewise.
2008-04-23opcodes/David S. Miller4-0/+26
* sparc-opc.c (asi_table): Add UltraSPARC and Niagara extended values. (prefetch_table): Add missing values. gas/ * config/tc-sparc.c (v9a_asr_table): Add missing 'stick' and 'stick_cmpr', and document ordering rules of table. (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and BFD_RELOC_SPARC_PC10. * doc/c-sparc.texi: New section on Sparc constants. Add documentation for %stick and %stick_cmpr. gas/testsuite/ * gas/sparc/pc2210.d: New file. * gas/sparc/pc2210.d: Likewise. * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.
2008-04-18gas/H.J. Lu7-676/+685
2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): Swap REG and NDS for FMA. gas/testsuite/ 2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.d: Updated. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_VEX_FMA): New. (OP_EX_VexImmW): Likewise. (VexFMA): Likewise. (Vex128FMA): Likewise. (EXVexImmW): Likewise. (get_vex_imm8): Likewise. (OP_EX_VexReg): Likewise. (vex_i4_done): Renamed to ... (vex_w_done): This. (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on FMA instructions. (print_insn): Updated. (OP_EX_VexW): Rewrite to swap register in VEX with EX. (OP_REG_VexI4): Check invalid high registers.
2008-04-16<opcode changes>Dwarakanath Rajagopal3-1/+15
2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * i386-opc.tbl: Fix protX to allow memory in the middle operand. * i386-tbl.h: Regenerate from i386-opc.tbl. <gas/testsuite changes> 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle operand. * gas/i386/x86-64-sse5.d: Likewise.
generated by cgit v1.1 at 2025-01-15 11:12:31 +0000