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2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu7-33/+21
2018-03-08x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich3-0/+47
2018-03-08x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich17-1/+144
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich14-125/+63
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2-0/+711
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich2-18/+18
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich3-6/+0
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu61-3206/+2144
2018-03-07XCOFF disassemblerAlan Modra3-74/+75
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu4-0/+104
2018-02-27gas: Rename .nop directive to .nopsH.J. Lu20-32/+32
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu17-0/+475
2018-02-26BFD messagesAlan Modra1-1/+1
2018-02-26MIPS messagesAlan Modra1-1/+1
2018-02-22Diagnose when trying to assemble conditional FP16 vmovx and vinsAndre Simoes Dias Vieira2-205/+265
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu2-0/+52
2018-02-20MIPS16/GAS/testsuite: Add cross-section R_MIPS16_PC16_S1 relocation testsMaciej W. Rozycki5-0/+114
2018-02-20gas: xtensa: limit size of auto litpoolsMax Filippov5-3/+19
2018-02-17Add .nop assembler directiveH.J. Lu21-0/+459
2018-02-15Fix AArch32 build attributes for Armv8.4-A.Tamar Christina1-0/+17
2018-02-13Fix ARm assembler so that it rejects invalid immediate values for the Thumb O...Nick Clifton3-0/+14
2018-02-13x86-64: Generate branch with PLT32 relocationH.J. Lu8-22/+22
2018-02-13MIPS/GAS/testsuite: Correct duplicate `Loongson-3A tests' test nameMaciej W. Rozycki1-1/+1
2018-02-12MIPS/GAS/test: Fix an n32 `.reginfo' size test failureMaciej W. Rozycki1-1/+1
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong3-6/+6
2018-02-08PR22819, powerpc gas "instruction address is not a multiple of 4"Alan Modra6-0/+29
2018-02-05MIPS/BFD: Correctly report unsupported `.reginfo' section sizeMaciej W. Rozycki5-0/+16
2018-01-24[GAS][AARCH64]Add group relocations to create PC-relative offset.Renlin Li14-0/+155
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist7-0/+58
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist7-0/+58
2018-01-22Fix the RX assembler so that it can handle escaped double quote characters, i...Oleg Endo3-0/+17
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist9-0/+44
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-2/+4
2018-01-15[ARM] Enable conditional Armv8-M instructionsThomas Preud'homme1-2/+11
2018-01-15[ARM] No IT usage deprecation for ARMv8-MThomas Preud'homme5-48/+49
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist19-1030/+16
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich12-381/+384
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich6-0/+36
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2-0/+16
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh4-0/+19
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-1/+1
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu4-0/+136
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson2-24/+28
2018-01-03Update year range in copyright notice of binutils filesAlan Modra192-192/+192
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson2-0/+518
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson12-0/+92
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-432/+432
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina3-0/+24
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-45/+45
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu3-0/+17
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