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2018-02-27gas: Rename .nop directive to .nopsH.J. Lu20-32/+32
Since directives of NO_PSEUDO_DOT targets don't have the leading '.' and "nop" can be a valid instruction, rename .nop directive to .nops to avoid conflict. * NEWS: Rename .nop to .nops. * doc/as.texinfo: Likewise. * read.c (potable): Add "nops". Remove "nop". (s_nop): Renamed to ... (s_nops): This. * read.h (s_nop): Renamed to ... (s_nops): This. * write.c (cvt_frag_to_fill): Rename .nop to .nops. (md_generate_nops): Likewise. (relax_segment): Likewise. * testsuite/gas/i386/nop-1.d: Updated. * testsuite/gas/i386/nop-1.s: Likewise. * testsuite/gas/i386/nop-2.d: Likewise. * testsuite/gas/i386/nop-2.s: Likewise. * testsuite/gas/i386/nop-3.d: Likewise. * testsuite/gas/i386/nop-3.s: Likewise. * testsuite/gas/i386/nop-4.d: Likewise. * testsuite/gas/i386/nop-4.s: Likewise. * testsuite/gas/i386/nop-5.d: Likewise. * testsuite/gas/i386/nop-5.s: Likewise. * testsuite/gas/i386/nop-6.d: Likewise. * testsuite/gas/i386/nop-6.s: Likewise. * testsuite/gas/i386/nop-bad-1.l: Likewise. * testsuite/gas/i386/nop-bad-1.s: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-nop-2.d: Likewise. * testsuite/gas/i386/x86-64-nop-3.d: Likewise. * testsuite/gas/i386/x86-64-nop-4.d: Likewise. * testsuite/gas/i386/x86-64-nop-5.d: Likewise. * testsuite/gas/i386/x86-64-nop-6.d: Likewise.
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu17-0/+475
On x86, some instructions have alternate shorter encodings: 1. When the upper 32 bits of destination registers of andq $imm31, %r64 testq $imm31, %r64 xorq %r64, %r64 subq %r64, %r64 known to be zero, we can encode them without the REX_W bit: andl $imm31, %r32 testl $imm31, %r32 xorl %r32, %r32 subl %r32, %r32 This optimization is enabled with -O, -O2 and -Os. 2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit immediate to 64-bit destination register, we can use it to encode 64-bit mov with 32-bit immediates. This optimization is enabled with -O, -O2 and -Os. 3. Since the upper bits of destination registers of VEX128 and EVEX128 instructions are extended to zero, if all bits of destination registers of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128 encoding to encode AVX256 or AVX512 instructions. When 2 source registers are identical, AVX256 and AVX512 andn and xor instructions: VOP %reg, %reg, %dest_reg can be encoded with VOP128 %reg, %reg, %dest_reg This optimization is enabled with -O2 and -Os. 4. 16-bit, 32-bit and 64-bit register tests with immediate may be encoded as 8-bit register test with immediate. This optimization is enabled with -Os. This patch does: 1. Add {nooptimize} pseudo prefix to disable instruction size optimization. 2. Add optimize to i386_opcode_modifier to tell assembler that encoding of an instruction may be optimized. gas/ PR gas/22871 * NEWS: Mention -O[2|s]. * config/tc-i386.c (_i386_insn): Add no_optimize. (optimize): New. (optimize_for_space): Likewise. (fits_in_imm7): New function. (fits_in_imm31): Likewise. (optimize_encoding): Likewise. (md_assemble): Call optimize_encoding to optimize encoding. (parse_insn): Handle {nooptimize}. (md_shortopts): Append "O::". (md_parse_option): Handle -On. * doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well as {nooptimize}. * testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler. * testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise. * testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2, optimize-3, x86-64-optimize-1, x86-64-optimize-2, x86-64-optimize-3 and x86-64-optimize-4. * testsuite/gas/i386/optimize-1.d: New file. * testsuite/gas/i386/optimize-1.s: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. opcodes/ PR gas/22871 * i386-gen.c (opcode_modifiers): Add Optimize. * i386-opc.h (Optimize): New enum. (i386_opcode_modifier): Add optimize. * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, vpxord and vpxorq. * i386-tbl.h: Regenerated.
2018-02-26BFD messagesAlan Modra1-1/+1
bfd/ * archive.c, * bfd.c, * linker.c, * reloc.c, * stabs.c, * syms.c: Standardize error/warning messages. binutils/ * testsuite/binutils-all/mips/mips-reginfo-n32.d, * testsuite/binutils-all/mips/mips-reginfo.d: Update. gas/ * testsuite/gas/mips/reginfo-2.l: Update. ld/ * testsuite/ld-arm/cmse-implib-errors.out, * testsuite/ld-arm/cmse-new-earlier-later-implib.out, * testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out, * testsuite/ld-arm/cmse-new-wrong-implib.out, * testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out, * testsuite/ld-arm/cmse-veneers-wrong-entryfct.out, * testsuite/ld-cris/badgotr1.d, * testsuite/ld-cris/tls-err-24.d, * testsuite/ld-cris/tls-err-25.d, * testsuite/ld-cris/tls-err-26.d, * testsuite/ld-cris/tls-err-27.d, * testsuite/ld-cris/tls-err-28.d, * testsuite/ld-cris/tls-err-40.d, * testsuite/ld-cris/tls-err-44.d, * testsuite/ld-cris/tls-err-48.d, * testsuite/ld-cris/tls-err-52.d, * testsuite/ld-cris/tls-err-53.d, * testsuite/ld-cris/tls-err-55.d, * testsuite/ld-cris/tls-err-56.d, * testsuite/ld-cris/tls-err-62.d, * testsuite/ld-cris/tls-err-65.d, * testsuite/ld-cris/tls-err-77.d, * testsuite/ld-elf/empty-implib.out, * testsuite/ld-elf/indirect.exp: Update.
2018-02-26MIPS messagesAlan Modra1-1/+1
More standardization of messages. bfd/ * elfxx-mips.c: Standardize error/warning messages. binutils/ * testsuite/binutils-all/mips/mips-reginfo-n32.d, * testsuite/binutils-all/mips/mips-reginfo.d: Update. gas/ * testsuite/gas/mips/reginfo-2.l: Update. ld/ * testsuite/ld-mips-elf/attr-gnu-4-12.d, * testsuite/ld-mips-elf/attr-gnu-4-13.d, * testsuite/ld-mips-elf/attr-gnu-4-14.d, * testsuite/ld-mips-elf/attr-gnu-4-16.d, * testsuite/ld-mips-elf/attr-gnu-4-17.d, * testsuite/ld-mips-elf/attr-gnu-4-18.d, * testsuite/ld-mips-elf/attr-gnu-4-19.d, * testsuite/ld-mips-elf/attr-gnu-4-21.d, * testsuite/ld-mips-elf/attr-gnu-4-23.d, * testsuite/ld-mips-elf/attr-gnu-4-24.d, * testsuite/ld-mips-elf/attr-gnu-4-25.d, * testsuite/ld-mips-elf/attr-gnu-4-26.d, * testsuite/ld-mips-elf/attr-gnu-4-27.d, * testsuite/ld-mips-elf/attr-gnu-4-28.d, * testsuite/ld-mips-elf/attr-gnu-4-29.d, * testsuite/ld-mips-elf/attr-gnu-4-31.d, * testsuite/ld-mips-elf/attr-gnu-4-32.d, * testsuite/ld-mips-elf/attr-gnu-4-34.d, * testsuite/ld-mips-elf/attr-gnu-4-35.d, * testsuite/ld-mips-elf/attr-gnu-4-36.d, * testsuite/ld-mips-elf/attr-gnu-4-37.d, * testsuite/ld-mips-elf/attr-gnu-4-38.d, * testsuite/ld-mips-elf/attr-gnu-4-39.d, * testsuite/ld-mips-elf/attr-gnu-4-41.d, * testsuite/ld-mips-elf/attr-gnu-4-42.d, * testsuite/ld-mips-elf/attr-gnu-4-43.d, * testsuite/ld-mips-elf/attr-gnu-4-45.d, * testsuite/ld-mips-elf/attr-gnu-4-46.d, * testsuite/ld-mips-elf/attr-gnu-4-47.d, * testsuite/ld-mips-elf/attr-gnu-4-48.d, * testsuite/ld-mips-elf/attr-gnu-4-49.d, * testsuite/ld-mips-elf/attr-gnu-4-52.d, * testsuite/ld-mips-elf/attr-gnu-4-53.d, * testsuite/ld-mips-elf/attr-gnu-4-54.d, * testsuite/ld-mips-elf/attr-gnu-4-58.d, * testsuite/ld-mips-elf/attr-gnu-4-59.d, * testsuite/ld-mips-elf/attr-gnu-4-61.d, * testsuite/ld-mips-elf/attr-gnu-4-62.d, * testsuite/ld-mips-elf/attr-gnu-4-63.d, * testsuite/ld-mips-elf/attr-gnu-4-64.d, * testsuite/ld-mips-elf/attr-gnu-4-68.d, * testsuite/ld-mips-elf/attr-gnu-4-69.d, * testsuite/ld-mips-elf/attr-gnu-4-71.d, * testsuite/ld-mips-elf/attr-gnu-4-72.d, * testsuite/ld-mips-elf/attr-gnu-4-73.d, * testsuite/ld-mips-elf/attr-gnu-4-74.d, * testsuite/ld-mips-elf/attr-gnu-4-78.d, * testsuite/ld-mips-elf/attr-gnu-4-79.d, * testsuite/ld-mips-elf/attr-gnu-4-81.d, * testsuite/ld-mips-elf/attr-gnu-4-89.d, * testsuite/ld-mips-elf/attr-gnu-8-12.d, * testsuite/ld-mips-elf/attr-gnu-8-21.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d, * testsuite/ld-mips-elf/bal-jalx-pic-micromips.d, * testsuite/ld-mips-elf/bal-jalx-pic-n32.d, * testsuite/ld-mips-elf/bal-jalx-pic-n64.d, * testsuite/ld-mips-elf/bal-jalx-pic.d, * testsuite/ld-mips-elf/mode-change-error-1.d, * testsuite/ld-mips-elf/unaligned-branch-2.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d, * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d, * testsuite/ld-mips-elf/unaligned-branch-micromips.d, * testsuite/ld-mips-elf/unaligned-branch-mips16.d, * testsuite/ld-mips-elf/unaligned-branch-r6-1.d, * testsuite/ld-mips-elf/unaligned-branch-r6-2.d, * testsuite/ld-mips-elf/unaligned-branch.d, * testsuite/ld-mips-elf/unaligned-jalx-1.d, * testsuite/ld-mips-elf/unaligned-jalx-3.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-1.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-3.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d, * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d, * testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d, * testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d, * testsuite/ld-mips-elf/unaligned-jump-micromips.d, * testsuite/ld-mips-elf/unaligned-jump-mips16.d, * testsuite/ld-mips-elf/unaligned-jump.d: Update.
2018-02-22Diagnose when trying to assemble conditional FP16 vmovx and vinsAndre Simoes Dias Vieira2-205/+265
This patch makes GAS emit a warning when trying to assemble the Armv8.2 FP16 instructions VMOVX and VINS with condition codes. The Armv8-A Reference Manual specifies these instructions without conditional codes and says that if they are found in an IT block that they are CONSTRAINED UNPREDICABLE. gas/ChangeLog: 2018-02-22 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_movhf): If conditional error out when in arm mode and emit warning in thumb mode. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: Add new tests. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: Idem.
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu2-0/+52
Add {rex} pseudo prefix to generate a REX byte for integer and legacy vector instructions if possible. Note that this differs from the rex prefix which generates REX prefix unconditionally. gas/ * config/tc-i386.c (_i386_insn): Add rex_encoding. (md_assemble): When i.rex_encoding is true, generate a REX byte if possible. (parse_insn): Set i.rex_encoding for {rex}. * doc/c-i386.texi: Document {rex}. * testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests. * testsuite/gas/i386/x86-64-pseudos.d: Updated. opcodes/ * i386-opc.tbl: Add {rex}, * i386-tbl.h: Regenerated.
2018-02-20MIPS16/GAS/testsuite: Add cross-section R_MIPS16_PC16_S1 relocation testsMaciej W. Rozycki5-0/+114
Add a pair of MIPS16 branch tests to verify correct R_MIPS16_PC16_S1 relocation generation for cross-section references in a single source. This complements commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support"). gas/ * testsuite/gas/mips/mips16-branch-reloc-4.d: New test. * testsuite/gas/mips/mips16-branch-reloc-5.d: New test. * testsuite/gas/mips/mips16-branch-reloc-4.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-5.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2018-02-20gas: xtensa: limit size of auto litpoolsMax Filippov5-3/+19
Literal movement code may grow auto litpool so big that it won't be possible to jump around it. Limit the size of auto litpools by 1/2 of the jump range. gas/ 2018-02-20 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (struct litpool_frag): Add new field literal_count. (MAX_AUTO_POOL_LITERALS, MAX_EXPLICIT_POOL_LITERALS) (MAX_POOL_LITERALS): New macro definitions. (auto_litpool_limit): Initialize to 0. (md_parse_option): Set auto_litpool_limit in the presence of --auto-litpools option. (xtensa_maybe_create_literal_pool_frag): Zero-initialize literal_count field. (xg_find_litpool): New function. Make sure that found literal pool size is within the limit. (xtensa_move_literals): Extract literal pool search code into the new function. * testsuite/gas/xtensa/all.exp: Add auto-litpools-2 test. * testsuite/gas/xtensa/auto-litpools-2.d: New file. * testsuite/gas/xtensa/auto-litpools-2.s: New file. * testsuite/gas/xtensa/auto-litpools.d: Fix up changed addresses. * testsuite/gas/xtensa/auto-litpools.s: Change literal value so that objdump doesn't get out of sync.
2018-02-17Add .nop assembler directiveH.J. Lu21-0/+459
Implement the '.nop SIZE[, CONTROL]' assembler directive, which emits SIZE bytes filled with no-op instructions. SIZE is absolute expression. The optional CONTROL byte controls how no-op instructions should be generated. If the comma and @var{control} are omitted, CONTROL is assumed to be zero. For Intel 80386 and AMD x86-64 targets, CONTROL byte specifies the size limit of a single no-op instruction. The valid values of CONTROL byte are between 0 and 8 for 16-bit mode, between 0 and 10 for 32-bit mode, between 0 and 11 for 64-bit mode. When 0 is used, the no-op size limit is set to the maximum supported size. 2 new relax states, rs_space_nop and rs_fill_nop, are added to enum _relax_state, which are similar to rs_space and rs_fill, respectively, but they fill with no-op instructions, instead of a single byte. A target backend must override the default md_generate_nops to generate proper no-op instructions. Otherwise, an error of unimplemented .nop directive will be issued whenever .nop directive is used. * NEWS: Mention .nop directive. * as.h (_relax_state): Add rs_space_nop and rs_fill_nop. * read.c (potable): Add .nop. (s_nop): New function. * read.h (s_nop): New prototype. * write.c (cvt_frag_to_fill): Handle rs_space_nop and rs_fill_nop. (md_generate_nops): New function. (relax_segment): Likewise. (write_contents): Use md_generate_nops for rs_fill_nop. * config/tc-i386.c (alt64_11): New. (alt64_patt): Likewise. (md_convert_frag): Handle rs_space_nop. (i386_output_nops): New function. (i386_generate_nops): Likewise. (i386_align_code): Call i386_output_nops. * config/tc-i386.h (i386_generate_nops): New. (md_generate_nops): Likewise. * doc/as.texinfo: Document .nop directive. * testsuite/gas/i386/i386.exp: Run .nop directive tests. * testsuite/gas/i386/nop-1.d: New file. * testsuite/gas/i386/nop-1.s: Likewise. * testsuite/gas/i386/nop-2.d: Likewise. * testsuite/gas/i386/nop-2.s: Likewise. * testsuite/gas/i386/nop-3.d: Likewise. * testsuite/gas/i386/nop-3.s: Likewise. * testsuite/gas/i386/nop-4.d: Likewise. * testsuite/gas/i386/nop-4.s: Likewise. * testsuite/gas/i386/nop-5.d: Likewise. * testsuite/gas/i386/nop-5.s: Likewise. * testsuite/gas/i386/nop-6.d: Likewise. * testsuite/gas/i386/nop-6.s: Likewise. * testsuite/gas/i386/nop-bad-1.l: Likewise. * testsuite/gas/i386/nop-bad-1.s: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-nop-2.d: Likewise. * testsuite/gas/i386/x86-64-nop-3.d: Likewise. * testsuite/gas/i386/x86-64-nop-4.d: Likewise. * testsuite/gas/i386/x86-64-nop-5.d: Likewise. * testsuite/gas/i386/x86-64-nop-6.d: Likewise.
2018-02-15Fix AArch32 build attributes for Armv8.4-A.Tamar Christina1-0/+17
The build attribute number for Armv8.4-A is currently incorrectly set to that of Armv8-M. This patch fixes that by setting it as part of the Armv8-A family and adds a test for it. gas/ 2018-02-15 Tamar Christina <tamar.christina@arm.com> * config/tc-arm.c (cpu_arch_ver): Renumber ARM_ARCH_V8_4A. * testsuite/gas/arm/attr-march-armv8_4-a.d: New.
2018-02-13Fix ARm assembler so that it rejects invalid immediate values for the Thumb ↵Nick Clifton3-0/+14
ORR instruction. PR 22773 * config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR instruction before assuming that it is a MOV instruction. * testsuite/gas/arm/pr22773.s: New test. * testsuite/gas/arm/pr22773.d: New test driver. * testsuite/gas/arm/pr22773.l: New expected output.
2018-02-13x86-64: Generate branch with PLT32 relocationH.J. Lu8-22/+22
Since there is no need to prepare for PLT branch on x86-64, generate R_X86_64_PLT32, instead of R_X86_64_PC32, if possible, which can be used as a marker for 32-bit PC-relative branches. To compile Linux kernel, this patch: From: "H.J. Lu" <hjl.tools@gmail.com> Subject: [PATCH] x86: Treat R_X86_64_PLT32 as R_X86_64_PC32 On i386, there are 2 types of PLTs, PIC and non-PIC. PIE and shared objects must use PIC PLT. To use PIC PLT, you need to load _GLOBAL_OFFSET_TABLE_ into EBX first. There is no need for that on x86-64 since x86-64 uses PC-relative PLT. On x86-64, for 32-bit PC-relative branches, we can generate PLT32 relocation, instead of PC32 relocation, which can also be used as a marker for 32-bit PC-relative branches. Linker can always reduce PLT32 relocation to PC32 if function is defined locally. Local functions should use PC32 relocation. As far as Linux kernel is concerned, R_X86_64_PLT32 can be treated the same as R_X86_64_PC32 since Linux kernel doesn't use PLT. is needed. It is available on hjl/plt32/master branch at https://github.com/hjl-tools/linux bfd/ PR gas/22791 * elf64-x86-64.c (is_32bit_relative_branch): Removed. (elf_x86_64_relocate_section): Check PIC relocations in PIE. Remove is_32bit_relative_branch usage. Disallow PC32 reloc against protected function in shared object. gas/ PR gas/22791 * config/tc-i386.c (need_plt32_p): New function. (output_jump): Generate BFD_RELOC_X86_64_PLT32 if possible. (md_estimate_size_before_relax): Likewise. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/x86-64-jump.d: Likewise. * testsuite/gas/i386/x86-64-mpx-branch-1.d: Likewise. * testsuite/gas/i386/x86-64-mpx-branch-2.d: Likewise. * testsuite/gas/i386/x86-64-relax-2.d: Likewise. * testsuite/gas/i386/x86-64-relax-3.d: Likewise. * testsuite/gas/i386/ilp32/reloc64.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. ld/ PR gas/22791 * testsuite/ld-x86-64/mpx1c.rd: Updated. * testsuite/ld-x86-64/pr22791-1.err: New file. * testsuite/ld-x86-64/pr22791-1a.c: Likewise. * testsuite/ld-x86-64/pr22791-1b.s: Likewise. * testsuite/ld-x86-64/pr22791-2.rd: Likewise. * testsuite/ld-x86-64/pr22791-2a.s: Likewise. * testsuite/ld-x86-64/pr22791-2b.c: Likewise. * testsuite/ld-x86-64/pr22791-2c.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run PR ld/22791 tests.
2018-02-13MIPS/GAS/testsuite: Correct duplicate `Loongson-3A tests' test nameMaciej W. Rozycki1-1/+1
Correct a duplicate `Loongson-3A tests' GAS test name introduced with commit 986754024085 ("Add Loongson3A specific instructions"), <https://sourceware.org/ml/binutils/2010-12/msg00447.html>, shared between gas/testsuite/gas/mips/loongson-3a.d and gas/testsuite/gas/mips/loongson-3a-2.d. gas/ * testsuite/gas/mips/loongson-3a-2.d: Rename test.
2018-02-12MIPS/GAS/test: Fix an n32 `.reginfo' size test failureMaciej W. Rozycki1-1/+1
Correct a commit 2d6dda71611b ("MIPS/BFD: Correctly report unsupported `.reginfo' section size") issue and avoid a GAS test failure: regexp_diff match failure regexp "^.*: Incorrect `\.reginfo' section size; expected 24, got 28$" line "../as-new: dump.o: Incorrect `.reginfo' section size; expected 24, got 32" FAIL: MIPS assembled .reginfo section size (n32) on MIPS targets other than bare-metal ones. The reason for this failure is section padding to alignment, done in `size_seg'. For n32 `.reginfo' the section alignment is set to 3, and therefore the section is padded to a multiple of 8, except for bare-metal targets, for which padding is unconditionally disabled in `md_section_align'. Use `--no-pad-sections' then to disable padding for all targets, so that the size of `.reginfo' is always the same, matching the message pattern. gas/ * testsuite/gas/mips/reginfo-2-n32.d: Add `--no-pad-sections' to `as' flags.
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong3-6/+6
The instruction encoding for the MIPS r6 sigrie instruction seems to be incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp, and dvp), but should be 0x0417xxxx. See ISA reference[1][2]. References: [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies, Inc., Document Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32 REGIMM Encoding of rt Field", p. 452 [2] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies, Inc., Document Number: MD00087, Revision 6.06, December 15, 2016, Table A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581 opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. gas/ * testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-08PR22819, powerpc gas "instruction address is not a multiple of 4"Alan Modra6-0/+29
Checks for insn alignment were hopelessly confused when misaligned data starts a new frag. The real-world testcase happened to run out of frag space in the middle of emitting a trace-back table via something like: .byte 0 /* VERSION=0 */ .byte 9 /* LANG=C++ */ .byte 34 /* Bits on: has_tboff, fp_present */ .byte 64 /* Bits on: name_present */ .byte 128 /* Bits on: stores_bc, FP_SAVED=0 */ .byte 0 /* Bits on: GP_SAVED=0 */ .byte 2 /* FIXEDPARMS=2 */ .byte 1 /* FLOATPARMS=0, parmsonstk */ .long 0 .long 768 /* tb_offset: 0x300 */ .hword 45 /* Function name length: 45 */ .long 0x334e5a5f .long 0x31766f70 .long 0x65744932 .long 0x69746172 .long 0x7a5f6e6f .long 0x64504533 .long 0x5f534e50 .long 0x72463431 .long 0x61746361 .long 0x74535f6c .long 0x74637572 .byte 0x45 .byte 0 The trigger being those misaligned .long's output for the function name. A most horrible way to output a string, especially considering endian issues.. PR 22819 * config/tc-ppc.c (md_assemble): Rewrite insn alignment checking. (ppc_frag_check): Likewise. * testsuite/gas/ppc/misalign.d, * testsuite/gas/ppc/misalign.l, * testsuite/gas/ppc/misalign.s: New test. * testsuite/gas/ppc/misalign2.d, * testsuite/gas/ppc/misalign2.s: New test. * testsuite/gas/ppc/ppc.exp: Run them.
2018-02-05MIPS/BFD: Correctly report unsupported `.reginfo' section sizeMaciej W. Rozycki5-0/+16
Report an error when an unsupported `.reginfo' section size is found in `_bfd_mips_elf_section_processing', removing an assertion that triggers at elfxx-mips.c:7105 in GAS when assembling input like: .section .reginfo .word 0xdeadbeef and in `objcopy --rename-section' when renaming an incorrectly sized section to `.reginfo'. bfd/ * elfxx-mips.c (_bfd_mips_elf_section_processing): For SHT_MIPS_REGINFO sections don't assert the correct size and report an error instead. binutils/ * testsuite/binutils-all/mips/mips-reginfo.d: New test. * testsuite/binutils-all/mips/mips-reginfo-n32.d: New test. * testsuite/binutils-all/mips/mips-reginfo.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/reginfo-2.d: New test. * testsuite/gas/mips/reginfo-2-n32.d: New test. * testsuite/gas/mips/reginfo-2.l: New test stderr output. * testsuite/gas/mips/reginfo-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2018-01-24[GAS][AARCH64]Add group relocations to create PC-relative offset.Renlin Li14-0/+155
This is a patch to add the gas support for group relocations to create a 16, 32, 48, or 64 bit PC-relative offset inline. The following relocations are added along with the test cases: BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. bfd/ 2018-01-24 Renlin Li <renlin.li@arm.com> * reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. gas/ 2018-01-24 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. (process_movw_reloc_info): Supports newly added MOVW_PREL relocations. (md_apply_fix): Likewise * testsuite/gas/aarch64/prel_g0.s: New. * testsuite/gas/aarch64/prel_g0.d: New. * testsuite/gas/aarch64/prel_g0_nc.s: New. * testsuite/gas/aarch64/prel_g0_nc.d: New. * testsuite/gas/aarch64/prel_g1.s: New. * testsuite/gas/aarch64/prel_g1.d: New. * testsuite/gas/aarch64/prel_g1_nc.s: New. * testsuite/gas/aarch64/prel_g1_nc.d: New. * testsuite/gas/aarch64/prel_g2.s: New. * testsuite/gas/aarch64/prel_g2.d: New. * testsuite/gas/aarch64/prel_g2_nc.s: New. * testsuite/gas/aarch64/prel_g2_nc.d: New. * testsuite/gas/aarch64/prel_g3.s: New. * testsuite/gas/aarch64/prel_g3.d: New.
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist7-0/+58
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist7-0/+58
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-22Fix the RX assembler so that it can handle escaped double quote characters, ↵Oleg Endo3-0/+17
ie: \" PR 22737 * config/tc-rx.c (rx_start_line): Handle escaped double-quote character. * testsuite/gas/rx/pr22737.s: New test. * testsuite/gas/rx/pr22737.d: Likewise. * testsuite/gas/rx/rx.exp: Run the new test.
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist9-0/+44
The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-2/+4
gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2018-01-15[ARM] Enable conditional Armv8-M instructionsThomas Preud'homme1-2/+11
Newly introduced instructions common to ARMv8-M Baseline and Mainline are currently all marked as unconditional. However, all instructions but sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually support conditional execution. This patch fixes the definition of these instructions accordingly. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm conditionally executable and reindent parameters. * testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of aforementionned instructions.
2018-01-15[ARM] No IT usage deprecation for ARMv8-MThomas Preud'homme5-48/+49
Deprecations related to the use of the IT instruction introduced in Armv8-A do not apply to Armv8-M Baseline and mainline. However the warning logic do not distinguish between the various profiles and warn whenever the architecture version is 8. This patch adds a check to exclude M profile architectures from this warning. This works as expected when -march is specified on the command-line or a .arch/.cpu directive exist. However, in autodetection mode the CPU/architecture targeted is only known once the instructions have been all processed but this code is run when IT instruction is processed. It is therefore not possible to distinguish between Armv8-M and Armv8-A in that mode. The approach chosen here is not to warn in autodetection mode. The udf.d testcase that relied on that behavior to test deprecation warning for Armv8-A is therefore updated to explicitely pass -march=armv8-a. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M profile architecture or if in autodetection mode. Clarify that deprecation is for performance reason and concerns Armv8-A and Armv8-R. * testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning message. * testsuite/gas/arm/armv8-ar-it-bad.l: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise. * testsuite/gas/arm/udf.l: Likewise. * testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist19-1030/+16
AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich12-381/+384
Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich6-0/+36
In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2-0/+16
gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh4-0/+19
CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-1/+1
CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu4-0/+136
For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson2-24/+28
gas/ * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval. * testsuite/gas/riscv/priv-reg.d: Likewise. include/ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL. (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry. Add alias to map mbadaddr to CSR_MTVAL.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra192-192/+192
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson2-0/+518
gas/ * testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New. include/ * opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers. Sort to match privileged spec documentation order. (DECLARE_CSR_ALIAS): Add ubadaddr, and comments.
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson12-0/+92
gas/ * config/tc-riscv.c (risc_ip) <o>: Add comment. * testsuite/gas/riscv/c-nonzero-imm.d, * testsuite/gas/riscv/c-nonzero-imm.l, * testsuite/gas/riscv/c-nonzero-imm.s, * testsuite/gas/riscv/c-nonzero-reg.d, * testsuite/gas/riscv/c-nonzero-reg.l, * testsuite/gas/riscv/c-nonzero-reg.s, * testsuite/gas/riscv/c-zero-imm-64.d, * testsuite/gas/riscv/c-zero-imm-64.s, * testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s, * testsuite/gas/riscv/c-zero-reg.d, * testsuite/gas/riscv/c-zero-reg.s: New. opcodes/ * riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New. (riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co. <andi, and, add, addiw, addw, c.addi>: Change Cj to Co. <add>: Add explanatory comment for 4-operand add instruction. <c.nop>: Add support for immediate operand. <c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add. <c.lui>: Use match_c_lui_with_hint instead of match_c_lui. <c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-432/+432
Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina3-0/+24
Previously parse_vector_type_for_operand was changed to allow the use of 4b register size for indexed lane instructions. However this had the unintended side effect of also allowing 4b for normal vector registers. Because this support was only partial the rest of the tool silently treated 4b as 8b and continued. This patch adds full support for 4b so it can be properly distinguished from 8b and the correct errors are generated. With this patch you still can't encode any instruction which actually requires v<num>.4b but such instructions don't exist so to prevent needing a workaround in get_vreg_qualifier_from_value this was just omitted. gas/ PR gas/22529 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B. * gas/testsuite/gas/aarch64/pr22529.s: New. * gas/testsuite/gas/aarch64/pr22529.d: New. * gas/testsuite/gas/aarch64/pr22529.l: New. include/ PR gas/22529 * opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B. opcodes/ PR gas/22529 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-45/+45
... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time.
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu3-0/+17
Pseudo prefixes must be used on an instruction. Issue an error when pseudo prefix is used without instruction. PR gas/22623 * gas/config/tc-i386.c (output_insn): Check pseudo prefix without instruction. * testsuite/gas/i386/i386.exp: Run inval-pseudo. * testsuite/gas/i386/inval-pseudo.l: New file. * testsuite/gas/i386/inval-pseudo.s: Likewise.
2017-12-14Update the address of the FSF in the copyright notice of files which were ↵Nick Clifton1-3/+3
using the old address. top * COPYING.LIBGLOSS: Update address of FSF in copyright notice. bfd * cpu-mt.c: Update address of FSF in copyright notice. * elf32-m32c.c: Likewise. * elf32-mt.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-rx.h: Likewise. * elf32-spu.h: Likewise. * hosts/x86-64linux.h: Likewise. etc * add-log.el: Update address of FSF in copyright notice. gas * config/tc-m32c.c: Update address of FSF in copyright notice. * config/tc-m32c.h: Likewise. * config/tc-mt.c: Likewise. * config/tc-mt.h: Likewise. * config/tc-visium.c: Likewise. * config/tc-visium.h: Likewise. * testsuite/gas/rx/explode: Likewise. ld * testsuite/ld-mn10300/mn10300.exp: Update address of FSF in copyright notice.
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson2-0/+17
PR 22599 gas/ * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print ↵Dimitar Dimitrov2-0/+15
correct symbols when disassembling arguments of "call" instructions with a relocation. opcodes * disassemble.c: Enable disassembler_needs_relocs for PRU. gas * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM relocation. * testsuite/gas/pru/extern.d: New test driver.
2017-12-04Run powerpc vle gas tests for all powerpc ELF targetsAlan Modra18-39/+37
* testsuite/gas/ppc/ppc.exp: Don't exclude VLE tests when little-endian. * testsuite/gas/ppc/efs.d: Add -mbig to assembler options. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/lsp-checks.d: Likewise. * testsuite/gas/ppc/lsp.d: Likewise. * testsuite/gas/ppc/spe.d: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/vle-mult-ld-st-insns.d: Likewise. * testsuite/gas/ppc/vle-reloc.d: Likewise. * testsuite/gas/ppc/vle-simple-1.d: Likewise. * testsuite/gas/ppc/vle-simple-2.d: Likewise. * testsuite/gas/ppc/vle-simple-3.d: Likewise. * testsuite/gas/ppc/vle-simple-4.d: Likewise. * testsuite/gas/ppc/vle-simple-5.d: Likewise. * testsuite/gas/ppc/vle-simple-6.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise.
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich4-4/+26
While we shouldn't outright reject such (as was wrongly done by commit 4d36230d59 ("x86: Update segment register check in Intel syntax"), as MASM accepts them even silently, issue (by default) a warning for such questionable constructs.
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich5-43/+11
This reverts commit 4d36230d59903b92fbe2b53b31ed64a884860f0e. I was committed without maintainer ack and regresses intended functionality. A replacement will be committed shortly.
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson3-9/+6
gas/ * config/tc-riscv.c (riscv_frag_align_code): New local insn_alignment. Early return if bytes less than or equal to insn_alignment. * testsuite/gas/riscv/align-1.l: New. * testsuite/gas/riscv/align-1.s: New. * testsuite/gas/riscv/riscv.exp: Use run_dump_tests. Use run_list_test for align-1.
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li2-1/+5
This should be an obvious fix. It corrects the register number for IP1 to 17. gas/ 2017-11-29 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reg_names): Fix IP1 register alias error. * testsuite/gas/aarch64/register_aliases.s: Add IP0 and IP1 tests. * testsuite/gas/aarch64/register_aliases.d: Update.
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson5-0/+54
gas/ * config/tc-riscv.c (riscv_handle_implicit_zero_offset): New. (riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to riscv_handle_implicit_zero_offset. At label load_store, replace existing code with call to riscv_handle_implicit_zero_offset. * testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New. * testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New. * testsuite/gas/riscv/riscv.exp: Run new tests.
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov5-16/+38
There is a recurring pattern in assembly files generated by a compiler where a lot of jumps in a function are going to the same place. When these jumps are relaxed with trampolines the assembler generates a separate jump thread from each source. Create an index of trampoline jump targets for each segment and see if a jump being relaxed goes to a location from that index, in which case replace its target with a location of existing trampoline jump that results in the shortest path to the original target. gas/ 2017-11-27 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (trampoline_chain_entry, trampoline_chain) (trampoline_chain_index): New structures. (trampoline_index): Add chain_index field. (xg_order_trampoline_chain_entry, xg_sort_trampoline_chain) (xg_find_chain_entry, xg_get_best_chain_entry) (xg_order_trampoline_chain, xg_get_trampoline_chain) (xg_find_best_eq_target, xg_add_location_to_chain) (xg_create_trampoline_chain, xg_get_single_symbol_slot): New functions. (xg_relax_fixups): Call xg_find_best_eq_target to adjust jump target to point to an existing jump. Call xg_create_trampoline_chain to create new jump target. Call xg_add_location_to_chain to add newly created trampoline jump to the corresponding chain. (add_jump_to_trampoline): Extract loop searching for a single slot with a symbol into a separate function, replace that code with a call to that function. (relax_frag_immed): Call xg_find_best_eq_target to adjust jump target to point to an existing jump. * testsuite/gas/xtensa/all.exp: Add trampoline-2 test. * testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses as many duplicate trampoline chains are now coalesced. * testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump stays in sync with instruction stream. * testsuite/gas/xtensa/trampoline-2.l: New test result file. * testsuite/gas/xtensa/trampoline-2.s: New test source file.
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