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2006-05-25include/opcodes/Richard Sandiford3-0/+21
* m68k.h (mcf_mask): Define. opcodes/ * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd and fmovem entries. Put register list entries before immediate mask entries. Use "l" rather than "L" in the fmovem entries. * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it out from INFO. (m68k_scan_mask): New function, split out from... (print_insn_m68k): ...here. If no architecture has been set, first try printing an m680x0 instruction, then try a Coldfire one. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions. * gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-05-25 * gas/bfin/vector2.s, gas/bfin/vector2.d: Test to ensure (m) is notJie Zhang3-0/+13
thrown away.
2006-05-23 [ gas/ChangeLog ]Thiemo Seufer8-2/+19
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename. (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS, ISA_HAS_MXHC1): New macros. (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments. (mips_cpu_info): Change to use combined ASE/IS_ISA flag. (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines. (mips_after_parse_args): Change default handling of float register size to account for 32bit code with 64bit FP. Better sanity checking of ISA/ASE/ABI option combinations. (s_mipsset): Support switching of GPR and FPR sizes via .set {g,f}p={32,64,default}. Better sanity checking for .set ASE options. (mips_elf_final_processing): We should record the use of 64bit FP registers in 32bit code but we don't, because ELF header flags are a scarce ressource. (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef, 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions. (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA. * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document missing -march options. Document .set arch=CPU. Move .set smartmips to ASE page. Use @code for .set FOO examples. [ gas/testsuite/Changelog ] * gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d, gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l, gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler output. * gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files, catch assembler warnings.
2006-05-22* gas/mips/mips32-dsp.l: Fix expected unsigned decoding of -1 in warning ↵Nick Clifton3-145/+151
messages. * gas/mips/mips32-mt.l: Likewise.
2006-05-19 * gas/mips/vxworks1-el.d, gas/mips/vxworks1-xgot-el.d: Add littleThiemo Seufer6-2/+187
endian testcases. * gas/mips/vxworks1.d, gas/mips/vxworks1-xgot.d: Build as big endian. * gas/mips/mips.exp: Run new testcases.
2006-05-14 [ gas/ChangeLog ]Thiemo Seufer7-0/+150
* config/tc-mips.c (macro_build): Test for currently active mips16 option. (mips16_ip): Reject invalid opcodes. [ opcodes/ChangeLog ] * mips16-opc.c (I1, I32, I64): New shortcut defines. (mips16_opcodes): Change membership of instructions to their lowest baseline ISA. [ gas/testsuite/ChangeLog ] * gas/mips/mips.exp: Run new tests. * gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s, gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
2006-05-112006-05-11 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+25
gas/ * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols. gas/testsuite/ * gas/arm/local_function.d: New test. * gas/arm/local_function.s: New test.
2006-05-11 [ gas/ChangeLog ]Thiemo Seufer3-2/+8
* config/tc-mips.c (append_insn): Don't check the range of j or jal addresses. [ gas/testsuite/ChangeLog ] * gas/mips/jal-range.l: Don't check the range of j or jal addresses.
2006-05-092006-05-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-8/+12
* gas/i386/x86-64-gidt.d: Adjusted.
2006-05-09gas/testsuite/H.J. Lu4-0/+39
2006-05-09 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-gidt. * gas/i386/x86-64-gidt.d: New file. * gas/i386/x86-64-gidt.s: Likewise. opcodes/ 2006-05-09 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (grps): Update sgdt/sidt for 64bit.
2006-05-09 [ gas/ChangeLog ]Thiemo Seufer2-1/+6
* config/tc-mips.c (append_insn): Only warn about an out-of-range j or jal address. [ gas/testsuite/ChangeLog ] * gas/mips/jal-range.l: Only warn about an out-of-range j or jal address.
2006-05-08 * gas/mips/mips32.s, gas/mips/mips32.d: Extend testcase to checkThiemo Seufer3-16/+37
larger offset arguments for cache instructions.
2006-05-08 [ gas/ChangeLog ]Thiemo Seufer4-0/+68
* config/tc-mips.c (mips_set_options): Add ase_smartmips flag. (mips_opts): Likewise. (file_ase_smartmips): New variable. (ISA_HAS_ROR): SmartMIPS implements rotate instructions. (macro_build): Handle SmartMIPS instructions. (mips_ip): Likewise. (md_longopts): Add argument handling for smartmips. (md_parse_options, mips_after_parse_args): Likewise. (s_mipsset): Add .set smartmips support. (md_show_usage): Document -msmartmips/-mno-smartmips. * doc/as.texinfo: Document -msmartmips/-mno-smartmips and .set smartmips. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] * gas/mips/smartmips.s, gas/mips/smartmips.d: New smartmips test. * gas/mips/mips.exp: Run smartmips test.
2006-05-05 * gas/arm/vfp-neon-overlap.s: New test. Overlapping VFP/NeonJulian Brown6-73/+158
instructions. * gas/arm/vfp-neon-overlap.d: Expected output of above. * gas/arm/vfp1xD.d: Test for fldmx/fstmx. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfpv3-32drs.d: Likewise.
2006-05-05 * gas/mips/noreorder.s, gas/mips/noreorder.d: New test forThiemo Seufer4-0/+56
reorder/noreorder corner case. * gas/mips/mips.exp: Run new test. -------------------------------------------------------------------
2006-05-04gas/Kazu Hirata5-0/+31
* config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated. (opcode_lookup): Issue a warning for opcode with OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated identical to OT_cinfix3. (TxC3w, TC3w, tC3w): New. (insns): Use tC3w and TC3w for comparison instructions with 's' suffix. gas/testsuite * gas/arm/armv1.d (error-output): New. * gas/arm/armv1.l: New. * gas/arm/thumb32.d (error-output): New. * gas/arm/thumb32.l: New.
2006-05-04[ gas/testsuite/ChangeLog ]Thiemo Seufer3-5/+11
2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> * gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2. * gas/mips/set-arch.d: Adjust according to opcode table changes. [ include/opcode/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. [ opcodes/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips-dis.c (mips_arch_choices): Add smartmips instruction decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to MIPS64R2. * mips-opc.c: fix random typos in comments. (INSN_SMARTMIPS): New defines. (mips_builtin_opcodes): Add paired single support for MIPS32R2. Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the FP_S and FP_D flags to denote single and double register accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 for MIPS32R2. Add SmartMIPS instructions. Add two-argument variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to release 2 ISAs. * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
2006-05-032006-05-03 Thiemo Seufer <ths@mips.com>Thiemo Seufer2-129/+133
[ opcodes/ChangeLog ] * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-mt.d: Fix mftr argument order.
2006-05-02 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4Joseph Myers5-4/+19
here. (md_apply_fix3): Multiply offset by 4 here for BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. testsuite: * gas/arm/iwmmxt.s: Increase offsets for wstrb and wstrh. * gas/arm/iwmmxt.d: Update expected results. * gas/arm/iwmmxt-bad2.s: Test wstrb, wstrh, wldrb and wldrh. * gas/arm/iwmmxt-bad2.l: Update expected error messages.
2006-04-302006-04-29 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu4-0/+29
* gas/i386/fp.d: New file. * gas/i386/fp.s: Likewise. * gas/i386/i386.exp: Run "fp".
2006-04-28Don't mis-spell your boss' name...Thiemo Seufer1-1/+1
2006-04-28[ opcodes/ChangeLog ]Thiemo Seufer3-47/+52
2006-04-28 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> Nigel Stevens <nigel@mips.com> * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register names. [ gas/testsuite/ChangeLog ] 2006-04-28 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> Nigel Stevens <nigel@mips.com> * gas/mips/cp0sel-names-mips32r2.d, gas/mips/cp0sel-names-mips64r2.d: Update for MT register names.
2006-04-26 * gas/testsuite/gas/arm/neon-const.s: New testcase. Neon floating-pointJulian Brown4-2/+572
constants. * gas/testsuite/gas/arm/neon-const.d: Expected output of above. * gas/testsuite/gas/arm/neon-cov.d: Expect floating-point disassembly for VMOV.F32.
2006-04-26 * gas/arm/neon-psyn.s: Basic test of programmers syntax.Julian Brown3-1/+121
* gas/arm/neon-psyn.d: Expected output of above.
2006-04-26 * gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon instruction.Julian Brown23-232/+2666
* gas/arm/copro.d: Update accordingly. * gas/arm/neon-cond.s: New test. Conditional Neon opcodes in ARM mode. * gas/arm/neon-cond.d: Expected results of above. * gas/arm/neon-cov.s: New test. Coverage of Neon instructions. * gas/arm/neon-cov.d: Expected results of above. * gas/arm/neon-ldst-es.s: New test. Element and structure loads and stores. * gas/arm/neon-ldst-es.d: Expected results of above. * gas/arm/neon-ldst-rm.s: New test. Single and multiple register loads and stores. * gas/arm/neon-ldst-rm.d: Expected results of above. * gas/arm/neon-omit.s: New test. Omission of optional operands. * gas/arm/neon-omit.d: Expected results of above. * gas/arm/vfp1.d: Expect Neon syntax for some VFP instructions. * gas/arm/vfp1_t2.d: Likewise. * gas/arm/vfp1xD.d: Likewise. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise. * gas/arm/vfp3-32drs.s: New test. Extended D register range for VFP instructions. * gas/arm/vfp3-32drs.d: Expected results of above. * gas/arm/vfp3-const-conv.s: New test. VFPv3 constant-load and conversion instructions. * gas/arm/vfp3-const-conv.d: Expected results of above.
2006-04-26Add missing changelog entryAndreas Jaeger1-0/+6
2006-04-202005-04-20 Paul Brook <paul@codesourcery.com>Paul Brook5-4/+7
gas/ * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for all targets. (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets. gas/testsuite/ * gas/arm/arch7.d: Remove skip. * gas/arm/svc.d: Ditto. * gas/arm/thumb2_bcond.d: Ditto. * gas/arm/thumb2_it_bad.d: Ditto.
2006-04-18gas/H.J. Lu3-0/+10
2006-04-18 H.J. Lu <hongjiu.lu@intel.com> PR gas/2533 * config/tc-i386.c (i386_immediate): Check illegal immediate register operand. gas/testsuite/ 2006-04-18 H.J. Lu <hongjiu.lu@intel.com> PR gas/2533 * gas/i386/inval.s: Add test for illegal immediate register operand. * gas/i386/inval.l: Updated.
2006-04-16Skip ELF specific tests on non-ELF ARM targetsNick Clifton6-0/+13
2006-04-072006-04-07 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+35
gas/ * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction. gas/testsuite/ * gas/arm/blx-local.d: New test. * gas/arm/blx-local.d: New test.
2006-04-072006-04-07 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+33
gas/ * config/tc-arm.c (THUMB2_LOAD_BIT): Define. (move_or_literal_pool): Handle Thumb-2 instructions. (do_t_ldst): Call move_or_literal_pool for =N addressing modes. gas/testsuite/ * gas/arm/thumb2_pool.d: New test. * gas/arm/thumb2_pool.s: New test.
2006-04-05bfd/Richard Sandiford4-1/+48
* config.bfd (sparc-*-vxworks*): New stanza. * configure.in (bfd_elf32_sparc_vxworks_vec): New stanza. (bfd_elf32_sparc_vec, bfd_elf64_sparc_vec): Add elf-vxworks.lo. * configure: Regenerate. * elf32-sparc.c: Include elf-vxworks.h. (elf32_sparc_vxworks_link_hash_table_create: New. (elf32_sparc_vxworks_final_write_processing): New. (TARGET_BIG_SYM): Override for VxWorks. (TARGET_BIG_NAME, ELF_MINPAGESIZE): Likewise. (bfd_elf32_bfd_link_hash_table_create): Likewise. (elf_backend_want_got_plt, elf_backend_plt_readonly): Likewise. (elf_backend_got_header_size, elf_backend_add_symbol_hook): Likewise. (elf_backend_link_output_symbol_hook): Likewise. (elf_backend_emit_relocs): Likewise. (elf_backend_final_write_processing, elf32_bed): Likewise. * elfxx-sparc.c: Include libiberty.h and elf-vxworks.h. (sparc_vxworks_exec_plt0_entry, sparc_vxworks_exec_plt_entry): New. (sparc_vxworks_shared_plt0_entry, sparc_vxworks_shared_plt_entry): New. (_bfd_sparc_elf_link_hash_table_create): Don't initialize build_plt_entry here. (create_got_section): Initialize sgotplt for VxWorks. (_bfd_sparc_elf_create_dynamic_sections): Initialize build_plt_entry, plt_header_size and plt_entry_size, with new VxWorks-specific settings. Call elf_vxworks_create_dynamic_sections for VxWorks. (allocate_dynrelocs): Use plt_header_size and plt_entry_size. Allocate room for .got.plt and .rela.plt.unloaded entries on VxWorks. (_bfd_sparc_elf_size_dynamic_sections): Don't allocate a nop in .plt for VxWorks. Check for the .got.plt section. (sparc_vxworks_build_plt_entry): New function. (_bfd_sparc_elf_finish_dynamic_symbol): Add handling of VxWorks PLTs. Don't make _GLOBAL_OFFSET_TABLE_ and _PROCEDURE_LINKAGE_TABLE_ absolute on VxWorks. (sparc32_finish_dyn): Add special handling for DT_RELASZ and DT_PLTGOT on VxWorks. (sparc_vxworks_finish_exec_plt): New. (sparc_vxworks_finish_shared_plt): New. (_bfd_sparc_elf_finish_dynamic_sections): Call them. Use plt_header_size and plt_entry_size. * elfxx-sparc.h (_bfd_sparc_elf_link_hash_table): Add is_vxworks, srelplt2, sgotplt, plt_header_size and plt_entry_size fields. * Makefile.am (elfxx-sparc.lo): Depend on elf-vxworks.h. (elf32-sparc.lo): Likewise. * Makefile.in: Regenerate. * targets.c (bfd_elf32_sparc_vxworks_vec): Declare. (_bfd_target_vector): Add a pointer to it. gas/ * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS. (GOTT_BASE, GOTT_INDEX): New. (tc_gen_reloc): Don't alter relocations against GOTT_BASE and GOTT_INDEX when generating VxWorks PIC. * configure.tgt (sparc*-*-vxworks*): Remove this special case; use the generic *-*-vxworks* stanza instead. gas/testsuite/ * gas/sparc/vxworks-pic.s, gas/sparc/vxworks-pic.d: New test. * gas/sparc/sparc.exp: Run it. Remove sparc*-*-vxworks* XFAILs. ld/ * configure.tgt (sparc*-*-vxworks*): New stanza. * emulparams/elf32_sparc_vxworks.sh: New file. * Makefile.am (ALL_EMULATIONS): Add eelf32_sparc_vxworks.o. (eelf32_sparc_vxworks.c): New rule. * Makefile.in: Regenerate. ld/testsuite/ * ld-sparc/vxworks1.dd, ld-sparc/vxworks1.ld, ld-sparc/vxworks1-lib.dd, * ld-sparc/vxworks1-lib.nd, ld-sparc/vxworks1-lib.rd, * ld-sparc/vxworks1-lib.s, ld-sparc/vxworks1.rd, ld-sparc/vxworks1.s, * ld-sparc/vxworks1-static.d, ld-sparc/vxworks2.s, * ld-sparc/vxworks2.sd, ld-sparc/vxworks2-static.sd: New tests. * ld-sparc/sparc.exp: Run them.
2006-03-242006-03-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu3-0/+8
* gas/i386/rep.s: Pad with .p2align. * gas/i386/rep.d: Adjust.
2006-03-23Patch by matz@suse.de:Andreas Jaeger3-7/+7
bfd/ChangeLog: * reloc.c: Add BFD_RELOC_X86_64_GOT64, BFD_RELOC_X86_64_GOTPCREL64, BFD_RELOC_X86_64_GOTPC64, BFD_RELOC_X86_64_GOTPLT64, BFD_RELOC_X86_64_PLTOFF64. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf64-x86-64.c (x86_64_elf_howto_table): Correct comment. Add howtos for above relocs. (x86_64_reloc_map): Add mappings for new relocs. (elf64_x86_64_check_relocs): R_X86_64_GOT64, R_X86_64_GOTPCREL64, R_X86_64_GOTPLT64 need a got entry. R_X86_64_GOTPLT64 also a PLT entry. R_X86_64_GOTPC64 needs a .got section. R_X86_64_PLTOFF64 needs a PLT entry. (elf64_x86_64_gc_sweep_hook): Reflect changes from elf64_x86_64_check_relocs for the new relocs. (elf64_x86_64_relocate_section): Handle new relocs. gas/ChangeLog: * config/tc-i386.c (type_names): Correct placement of 'static'. (reloc): Map some more relocs to their 64 bit counterpart when size is 8. (output_insn): Work around breakage if DEBUG386 is defined. (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing different from i386. (output_imm): Ditto. (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also Imm64. (md_convert_frag): Jumps can now be larger than 2GB away, error out in that case. (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64. gas/testsuite/ChangeLog: * gas/i386/reloc64.s: Accept 64-bit forms. * gas/i386/reloc64.d: Adjust. * gas/i386/reloc64.l: Adjust. include/ChangeLog: * elf/x86-64.h: Add the new relocations with their official numbers.
2006-03-22 Richard Sandiford <richard@codesourcery.com>Richard Sandiford5-4/+203
Daniel Jacobowitz <dan@codesourcery.com> Phil Edwards <phil@codesourcery.com> Zack Weinberg <zack@codesourcery.com> Mark Mitchell <mark@codesourcery.com> Nathan Sidwell <nathan@codesourcery.com> bfd/ * bfd-in2.h: Regenerate. * config.bfd (mips*-*-vxworks*, mips*el-*-vxworks*): New stanzas. * configure.in (bfd_elf32_bigmips_vxworks_vec): New stanza. (bfd_elf32_littlemips_vxworks_vec): Likewise. (bfd_elf32_bigmips_vec): Add elf-vxworks.lo. (bfd_elf32_littlemips_vec): Likewise. (bfd_elf32_nbigmips_vec): Likewise. (bfd_elf32_nlittlemips_vec): Likewise. (bfd_elf32_ntradbigmips_vec): Likewise. (bfd_elf32_ntradlittlemips_vec): Likewise. (bfd_elf32_tradbigmips_vec): Likewise. (bfd_elf32_tradlittlemips_vec): Likewise. (bfd_elf64_bigmips_vec): Likewise. (bfd_elf64_littlemips_vec): Likewise. (bfd_elf64_tradbigmips_vec): Likewise. (bfd_elf64_tradlittlemips_vec): Likewise. * elf32-mips.c: Include elf-vxworks.h. (mips_info_to_howto_rel): Use elf_backend_mips_rtype_to_howto instead of calling mips_elf32_rtype_to_howto directly. (mips_vxworks_copy_howto_rela): New reloc howto. (mips_vxworks_jump_slot_howto_rela): Likewise. (mips_vxworks_bfd_reloc_type_lookup): New function. (mips_vxworks_rtype_to_howto): Likewise. (mips_vxworks_final_write_processing): Likewise. (TARGET_LITTLE_SYM, TARGET_LITTLE_NAME): Override for VxWorks. (TARGET_BIG_SYM, TARGET_BIG_NAME, elf_bed, ELF_MAXPAGESIZE): Likewise. (elf_backend_want_got_plt): Likewise. (elf_backend_want_plt_sym): Likewise. (elf_backend_got_symbol_offset): Likewise. (elf_backend_want_dynbss): Likewise. (elf_backend_may_use_rel_p): Likewise. (elf_backend_may_use_rela_p): Likewise. (elf_backend_default_use_rela_p): Likewise. (elf_backend_got_header_size: Likewise. (elf_backend_plt_readonly): Likewise. (bfd_elf32_bfd_reloc_type_lookup): Likewise. (elf_backend_mips_rtype_to_howto): Likewise. (elf_backend_adjust_dynamic_symbol): Likewise. (elf_backend_finish_dynamic_symbol): Likewise. (bfd_elf32_bfd_link_hash_table_create): Likewise. (elf_backend_add_symbol_hook): Likewise. (elf_backend_link_output_symbol_hook): Likewise. (elf_backend_emit_relocs): Likewise. (elf_backend_final_write_processing: Likewise. (elf_backend_additional_program_headers): Likewise. (elf_backend_modify_segment_map): Likewise. (elf_backend_symbol_processing): Likewise. * elfxx-mips.c: Include elf-vxworks.h. (mips_elf_link_hash_entry): Add is_relocation_target and is_branch_target fields. (mips_elf_link_hash_table): Add is_vxworks, srelbss, sdynbss, srelplt, srelplt2, sgotplt, splt, plt_header_size and plt_entry_size fields. (MIPS_ELF_RELA_SIZE, MIPS_ELF_REL_DYN_NAME): New macros. (MIPS_RESERVED_GOTNO): Take a mips_elf_link_hash_table argument. Return 3 for VxWorks. (ELF_MIPS_GP_OFFSET): Change the argument from a bfd to a mips_elf_link_hash_table. Return 0 for VxWorks. (MIPS_ELF_GOT_MAX_SIZE): Change the argument from a bfd to a mips_elf_link_hash_table. Update the call to ELF_MIPS_GP_OFFSET. (mips_vxworks_exec_plt0_entry): New variable. (mips_vxworks_exec_plt_entry): Likewise. (mips_vxworks_shared_plt0_entry): Likewise. (mips_vxworks_shared_plt_entry): Likewise. (mips_elf_link_hash_newfunc): Initialize the new hash_entry fields. (mips_elf_rel_dyn_section): Change the bfd argument to a mips_elf_link_hash_table. Use MIPS_ELF_REL_DYN_NAME to get the name of the section. (mips_elf_initialize_tls_slots): Update the call to mips_elf_rel_dyn_section. (mips_elf_gotplt_index): New function. (mips_elf_local_got_index): Add an input_section argument. Update the call to mips_elf_create_local_got_entry. (mips_elf_got_page): Likewise. (mips_elf_got16_entry): Likewise. (mips_elf_create_local_got_entry): Add bfd_link_info and input_section arguments. Create dynamic relocations for each entry on VxWorks. (mips_elf_merge_gots): Update the use of MIPS_ELF_GOT_MAX_SIZE. (mips_elf_multi_got): Update the uses of MIPS_ELF_GOT_MAX_SIZE and MIPS_RESERVED_GOTNO. (mips_elf_create_got_section): Update the uses of MIPS_ELF_GOT_MAX_SIZE. Create .got.plt on VxWorks. (is_gott_symbol): New function. (mips_elf_calculate_relocation): Use a dynobj local variable. Update the calls to mips_elf_local_got_index, mips_elf_got16_entry and mips_elf_got_page_entry. Set G to the .got.plt entry when calculating VxWorks R_MIPS_CALL* relocations. Calculate and use G for all GOT relocations on VxWorks. Add dynamic relocations for references to the VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Don't create dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables. (mips_elf_allocate_dynamic_relocations): Add a bfd_link_info argument. Use MIPS_ELF_RELA_SIZE to calculate the size of a VxWorks entry. Don't allocate a null entry on VxWorks. (mips_elf_create_dynamic_relocation): Update the call to mips_elf_rel_dyn_section. Use absolute rather than relative relocations for VxWorks, and make them RELA rather than REL. (_bfd_mips_elf_create_dynamic_sections): Don't make .dynamic read-only on VxWorks. Update the call to mips_elf_rel_dyn_section. Create the .plt, .rela.plt, .dynbss and .rela.bss sections on VxWorks. Likewise create the _PROCEDURE_LINKAGE_TABLE symbol. Call elf_vxworks_create_dynamic_sections for VxWorks and initialize the plt_header_size and plt_entry_size fields. (_bfd_mips_elf_check_relocs): Don't allow GOT relocations to be used in VxWorks executables. Don't allocate dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables. Set is_relocation_target for each symbol referenced by a relocation. Allocate .rela.dyn entries for relocations against the special VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Create GOT entries for all VxWorks R_MIPS_GOT16 relocations. Don't allocate a global GOT entry for symbols mentioned in VxWorks R_MIPS_CALL*, R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 relocations. Update the calls to mips_elf_rel_dyn_section and mips_elf_allocate_dynamic_relocations. Set is_branch_target for symbols mentioned in R_MIPS_PC16 or R_MIPS_26 relocations. Don't set no_fn_stub on VxWorks. (_bfd_mips_elf_adjust_dynamic_symbol): Update the call to mips_elf_allocate_dynamic_relocations. (_bfd_mips_vxworks_adjust_dynamic_symbol): New function. (_bfd_mips_elf_always_size_sections): Do not allocate GOT page entries for VxWorks, and do not create multiple GOTs. (_bfd_mips_elf_size_dynamic_sections): Use MIPS_ELF_REL_DYN_NAME. Handle .got specially for VxWorks. Update the uses of MIPS_RESERVED_GOTNO and mips_elf_allocate_dynamic_relocations. Check for sgotplt and splt. Allocate the .rel(a).dyn contents last, once its final size is known. Set DF_TEXTREL for VxWorks. Add DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL tags on VxWorks. Do not add the MIPS-specific tags for VxWorks. (_bfd_mips_vxworks_finish_dynamic_symbol): New function. (mips_vxworks_finish_exec_plt): Likewise. (mips_vxworks_finish_shared_plt): Likewise. (_bfd_mips_elf_finish_dynamic_sections): Remove an unncessary call to mips_elf_rel_dyn_section. Use a VxWorks-specific value of DT_PLTGOT. Handle DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL. Update the uses of MIPS_RESERVED_GOTNO and mips_elf_rel_dyn_section. Use a different GOT header for VxWorks. Don't sort .rela.dyn on VxWorks. Finish the PLT on VxWorks. (_bfd_mips_elf_link_hash_table_create): Initialize the new mips_elf_link_hash_table fields. (_bfd_mips_vxworks_link_hash_table_create): New function. (_bfd_mips_elf_final_link): Set the GP value to _GLOBAL_OFFSET_TABLE_ on VxWorks. Update the call to ELF_MIPS_GP_OFFSET. * elfxx-mips.h (_bfd_mips_vxworks_adjust_dynamic_symbol): Declare. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. (_bfd_mips_vxworks_link_hash_table_create): Likewise. * libbfd.h: Regenerate. * Makefile.am (elfxx-mips.lo): Depend on elf-vxworks.h. (elf32-mips.lo): Likewise. * Makefile.in: Regenerate. * reloc.c (BFD_RELOC_MIPS_COPY, BFD_RELOC_MIPS_JUMP_SLOT): Declare. * targets.c (bfd_elf32_bigmips_vxworks_vec): Declare. (bfd_elf32_littlemips_vxworks_vec): Likewise. (_bfd_target_vector): Add entries for them. gas/ * config/tc-mips.c (mips_target_format): Handle vxworks targets. (md_begin): Complain about -G being used for PIC. Don't change the text, data and bss alignments on VxWorks. (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when generating VxWorks PIC. (load_address): Extend SVR4_PIC handling to VXWORKS_PIC. (macro): Likewise, but do not treat la $25 specially for VxWorks PIC, and do not handle jal. (OPTION_MVXWORKS_PIC): New macro. (md_longopts): Add -mvxworks-pic. (md_parse_option): Don't complain about using PIC and -G together here. Handle OPTION_MVXWORKS_PIC. (md_estimate_size_before_relax): Always use the first relaxation sequence on VxWorks. * config/tc-mips.h (VXWORKS_PIC): New. gas/testsuite/ * gas/mips/vxworks1.s, gas/mips/vxworks1.d, * gas/mips/vxworks1-xgot.d: New tests. * gas/mips/mips.exp: Run them. Do not run other tests on VxWorks. include/elf/ * mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs. ld/ * configure.tgt (mips*el-*-vxworks*, mips*-*-vxworks*): Use separate VxWorks emulations. * emulparams/elf32ebmipvxworks.sh: New file. * emulparams/elf32elmipvxworks.sh: New file. * Makefile.am (ALL_EMULATIONS): Add eelf32ebmipvxworks.o and eelf32elmipvxworks.o. (eelf32ebmipvxworks.c, eelf32elmipvxworks.c): New rules. * Makefile.in: Regenerate. ld/testsuite/ * ld-mips/vxworks1.dd, ld-mips/vxworks1.ld, ld-mips/vxworks1-lib.dd, * ld-mips/vxworks1-lib.nd, ld-mips/vxworks1-lib.rd, * ld-mips/vxworks1-lib.s, ld-mips/vxworks1.rd, ld-mips/vxworks1.s, * ld-mips/vxworks1-static.d, ld-mips/vxworks2.s, ld-mips/vxworks2.sd, * ld-mips/vxworks2-static.sd: New tests. * ld-mips/mips-elf.exp: Run them.
2006-03-212006-03-21 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+6
gas/ * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt. gas/testsuite/ * gas/arm/thumb32.d: Correct expected output.
2006-03-202006-03-20 Paul Brook <paul@codesourcery.com>Paul Brook6-0/+97
gas/ * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define. (do_t_branch): Encode branches inside IT blocks as unconditional. (do_t_cps): New function. (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi, do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints. (opcode_lookup): Allow conditional suffixes on all instructions in Thumb mode. (md_assemble): Advance condexec state before checking for errors. (insns): Use do_t_cps. gas/testsuite/ * gas/arm/thumb2_bcond.d: New test. * gas/arm/thumb2_bcond.s: New test. * gas/arm/thumb2_it_bad.d: New test. * gas/arm/thumb2_it_bad.l: New test. * gas/arm/thumb2_it_bad.s: New test.
2006-03-172006-03-17 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+26
gas/ * config/tc-arm.c (insns): Add ldm and stm. gas/testsuite/ * gas/arm/thumb32.d: Add ldm and stm tests. * gas/arm/thumb32.s: Ditto.
2006-03-16 * gas/bfin/shift2.s: Add new tests.Bernd Schmidt5-60/+128
* gas/bfin/shift.d: Match changed disassembler behaviour. * gas/bfin/parallel2.d: Likewise. * gas/bfin/shift2.d: Likewise; also match new tests.
2006-03-162006-03-16 Paul Brook <paul@codesourcery.com>Paul Brook7-7/+44
gas/ * config/tc-arm.c (insns): Add "svc". gas/testsuite/ * gas/arm/svc.d: New test. * gas/arm/svc.s: New test. * gas/arm/inst.d: Accept svc mnemonic. * gas/arm/thumb.d: Ditto. * gas/arm/wince_inst.d: Ditto. opcodes/ * arm-dis.c (arm_opcodes): Rename swi to svc. (thumb_opcodes): Ditto.
2006-03-092006-03-09 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+32
bfd/ * cpu-arm.c (bfd_is_arm_mapping_symbol_name): Recognise additional mapping symbols. gas/testsuite/ * gas/arm/nomapping.d: New test. * gas/arm/nomapping.s: New test.
2006-03-07gas/testsuite/H.J. Lu12-4/+301
2006-03-07 H.J. Lu <hongjiu.lu@intel.com> PR binutils/2428 * gas/i386/i386.exp: Add rep, rep-suffix, x86-64-rep and x86-64-rep-suffix. * gas/i386/naked.d: Replace repz with rep. * gas/i386/x86_64.d: Likewise. * gas/i386/rep-suffix.d: New file. * gas/i386/rep-suffix.s: Likewise. * gas/i386/rep.d: Likewise. * gas/i386/rep.s: Likewise. * gas/i386/x86-64-rep-suffix.d: Likewise. * gas/i386/x86-64-rep-suffix.s: Likewise. * gas/i386/x86-64-rep.d: Likewise. * gas/i386/x86-64-rep.s: Likewise. opcodes/ 2006-03-07 H.J. Lu <hongjiu.lu@intel.com> PR binutils/2428 * i386-dis.c (REP_Fixup): New function. (AL): Remove duplicate. (Xbr): New. (Xvr): Likewise. (Ybr): Likewise. (Yvr): Likewise. (indirDXr): Likewise. (ALr): Likewise. (eAXr): Likewise. (dis386): Updated entries of ins, outs, movs, lods and stos.
2006-03-07bfd/Richard Sandiford6-14/+70
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo. (bfd_elf32_bigarm_symbian_vec): Likewise. (bfd_elf32_bigarm_vxworks_vec): Likewise. (bfd_elf32_littlearm_vec): Likewise. (bfd_elf32_littlearm_symbian_vec): Likewise. (bfd_elf32_littlearm_vxworks_vec): Likewise. * configure: Regenerate. * elf32-arm.c: Include libiberty.h and elf-vxworks.h. (RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros. (elf32_arm_vxworks_bed): Add forward declaration. (elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12. (elf32_arm_vxworks_exec_plt0_entry): New table. (elf32_arm_vxworks_exec_plt_entry): Likewise. (elf32_arm_vxworks_shared_plt_entry): Likewise. (elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields. (reloc_section_p): New function. (create_got_section): Use RELOC_SECTION. (elf32_arm_create_dynamic_sections): Likewise. Call elf_vxworks_create_dynamic_sections for VxWorks targets. Choose between the two possible values of plt_header_size and plt_entry_size. (elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2. (elf32_arm_abs12_reloc): New function. (elf32_arm_final_link_relocate): Call it. Allow the creation of dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p, RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the r_addend fields of relocs. On rela targets, skip any code that adjusts in-place addends. When using _bfd_link_final_relocate to perform a final relocation, pass rel->r_addend as the addend argument. (elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks object, ignore flags that are not standard on VxWorks. (elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p. (elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE. (allocate_dynrelocs): Use RELOC_SIZE. Account for the size of .rela.plt.unloaded relocs on VxWorks targets. (elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for .rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags instead of DT_REL* tags on RELA targets. (elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks. (elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ like DT_RELSZ. Handle the VxWorks form of initial PLT entry. Correct the .rela.plt.unreloaded symbol indexes. (elf32_arm_output_symbol_hook): Call the VxWorks version of this hook on VxWorks targets. (elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true. Minor formatting tweak. (elf32_arm_vxworks_final_write_processing): New function. (elf_backend_add_symbol_hook): Override for VxWorks and reset for Symbian. (elf_backend_final_write_processing): Likewise. (elf_backend_emit_relocs): Likewise. (elf_backend_want_plt_sym): Likewise. (ELF_MAXPAGESIZE): Likewise. (elf_backend_may_use_rel_p): Minor formatting tweak. (elf_backend_may_use_rela_p): Likewise. (elf_backend_default_use_rela_p): Likewise. (elf_backend_rela_normal): Likewise. * Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h. gas/ * config/tc-arm.c (md_apply_fix): Install a value of zero into a BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA R_ARM_ABS12 reloc. (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets. gas/testsuite/ * gas/arm/abs12.s, gas/arm/abs12.d: New test. * gas/arm/pic.d: Skip for *-*-vxworks*... * gas/arm/pic_vxworks.d: ...use this version instead. * gas/arm/unwind_vxworks.d: Fix expected output. ld/ * emulparams/armelf_vxworks.sh: Include vxworks.sh. (MAXPAGESIZE): Define. * emulparams/vxworks.sh: Undefine. * Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em. * Makefile.in: Regenerate. ld/testsuite/ * ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd, * ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd, * ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s, * ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd, * ld-arm/vxworks2-static.sd: New tests. * ld-arm/arm-elf.exp: Run them.
2006-03-06 bfd:Nathan Sidwell3-2/+7
* archures.c (bfd_mach_mcf_isa_a_nodiv, bfd_mach_mcf_isa_b_nousp): New. Adjust other variants. (bfd_default_scan): Update. * bfd-in2.h: Rebuilt. * cpu-m68k.c: Adjust. (bfd_m68k_compatible): New. Use it for architectures. * elf32-m68k.c (elf32_m68k_object_p): Adjust. (elf32_m68k_merge_private_bfd_data): Adjust. Correct isa-a/b mismatch. (elf32_m68k_print_private_bfd_data): Adjust. * ieee.c (ieee_write_processor): Adjust. binutils: * readelf.c (get_machine_flags): Adjust. gas: * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k and cf. (m68k_ip): <case 'J'> Check we have some control regs. (md_parse_option): Allow raw arch switch. (m68k_init_arch): Better detection of arch/cpu mismatch. Detect whether 68881 or cfloat was meant by -mfloat. (md_show_usage): Adjust extension display. (m68k_elf_final_processing): Adjust. gas/testsuite: * gas/m68k/arch-cpu-1.s: Tweak. * gas/m68k/arch-cpu-1.d: Tweak. include/elf: * m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_ISA_C): Adjust. (EF_M68K_ISA_A_NODIV, EF_M68K_ISA_B_NOUSP): New. (EF_M68K_HW_DIV, EF_M68K_USP): Remove. (EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_FLOAT): Adjust. (EF_M68K_EMAC_B): New. ld/testsuite: * ld-m68k: New tests.
2006-02-28gas/Jan Beulich3-2/+7
2006-02-28 Jan Beulich <jbeulich@novell.com> * macro.c (get_any_string): Don't insert quotes for <>-quoted input. gas/testsuite/ 2006-02-28 Jan Beulich <jbeulich@novell.com> * gas/all/altmacro.s: Adjust. * gas/all/altmac2.s: Adjust.
2006-02-28gas/Jan Beulich4-0/+32
2006-02-28 Jan Beulich <jbeulich@novell.com> PR/1070 * macro.c (getstring): Don't treat parentheses special anymore. (get_any_string): Don't consider '(' and ')' as quoting anymore. Special-case '(', ')', '[', and ']' when dealing with non-quoting characters. gas/testsuite/ 2006-02-28 Jan Beulich <jbeulich@novell.com> * gas/macros/paren[sd]: New. * gas/macros/macros.exp: Run new test.
2006-02-27gas/H.J. Lu6-0/+297
2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (output_insn): Support Intel Merom New Instructions. * gas/config/tc-i386.h (CpuMNI): New. (CpuUnknownFlags): Add CpuMNI. gas/testsuite/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add merom and x86-64-merom. * gas/i386/merom.d: New file. * gas/i386/merom.s: Likewise. * gas/i386/x86-64-merom.d: Likewise. * gas/i386/x86-64-merom.s: Likewise. include/opcode/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Support Intel Merom New Instructions. opcodes/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by Intel Merom New Instructions. (THREE_BYTE_0): Likewise. (THREE_BYTE_1): Likewise. (three_byte_table): Likewise. (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use THREE_BYTE_1 for entry 0x3a. (twobyte_has_modrm): Updated. (twobyte_uses_SSE_prefix): Likewise. (print_insn): Handle 3-byte opcodes used by Intel Merom New Instructions.
2006-02-26missing from 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> commitNathan Sidwell2-0/+15
2006-02-252006-02-24 David S. Miller <davem@sunset.davemloft.net>David S. Miller12-2/+90
* gas/sparc/rdhpr.s: New test. * gas/sparc/rdhpr.d: New test. * gas/sparc/wrhpr.s: New test. * gas/sparc/wrhpr.d: New test. * gas/sparc/window.s: New test. * gas/sparc/window.d: New test. * gas/sparc/rdpr.s: Add case for reading %gl register. * gas/sparc/rdpr.d: Likewise. * gas/sparc/wrpr.s: Add case for writing %gl register. * gas/sparc/wrpr.d: Likewise. * gas/sparc/sparc.exp: Update for new tests.
2006-02-242006-02-24 Paul Brook <paul@codesourcery.com>Paul Brook7-10/+190
gas/ * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7, arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables. (struct asm_barrier_opt): Define. (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables. (parse_psr): Accept V7M psr names. (parse_barrier): New function. (enum operand_parse_code): Add OP_oBARRIER. (parse_operands): Implement OP_oBARRIER. (do_barrier): New function. (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions. (do_t_cpsi): Add V7M restrictions. (do_t_mrs, do_t_msr): Validate V7M variants. (md_assemble): Check for NULL variants. (v7m_psrs, barrier_opt_names): New tables. (insns): Add V7 instructions. Mark V6 instructions absent from V7M. (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh. (arm_cpu_option_table): Add Cortex-M3, R4 and A8. (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m. (struct cpu_arch_ver_table): Define. (cpu_arch_ver): New. (aeabi_set_public_attributes): Use cpu_arch_ver. Set Tag_CPU_arch_profile. * doc/c-arm.texi: Document new cpu and arch options. gas/testsuite/ * gas/arm/thumb32.d: Fix expected msr and mrs output. * gas/arm/arch7.d: New test. * gas/arm/arch7.s: New test. * gas/arm/arch7m-bad.l: New test. * gas/arm/arch7m-bad.d: New test. * gas/arm/arch7m-bad.s: New test. include/opcode/ * arm.h: Add V7 feature bits. opcodes/ * arm-dis.c (arm_opcodes): Add V7 instructions. (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. (print_arm_address): New function. (print_insn_arm): Use it. Add 'P' and 'U' cases. (psr_name): New function. (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
generated by cgit v1.1 at 2025-08-14 11:51:43 +0000