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2020-07-06x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich4-36/+36
Just like their AVX counterparts do for VEX.L. At this occasion also make EVEX.W have the same effect as VEX.W on the printing of VPINSR{B,W}'s operands, bringing them also in sync with VPEXTR{B,W}.
2020-07-06x86: replace EXqScalarS by EXqVexScalarSJan Beulich6-4/+12
There's only a single user, that that one can do fine with the alternative, as the "Vex" aspect of the other operand kind is meaningful only on 3-operand insns. While doing this I noticed that I didn't need to do the same adjustment in the EVEX tables, and voilà - there was a bug, which gets fixed at the same time (see the testsuite changes).
2020-07-03Re: Change readelf's display of symbol namesAlan Modra1-1/+1
Fixes some fallout from git commit 0942c7ab94e5. PR 26028 gas/ * testsuite/gas/ia64/unwind-ilp32.d: Add -T to readelf options. gold/ * testsuite/Makefile.am (file_in_many_sections.stdout): Add -W to readelf options. * testsuite/Makefile.in: Regenerate. ld/ * testsuite/ld-arm/arm-elf.exp (vxworks1): Pass --wide to readelf when dumping relocs. * testsuite/ld-i386/i386.exp (vxworks1): Likewise. * testsuite/ld-sh/sh-vxworks.exp (vxworks1): Likewise. * testsuite/ld-sparc/sparc.exp (vxworks1): Likewise. * testsuite/ld-arm/vxworks1.rd: Adjust to suit. * testsuite/ld-i386/vxworks1.rd: Adjust. * testsuite/ld-sh/vxworks1.rd: Adjust. * testsuite/ld-sparc/vxworks1.rd: Adjust.
2020-07-02Skip fill-1 gas test for MeP targets.Nick Clifton1-1/+3
* testsuite/gas/all/fill-1.d: Skip for MeP targets.
2020-07-02aarch64: Fix segfault on unicode symbolsAlex Coplan2-0/+10
This patch fixes a segfault which occurs when the AArch64 backend parses a symbol operand that begins with a register name and ends with a unicode byte (byte value > 127). For example, the following input causes the crash: x0é: udf x0é gas/ChangeLog: 2020-07-02 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (reg_name_p): Fix cast so that we don't segfault on negative chars. * testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test. * testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
2020-07-02Change readelf's display of symbol names (when not in --wide mode) so that ↵Nick Clifton6-6/+6
if they are going to be truncated then "[...]" is displayed at the end. Add a comment line option to disable this enhancement and restore the old behaviour. PR 26028 binutils* readelf.c (print_symbol): Handle truncation of symbol names. (options): Add -T/--silent-truncation option. (parse_args): Handle the option. (print_dynamic_symbol): Correct calculation of width available to display symbol name. * doc/binutils.texi: Document the -T option to readelf. * NEWS: Mention the new feature. gas * testsuite/gas/ia64/group-2.d: Add -T option to readelf command line. * testsuite/gas/ia64/unwind.d: Likewise. * testsuite/gas/mmix/bspec-1.d: Likewise. * testsuite/gas/mmix/bspec-2.d: Likewise. * testsuite/gas/mmix/comment-1.d: Likewise. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise. ld * testsuite/ld-powerpc/powerpc.exp: Add -T option to readelf command line when running some tests. * testsuite/ld-arm/arm-elf.exp: Likewise. * testsuite/ld-mips-elf/mips-elf.exp: Likewise. * testsuite/ld-mmix/local1.d: Likewise. * testsuite/ld-mmix/local3.d: Likewise. * testsuite/ld-mmix/local5.d: Likewise. * testsuite/ld-mmix/local7.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Likewise.
2020-07-01gas eqv-dot test failsAlan Modra1-1/+4
* testsuite/gas/all/eqv-dot.d: xfail targets that set linkrelax in data sections, and mep.
2020-06-30Remove x86 NaCl target supportH.J. Lu8-15/+6
NaCl has been deprecated: https://developer.chrome.com/native-client/migration and NaCl will completely disappear in 2021: https://lists.llvm.org/pipermail/llvm-dev/2020-April/141107.html Remove x86 NaCl target support from bfd, binutils, gas and ld. bfd/ * archures.c (bfd_mach_i386_nacl): Removed. (bfd_mach_i386_i386_nacl): Likewise. (bfd_mach_x86_64_nacl): Likewise. (bfd_mach_x64_32_nacl): Likewise. * config.bfd: Remove *-*-nacl* targets. * configure.ac: Remove x86 NaCl target vectors. * cpu-i386.c (bfd_arch_i386_onebyte_nop_fill): Removed. (bfd_x64_32_nacl_arch): Likewise. (bfd_x86_64_nacl_arch): Likewise. (bfd_i386_nacl_arch): Likewise. (bfd_x64_32_arch_intel_syntax): Updated. * elf32-i386.c: Don't include "elf-nacl.h". (elf_i386_nacl_plt): Removed. (elf_i386_nacl_plt0_entry): Likewise. (elf_i386_nacl_plt_entry): Likewise. (elf_i386_nacl_pic_plt0_entry): Likewise. (elf_i386_nacl_pic_plt_entry): Likewise. (elf_i386_nacl_eh_frame_plt): Likewise. (elf_i386_nacl_plt): Likewise. (elf32_i386_nacl_elf_object_p): Likewise. (elf_i386_get_synthetic_symtab): Updated. (elf_i386_link_setup_gnu_properties): Likewise. * elf64-x86-64.c: Don't include "elf-nacl.h". (elf_x86_64_nacl_plt): Removed. (elf64_x86_64_nacl_elf_object_p): Likewise. (elf_x86_64_nacl_plt0_entry): Likewise. (elf_x86_64_nacl_plt_entry): Likewise. (elf_x86_64_nacl_eh_frame_plt): Likewise. (elf_x86_64_nacl_plt): Likewise. (elf32_x86_64_nacl_elf_object_p): Likewise. (elf_x86_64_get_synthetic_symtab): Updated. (elf_x86_64_link_setup_gnu_properties): Likewise. * elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Likewise. * targets.c: Remove x86 NaCl target vectors. * bfd-in2.h: Regenerated. * configure: Likewise. binutils/ * NEWS: Mention x86 NaCl target support removal. * dwarf.c (init_dwarf_regnames_by_bfd_arch_and_mach): Remove x86 NaCl target support. * testsuite/binutils-all/elfedit-1.d: Likewise. * testsuite/binutils-all/i386/i386.exp: Likewise. * testsuite/binutils-all/x86-64/objects.exp: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/x86-64.exp: Likewise. gas/ * NEWS: Mention x86 NaCl target support removal. * config/tc-i386.c: Remove x86 NaCl target support. * config/tc-i386.h: Likewise. * configure.tgt: Likewise. * testsuite/gas/i386/i386.exp: Likewise. * testsuite/gas/i386/iamcu-1.d: Likewise. * testsuite/gas/i386/iamcu-2.d: Likewise. * testsuite/gas/i386/iamcu-3.d: Likewise. * testsuite/gas/i386/iamcu-4.d: Likewise. * testsuite/gas/i386/iamcu-5.d: Likewise. * testsuite/gas/i386/k1om.d: Likewise. * testsuite/gas/i386/l1om.d: Likewise. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_nacl.c, eelf32_x86_64_nacl.c, eelf_x86_64_nacl.c. Remove x86 NaCl dep files. * NEWS: Mention x86 NaCl target support removal. * configure.tgt: Remove x86 NaCl target support. * testsuite/ld-elf/binutils.exp: Likewise. * testsuite/ld-elf/elf.exp: Likewise. * testsuite/ld-elfvers/vers.exp: Likewise. * testsuite/ld-i386/align-branch-1.d: Likewise. * testsuite/ld-i386/export-class.exp: Likewise. * testsuite/ld-i386/i386.exp: Likewise. * testsuite/ld-i386/load1.d: Likewise. * testsuite/ld-i386/pie1.d: Likewise. * testsuite/ld-i386/pr12570a.d: Likewise. * testsuite/ld-i386/pr12570b.d: Likewise. * testsuite/ld-i386/pr19636-1d.d: Likewise. * testsuite/ld-i386/pr19636-1l.d: Likewise. * testsuite/ld-i386/pr19636-2c.d: Likewise. * testsuite/ld-i386/pr19636-2d.d: Likewise. * testsuite/ld-i386/pr19636-2e.d: Likewise. * testsuite/ld-i386/pr20244-1a.d: Likewise. * testsuite/ld-i386/pr20244-1b.d: Likewise. * testsuite/ld-i386/pr20244-2a.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Likewise. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-i386/pr20244-4a.d: Likewise. * testsuite/ld-i386/pr20244-4b.d: Likewise. * testsuite/ld-i386/pr21884.d: Likewise. * testsuite/ld-ifunc/binutils.exp: Likewise. * testsuite/ld-ifunc/ifunc-10-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-10-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-11-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-11-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-12-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-12-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-13-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-13-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14c-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14c-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14d-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14d-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14e-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14e-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14f-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14f-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-15-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-15-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-16-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-16-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-16-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-16-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-17a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-17a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-17b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-17b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-19a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-19a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-19b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-19b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-20-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-20-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-21-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-6a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-6a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-6b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-6b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-7a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-7a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-7b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-7b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-8-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-8-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-9-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-9-x86-64.d: Likewise. * testsuite/ld-ifunc/pr17154-i386-now.d: Likewise. * testsuite/ld-ifunc/pr17154-i386.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64-now.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64.d: Likewise. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/ld-x86-64/align-branch-1.d: Likewise. * testsuite/ld-x86-64/dwarfreloc.exp: Likewise. * testsuite/ld-x86-64/line.exp: Likewise. * testsuite/ld-x86-64/load1a.d: Likewise. * testsuite/ld-x86-64/load1b.d: Likewise. * testsuite/ld-x86-64/load1c.d: Likewise. * testsuite/ld-x86-64/load1d.d: Likewise. * testsuite/ld-x86-64/pie3.d: Likewise. * testsuite/ld-x86-64/pr18160.d: Likewise. * testsuite/ld-x86-64/pr19013-x32.d: Likewise. * testsuite/ld-x86-64/pr19013.d: Likewise. * testsuite/ld-x86-64/pr19636-2d.d: Likewise. * testsuite/ld-x86-64/pr19636-2l.d: Likewise. * testsuite/ld-x86-64/pr20253-1b.d: Likewise. * testsuite/ld-x86-64/pr20253-1d.d: Likewise. * testsuite/ld-x86-64/pr20253-1f.d: Likewise. * testsuite/ld-x86-64/pr20253-1h.d: Likewise. * testsuite/ld-x86-64/pr20253-1j.d: Likewise. * testsuite/ld-x86-64/pr20253-1l.d: Likewise. * testsuite/ld-x86-64/pr21884.d: Likewise. * testsuite/ld-x86-64/pr22393-3a.rd: Likewise. * testsuite/ld-x86-64/pr22393-3b.rd: Likewise. * testsuite/ld-x86-64/tlsgd10.dd: Likewise. * testsuite/ld-x86-64/tlsgd5.dd: Likewise. * testsuite/ld-x86-64/tlsgd8.dd: Likewise. * testsuite/ld-x86-64/x86-64.exp: Likewise. * emulparams/elf32_x86_64_nacl.sh: Removed. * emulparams/elf_i386_nacl.sh: Likewise. * emulparams/elf_x86_64_nacl.sh: Likewise. * testsuite/ld-i386/emit-relocs-nacl.rd: Likewise. * testsuite/ld-i386/load1-nacl.d: Likewise. * testsuite/ld-i386/pie1-nacl.d: Likewise. * testsuite/ld-i386/plt-nacl.pd: Likewise. * testsuite/ld-i386/plt-pic-nacl.pd: Likewise. * testsuite/ld-i386/pr17709-nacl.rd: Likewise. * testsuite/ld-i386/pr19636-1d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2c-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2e-nacl.d: Likewise. * testsuite/ld-i386/pr19827-nacl.rd: Likewise. * testsuite/ld-i386/pr21884-nacl.d: Likewise. * testsuite/ld-i386/pr21884-nacl.t: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic2-nacl.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/load1a-nacl.d: Likewise. * testsuite/ld-x86-64/load1b-nacl.d: Likewise. * testsuite/ld-x86-64/load1c-nacl.d: Likewise. * testsuite/ld-x86-64/load1d-nacl.d: Likewise. * testsuite/ld-x86-64/pie3-nacl.d: Likewise. * testsuite/ld-x86-64/plt-nacl.pd: Likewise. * testsuite/ld-x86-64/pr17709-nacl.rd: Likewise. * testsuite/ld-x86-64/pr19013-nacl.d: Likewise. * testsuite/ld-x86-64/pr19636-2d-nacl.d: Likewise. * testsuite/ld-x86-64/pr19827-nacl.rd: Likewise. * testsuite/ld-x86-64/pr21884-nacl.d: Likewise. * testsuite/ld-x86-64/pr21884-nacl.t: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.pd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise. * Makefile.in: Regenerated. * po/BLD-POTFILES.in: Likewise.
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu15-159/+150
The unprivileged CSR should be controlled by other specific specs rather than the privileged spec. For example, the debug CSR should be controlled by the debug spec, and the float CSR should be controlled by the float spec. User may use assembler options to choose what the debug and other specs they want, or may encode the versions of specs into the architecture string directly. Since we haven't decided which one is better, we set the defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec versions for them. However, these PRIV_SPEC_CLASS_NONE will be changed to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future. gas/ * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the checking into riscv_csr_address. (riscv_csr_version_check): Likewise. (riscv_csr_address): New function. Return the suitable CSR address after checking the ISA dependency and versions. Issue warnings if we find any conflict and -mcsr-check is set. CSR_CLASS_F and CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the priv spec versions for them. (reg_csr_lookup_internal): Call riscv_csr_address to find the suitable CSR address. * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the priv spec warnings here. These warnings are added by accident. Remove them and only focus on the ISA dependency warnings. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since dscratch0 and dscratch1 are regarded as the unprivileged CSR rather than the privileged ones. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. include/ * opcode/riscv-opc.h: Support the unprivileged CSR. The versions of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now. * opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG. opcodes/ * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the unprivileged CSR can also be initialized.
2020-06-29gas/testsuite: test-case for PR25331 (mmix reloc fixup bug)Hans-Peter Nilsson2-0/+481
The bug manifested "only" for a 64-bit host: pr25331.c: Assembler messages: pr25331.c:430: Error: internal error: fixup not contained within frag failed with: <pr25331.c: Assembler messages: pr25331.c:430: Error: internal error: fixup not contained within frag>, no expected output FAIL: gas/mmix/pr25331 gas: PR gas/25331 * testsuite/gas/mmix/pr25331.d, testsuite/gas/mmix/pr25331.s: New test.
2020-06-26x86: fix processing of -M disassembler optionJan Beulich2-0/+61
Multiple -M options can be specified in any order. Therefore stright assignment to fields affected needs to be avoided, such that earlier options' effects won't be discarded. This was in particular a problem for -Msuffix followed by certain of the other sub-options. While updating documentation, take the liberty and also drop the redundant mentioning of being able to comma-separate multiple options.
2020-06-25Stop the assembler from generating R_ARM_THM_JMP11 relocations as these are ↵Nick Clifton1-8/+4
not supported by the kernel. PR 26141 * config/tc-arm.c (arm_force_relocation): Force resolution of BFD_RELOC_THUMB_PCREL_BRANCH12 relocations. * testsuite/gas/arm/plt-1.d: Adjust expected disassembly.
2020-06-25x86: operand sizing prefixes can disambiguate insnsJan Beulich11-447/+1149
Use of an explicit data size or REX.W prefix is sufficient indication of the intended operation when operand size can't be derived from suffix or register operands. Avoid the ambiguity warning and make in particular immediate handling (sizing) cope with explicitly specified prefixes. Extending/reusing the noreg16 test made me notice a few cases of unintentional 32-bit addressing, which gets corrected at the same time.
2020-06-25x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S,D} and PTWRITEJan Beulich16-225/+225
SYSRET can't use the same macro as IRET, since there's no 16-bit operand size form of it. Re-use LQ for it instead. Doing so made obvious that outside of 64-bit mode {,V}CVTSI2S{S,D} and PTWRITE should have an 'l' suffix printed only in suffix-always mode.
2020-06-25x86-64: REX prefix is invalid with VEX etcJan Beulich4-12/+6
Just like for the data size prefix (see commit 7a8655d2bbdc ["x86: don't abort() upon DATA16 prefix on (E)VEX encoded insn"]), any form of REX prefix is invalid with VEX/XOP/EVEX.
2020-06-25x86-64: honor REX prefixes for SSE2AVXJan Beulich2-1/+65
Legacy encoded insns do so, and their automatic conversion to AVX ones ought to produce functionally identical code. Therefore explicit REX prefixes cannot simply be ignored. This is in particular relevant because at least PCMPESTR{I,M}'s 64-bit forms couldn't be expressed in older gas by other than using a REX64 prefix.
2020-06-25x86: also refuse data size prefix on SIMD insnsJan Beulich6-11/+17
The data size prefix alters the meaning of legacy encoded SIMD insns, and hence shouldn't be accepted there. Use of it also leads to inconsistencies in SSE2AVX mode. Don't match insns with data size prefix against SSE2AVX templates.
2020-06-23RISC-V: Generate ELF priv attributes if priv instruction are explicited used.Nelson Chu7-0/+61
We should generate the ELF priv attributes only if, 1. The priv attributes are already set in the assembly file. 2. The CSR are explicited used. 3. The privileged instruction are explicited used. * There are four privileged instruction defined in the v1.11 priv spec: `mret`, `sret`, `wfi` and `sfence.vma`. * `sfence.vm` is dropped in the v1.10 priv spec. * `uret` is actually a N-ext instruction. So it is better to regard it as an user instruction rather than the priv instruction. * `hret` is used to return from traps in H-mode. H-mode is removed since the v1.10 priv spec, but probably be added in the new hypervisor spec. Therefore, `hret` should be controlled by the hypervisor spec rather than priv spec in the future. * `dret` is a debug instruction. We should record the debug spec versions once it is explicited used in the future. gas/ * config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to explicit_priv_attr. It used to indicate CSR or priv instructions are explictly used. (riscv_is_priv_insn): Return True if it is a privileged instruction. (riscv_ip): Call riscv_is_priv_insn to check whether the instruction is privileged or not. If it is, then set explicit_priv_attr to TRUE. (riscv_write_out_attrs): Clarification of when to generate the elf priv spec attributes. * testsuite/gas/riscv/attribute-11.s: Add comments. * testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol `priv_insn_<n>` to decide which priv instruction is expected to used. (<n> is a to g.) * testsuite/gas/riscv/attribute-14a.d: Likewise. * testsuite/gas/riscv/attribute-14b.d: Likewise. * testsuite/gas/riscv/attribute-14c.d: Likewise. * testsuite/gas/riscv/attribute-14d.d: Likewise. * testsuite/gas/riscv/attribute-14e.d: Likewise.
2020-06-18x86: also test alternative VMGEXIT encodingJan Beulich2-1/+3
gas/ * testsuite/gas/i386/arch-13.s: Add alternative VMGEXIT case. * testsuite/gas/i386/arch-13.d: Extend -march=. Adjust expectations. opcodes/ * i386-dis.c (prefix_table): Revert the last vmgexit change.
2020-06-16x86: drop SSE4a from SSE check againJan Beulich4-10/+5
Upon re-consideration in commit 569d50f1c611 ("x86: further refine SSE check (SSE4a, SHA, GFNI)") I went too far: Mixing of SSE and AVX insns doesn't suffer as bad a penalty on AMD CPUs as on Intel ones. SSE4a being an AMD-only extension, it shouldn't be part of the ISA extensions set for which the diagnostic may get issued. Undo that part.
2020-06-15xtensa: allow runtime ABI selectionMax Filippov3-0/+15
2020-06-15 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED) (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New global variable. (xtensa_abi_choice): New function. (elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of XSHAL_ABI to select PLT code. gas/ * config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (option_abi_windowed, option_abi_call0): New enum constants. (md_longopts): Add entries for --abi-windowed and --abi-call0. (md_parse_option): Add handlers for --abi-windowed and --abi-call0. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. * doc/as.texi (Target Xtensa options): Add --abi-windowed and --abi-call0 to the list of options. * doc/c-xtensa.texi: Add description for options --abi-windowed and --abi-call0. * testsuite/gas/xtensa/abi-call0.d: New test definition. * testsuite/gas/xtensa/abi-windowed.d: New test definition. * testsuite/gas/xtensa/abi.s: New test source. include/ * elf/xtensa.h (xtensa_abi_choice): New declaration. ld/ * emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition. (XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test ABI tag consistency. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. (PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED, OPTION_ABI_CALL0 and declare elf32xtensa_abi. (PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and --abi-call0. (PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and --abi-call0. (PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and --abi-call0. * ld.texi: Add description for options --abi-windowed and --abi-call0.
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu3-3/+3
The correct mnemonic is xsusldtrk, not xsuspldtrk. gas/ PR gas/26115 * testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with xsusldtrk. * testsuite/gas/i386/tsxldtrk.s: Likewise. * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise. * testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise. opcodes/ PR gas/26115 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu3-298/+0
There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is 0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable, but may also cause risk of compatibility. Binutils already support the -mpriv-spec options and ELF priv attributes, which can used to choose what privileged spec you want, and then give a correponding CSR name and address to use. But Gdb and other tools don't have the simialr mechanism for now. However, there are two things can be confirmed, 1. If we don't have a way to control the priv specs, then the changes, like MISA, will cause risk and hard to maintain. 2. We get the guarantee that the CSR address won't be reused in the future specs, even if it is dropped. I'm not sure if Gdb needs to care about the priv spec versions, it is still discussing. But drop the priv spec v1.9, and make sure that we won't reuse the CSR address is a useful solution for now. Also, we might drop the v1.9.1 in a year or two. After that, specs above v1.10 should be compatible anyway. gas/ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. include/ * opcode/riscv-opc.h: Update the defined versions of CSR from PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9. * opcode/riscv.h (enum riscv_priv_spec_class): Remove PRIV_SPEC_CLASS_1P9. opcodes/ * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
2020-06-09x86: add missing 64-bit tests for "don't ignore mandatory pseudo prefixes"Jan Beulich2-0/+7
Commit da4977e00b73 added the 32-bit test files, but failed to add the 64-bit ones.
2020-06-09x86: consistently print prefixes explicitly which are invalid with VEX etcJan Beulich2-1/+9
All of data size, rep, lock, and rex prefixes are invalid with VEX- and alike encoded insns. Make sure they get printed explicitly in all cases, to signal the anomaly. With this, do away with "rex_ignored" - if there is a rex prefix, we want to print it anyway for VEX etc (and there's nothing "ignored" about it in the first place - such an instruction will raise #UD).
2020-06-09x86: correct decoding of packed-FP-only AVX encodingsJan Beulich2-0/+74
Various AVX insns utilizing the X macro fail to reject F3/F2 embedded prefix encodings. As the PREFIX_OPCODE attribute wasn't used by any non-legacy-encoded insns so far, re-use it to achieve the intended effect.
2020-06-09x86-64: adjust far indirect branch handlingJan Beulich6-0/+146
An unwanted side effect of 5990e377e5a3 ("x86-64: Intel64 adjustments for insns dealing with far pointers") was that with -mintel64 LCALL and LJMP would now default to 64-bit operand size. Since 64-bit far branches aren't portable, the default operand size should still be 32-bit. However, since the 64-bit variant is permitted, an ambiguous operand warning should be issued. As to the actual code change, please note that the conditional surrounding the switch() that gets adjusted covers several cases which are of no interest to or benign in 64-bit mode, hence the new conditional added can be quite a bit less involved.
2020-06-09x86: don't ignore mandatory pseudo prefixesJan Beulich4-3/+27
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not be randomly ignored. Fix this for insns without operands as well as for insns referencing the high 16 [XYZ]MM registers. To achieve the former, re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and moving its only operand check to check_VecOperands(). This involves fixing a testcase relying on {vex2} to get ignored.
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan2-0/+29
gas/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (insns): Add dfb. * testsuite/gas/arm/dfb.d: New test. * testsuite/gas/arm/dfb.s: Input for test. opcodes/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * arm-dis.c (arm_opcodes): Add dfb. (thumb32_opcodes): Add dfb.
2020-06-08Fix a gas testsuite failure for PE based targets which cannot assemble the ↵Nick Clifton1-0/+3
cfi-i386-2 test. * testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets.
2020-06-08x86: restrict %tr<N> visibilityJan Beulich3-0/+7
First of all, these registers have never been available on any 64-bit CPU, and hence should not be recognized in 64-bit mode. But even before that they had already disappeared - also don't recognize them when 586 or 686 architectures were explicitly set.
2020-06-08ix86: enable 2nd CFI testJan Beulich2-7/+8
While putting together the previous patch I noticed that this test, forever since its introduction, was dead. Update it so it will pass, and enable it.
2020-06-08x86: also allow %st(N) in CFI directivesJan Beulich1-0/+1
In 0e0eea782025 ("x86: x87-related adjustments") I screwed up CFI directives with FPU support disabled, by moving the conditional there across a check of "allow_pseudo_reg". Add the missing check.
2020-06-08x86: restrict use of register aliasesJan Beulich5-0/+41
Register aliases (created e.g. via .set) check their target register at the time of creation of the alias. While this makes sense, it's not enough: The underlying register must also be "visible" at the time of use. Wrong use of such aliases would lead to internal errors in e.g. add_prefix() or build_modrm_byte(). Split the checking part of parse_real_register() into a new helper function and use it also from the latter part of parse_register() (at the same time replacing a minor open coded part of it). Since parse_register() returning NULL already has a meaning, a fake new "bad register" indicator gets added, which all callers need to check for.
2020-06-05RISC-V: Don't generate the ELF privilege attributes when no CSR are used.Nelson Chu14-30/+24
gas/ * config/tc-riscv.c (explicit_csr): New static boolean. Used to indicate CSR are explictly used. (riscv_ip): Set explicit_csr to TRUE if any CSR is used. (riscv_write_out_attrs): If we already have set elf priv attributes, then generate them. Otherwise, don't generate them when no CSR are used. * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-11.s: New testcase. * testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is used, so we should output the ELF priv attributes. * testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is used, so output the priv attributes according to the -mpriv-spec. * testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't used, so ignore the -mpriv-spec setting. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
2020-06-04tcl global directive outside proc body does nothing (gas)Alan Modra6-7/+0
* testsuite/config/default.exp: Remove global directive outside proc body. * testsuite/gas/mep/complex-relocs.exp: Likewise. * testsuite/gas/microblaze/relax_size.exp: Likewise. * testsuite/gas/microblaze/reloc_sym.exp: Likewise. * testsuite/gas/mt/relocs.exp: Likewise. * testsuite/gas/rx/rx.exp: Likewise.
2020-06-02gas: Fix checking for backwards .org with negative offsetAlex Coplan6-0/+14
This patch fixes internal errors in (at least) arm and aarch64 GAS when assembling code that attempts a negative .org. The bug appears to be a regression introduced in binutils-2.29 by commit 9875b36538d. * write.c (relax_segment): Fix handling of negative offset when relaxing an rs_org frag. * testsuite/gas/aarch64/org-neg.d: New test. * testsuite/gas/aarch64/org-neg.l: Error output for test. * testsuite/gas/aarch64/org-neg.s: Input for test. * testsuite/gas/arm/org-neg.d: New test. * testsuite/gas/arm/org-neg.l: Error output for test. * testsuite/gas/arm/org-neg.s: Input for test.
2020-05-28Fix all unexpected failures in gas testsuite for pdp11-aout.Stephen Casner4-3/+110
These failures were caused by the PDP11's mix of little-endian octets in shorts but shorts in big endian order for long or quad so regexps did not match. Also tests used addresses as values in .long which required BRD_RELOC_32 that was not implemented. * gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad * gas/testsuite/gas/all/gas.exp: Select alternate test scripts for pdp11, skip octa test completely. * gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s * gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order. * gas/testsuite/gas/all/cond-pdp11.l: Match different octet order. * bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of addreses in .long (used in testsuites) and .stab values.
2020-05-27Fix PR gas/26001 (pdp11-*-*)Stephen Casner3-0/+22
PR gas/26001 * gas/config/tc-pdp11.c (parse_reg): Distinguish register names from symbols that begin with a register name. * gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols. * gas/testsuite/gas/pdp11/pr26001.s: Likewise. * gas/testsuite/gas/pdp11/pr26001.d: Likewise.
2020-05-26gas: Adjust x86 tests for PECOFFH.J. Lu3-1/+5
* testsuite/gas/i386/align-branch-9.d: Updated for PECOFF. * testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF. * testsuite/gas/i386/inval-avx512f.l: Updated.
2020-05-26S/390: z13: Accept vector alignment hintsStefan Schulze Frielinghaus2-8/+16
Accept vector alignment hints on z13 although they are ignored there. The advantage is that any binary compiled for architecture level z13 may run on z14 or later and benefit from vector alignment hints. gas/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector load/store instruction variants with alignment hints. * testsuite/gas/s390/zarch-z13.s: Emit new vector load/store instruction variants with alignment hints. opcodes/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * s390-opc.txt: Relocate vector load/store instructions with additional alignment parameter and change architecture level constraint from z14 to z13.
2020-05-21Replace "if (x) free (x)" with "free (x)", gasAlan Modra1-4/+2
* atof-generic.c: Replace "if (x) free (x)" with "free (x)" throughout. * config/obj-elf.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-tic30.c: Likewise. * ecoff.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. * symbols.c: Likewise. * testsuite/gas/all/test-gen.c: Likewise.
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard ↵Nelson Chu35-333/+1377
extensions and CSR 1. Remove the -mriscv-isa-version and --with-riscv-isa-version options. We can still use -march to choose the version for each extensions, so there is no need to add these. 2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...]. Unlike the architecture string has specified by spec, ther is no need to do the same thing for options. 3. Spilt the patches to reduce the burdens of review. [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions to [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default. [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version. to [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version. [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version. 4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c. The behavior is same as comparing the choosen privilege spec. include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean. (enum riscv_isa_spec_class): New enum class. All supported ISA spec belong to one of the class (struct riscv_ext_version): New structure holds version information for the specific ISA. * opcode/riscv-opc.h (DECLARE_CSR): There are two version information, define_version and abort_version. The define_version means which privilege spec is started to define the CSR, and the abort_version means which privilege spec is started to abort the CSR. If the CSR is valid for the newest spec, then the abort_version should be PRIV_SPEC_CLASS_DRAFT. (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR. * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define the current supported privilege spec versions. (struct riscv_csr_extra): Add new fields to store more information about the CSR. We use these information to find the suitable CSR address when user choosing a specific privilege spec. binutils * dwarf.c: Updated since DECLARE_CSR is changed. opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store all information about the supported spec and the corresponding ISA versions. Currently, only Zicsr is supported to verify the correctness of Z sub extension settings. Others will be supported in the future patches. (struct isa_spec_t, isa_specs): List for all supported ISA spec classes and the corresponding strings. (riscv_get_isa_spec_class): New function. Get the corresponding ISA spec class by giving a ISA spec string. * riscv-opc.c (struct priv_spec_t): New structure. (struct priv_spec_t priv_specs): List for all supported privilege spec classes and the corresponding strings. (riscv_get_priv_spec_class): New function. Get the corresponding privilege spec class by giving a spec string. (riscv_get_priv_spec_name): New function. Get the corresponding privilege spec string by giving a CSR version class. * riscv-dis.c: Updated since DECLARE_CSR is changed. * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR according to the chosen version. Build a hash table riscv_csr_hash to store the valid CSR for the chosen pirv verison. Dump the direct CSR address rather than it's name if it is invalid. (parse_riscv_dis_option_without_args): New function. Parse the options without arguments. (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to parse the options without arguments first, and then handle the options with arguments. Add the new option -Mpriv-spec, which has argument. * riscv-dis.c (print_riscv_disassembler_options): Add description about the new OBJDUMP option. ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated priv attributes according to the -mpriv-spec option. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function get_default_version. It is used to find the default version for the specific extension. * elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters default_major_version and default_minor_version. Add new bfd_boolean parameter *use_default_version. Set it to TRUE if we need to call the callback rps->get_default_version to find the default version. (riscv_parse_std_ext): Call rps->get_default_version if we fail to find the default version in riscv_parsing_subset_version, and then call riscv_add_subset to add the subset into subset list. (riscv_parse_prefixed_ext): Likewise. (riscv_std_z_ext_strtab): Support Zicsr extensions. * elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the strings rather than characters. riscv_merge_arch_attr_info): The callback function get_default_version is only needed for assembler, so set it to NULL int the linker. * elfxx-riscv.c (riscv_estimate_digit): Remove the static. * elfxx-riscv.h: Updated. gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated. * config/tc-riscv.c (default_arch_with_ext, default_isa_spec): Static variables which are used to set the ISA extensions. You can use -march (or ELF build attributes) and -misa-spec to set them, respectively. (ext_version_hash): The hash table used to handle the extensions with versions. (init_ext_version_hash): Initialize the ext_version_hash according to riscv_ext_version_table. (riscv_get_default_ext_version): The callback function of riscv_parse_subset_t. According to the choosed ISA spec, get the default version for the specific extension. (riscv_set_arch): Set the callback function. (enum options, struct option md_longopts): Add new option -misa-spec. (md_parse_option): Do not call riscv_set_arch for -march. We will call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class to set default_isa_spec class. (riscv_after_parse_args): Call init_ext_version_hash to initialize the ext_version_hash, and then call riscv_set_arch to set the architecture with versions according to default_arch_with_ext. * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for x extensions. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we already set it's version to 2p1 by march, so no need to use the default 2p2 version. For m-ext, we do not set the version by -march and ELF arch attribute, so set the default 2p0 to it. For zicsr, it is not defined in ISA spec 2p2, so set 0p0 to it. * testsuite/gas/riscv/attribute-10.d: New testcase. The version of zicsr is 2p0 according to ISA spec 20191213. * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT) (DEFAULT_RISCV_ISA_SPEC): Default configure option settings. You can set them by configure options --with-arch and --with-isa-spec, respectively. (riscv_set_default_isa_spec): New function used to set the default ISA spec. (md_parse_option): Call riscv_set_default_isa_spec rather than call riscv_get_isa_spec_class directly. (riscv_after_parse_args): If the -isa-spec is not set, then we set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by calling riscv_set_default_isa_spec. * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since the --with-isa-spec may be set to different ISA spec. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * configure.ac: Add configure options, --with-arch and --with-isa-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (default_priv_spec): Static variable which is used to check if the CSR is valid for the chosen privilege spec. You can use -mpriv-spec to set it. (enum reg_class): We now get the CSR address from csr_extra_hash rather than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX. (riscv_init_csr_hashes): Only need to initialize one hash table csr_extra_hash. (riscv_csr_class_check): Change the return type to void. Don't check the ISA dependency if -mcsr-check isn't set. (riscv_csr_version_check): New function. Check and find the CSR address from csr_extra_hash, according to default_priv_spec. Report warning for the invalid CSR if -mcsr-check is set. (reg_csr_lookup_internal): Updated. (reg_lookup_internal): Likewise. (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed. (enum options, struct option md_longopts): Add new GAS option -mpriv-spec. (md_parse_option): Call riscv_set_default_priv_version to set default_priv_spec. (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default privilege spec to the newest one. (enum riscv_csr_class, struct riscv_csr_extra): Move them to include/opcode/riscv.h. * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want to check the ISA dependency for CSR, so fix the spec version by adding -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some version warnings for the test case. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case. Check whether the CSR is valid when privilege version 1.9 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case. Check whether the CSR is valid when privilege version 1.9.1 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case. Check whether the CSR is valid when privilege version 1.10 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case. Check whether the CSR is valid when privilege version 1.11 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option setting. You can set it by configure option --with-priv-spec. (riscv_set_default_priv_spec): New function used to set the default privilege spec. (md_parse_option): Call riscv_set_default_priv_spec rather than call riscv_get_priv_spec_class directly. (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by calling riscv_set_default_priv_spec. * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since the --with-priv-spec may be set to different privilege spec. * testsuite/gas/riscv/priv-reg.d: Likewise. * configure.ac: Add configure option --with-priv-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to explicit_attr. Set it to TRUE if any ELF attribute is found. (riscv_set_default_priv_spec): Try to set the default_priv_spec if the priv attributes are set. (md_assemble): Set the default_priv_spec according to the priv attributes when we start to assemble instruction. (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to riscv_write_out_attrs. Update the arch and priv attributes. If we don't set the corresponding ELF attributes, then try to output the default ones. (riscv_set_public_attributes): If any ELF attribute or -march-attr options is set (explicit_attr is TRUE), then call riscv_write_out_attrs to update the arch and priv attributes. (s_riscv_attribute): Make sure all arch and priv attributes are set before any instruction. * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any ELF attribute or -march-attr is set. If the priv attributes are not set, then try to update them by the default setting (-mpriv-spec or --with-priv-spec). * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec set by priv attributes must be supported. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated priv attributes according to the -mpriv-spec option. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg.d: Removed. * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the CSR according to the priv spec 1.9. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the CSR according to the priv spec 1.9.1. * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the CSR according to the priv spec 1.10. * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the CSR according to the priv spec 1.11. * config/tc-riscv.c (md_show_usage): Add descriptions about the new GAS options. * doc/c-riscv.texi: Likewise.
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner4-0/+82
opcodes/ * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new WC values on POWER10 sync, dcbf and wait instructions. (insert_pl, extract_pl): New functions. (L2OPT, LS, WC): Use insert_ls and extract_ls. (LS3): New , 3-bit L for sync. (LS3, L3OPT): New, 3-bit L for sync and dcbf. (SC2, PL): New, 2-bit SC and PL for sync and wait. (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. (XOPL3, XWCPL, XSYNCLS): New opcode macros. (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. <wait>: Enable PL operand on POWER10. <dcbf>: Enable L3OPT operand on POWER10. <sync>: Enable SC2 operand on POWER10. gas/ * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync, pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync, sync, wait, waitrsv>: Add tests. * testsuite/gas/ppc/power10.d: Likewise.
2020-05-19Fix the ARM assembler to generate a Realtime profile for armv8-r.Alexander Fedotov4-4/+4
PR 25992 gas * config/tc-arm.c : Add arm_ext_v8r feature. (it_fsm_post_encode): Check arm_ext_v8r feature. (get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature. include * opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
2020-05-18Don't handle lret/iret when -mlfence-before-ret=[or|not|shl|yes] since they ↵liuhongt12-167/+1
are invalid in SGX enclaves. gas/ChangeLog * gas/config/tc-i386.c: Not handle lret/iret. * gas/testsuite/gas/i386/lfence-ret-a.d: Adjust testcase. * gas/testsuite/gas/i386/lfence-ret-b.d: Ditto. * gas/testsuite/gas/i386/lfence-ret-c.d: Ditto. * gas/testsuite/gas/i386/lfence-ret-d.d: Ditto. * gas/testsuite/gas/i386/lfence-ret.s: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret.s: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
2020-05-15Fix tight loop on recursively-defined symbolsAlan Modra4-0/+20
This patch fixes a bug in GAS where the assembler enters a tight loop when attempting to resolve recursively-defined symbols, e.g. when trying to assemble "a=a". This is a regression introduced between binutils 2.32 and 2.33, by commit 1903f1385bff9 * symbols.c (struct local_symbol): Update comment. (resolve_symbol_value): For resolved symbols equated to other symbols, verify that the referenced symbol is not a local_symbol before accessing sy_value. Don't leave symbol loops during finalize_syms resolution. * testsuite/gas/all/assign-bad-recursive.d: New test. * testsuite/gas/all/assign-bad-recursive.l: Error output for test. * testsuite/gas/all/assign-bad-recursive.s: Assembly for test. * testsuite/gas/all/gas.exp: Run it.
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra3-0/+23
opcodes/ * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, xsmaxcqp, xsmincqp. gas/ * testsuite/gas/ppc/scalarquad.d, * testsuite/gas/ppc/scalarquad.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra3-0/+28
opcodes/ * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, stxvrbx, stxvrhx, stxvrwx, stxvrdx. gas/ * testsuite/gas/ppc/rightmost.d, * testsuite/gas/ppc/rightmost.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 test lsb by byte operationAlan Modra3-0/+28
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. gas/ * testsuite/gas/ppc/xvtlsbb.d, * testsuite/gas/ppc/xvtlsbb.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
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