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2020-08-18PowerPC: Rename xvcvbf16sp to xvcvbf16spnPeter Bergner2-2/+2
The xvcvbf16sp mnemonic has been renamed to xvcvbf16spn, to be consistent with the other non-signaling conversion instructions which all end with "n". opcodes/ * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this... <xvcvbf16spn>: ...to this. gas/ * testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic. * testsuite/gas/ppc/vsx4.d: Likewise.
2020-08-17gas: Fix internal error in S_SET_SEGMENTAlex Coplan3-0/+9
This patch fixes an internal error in GAS when defining a section using a symbol that has already been named but not defined. For a minimal reproducer, try the following input: a=b .sect a The problem is that obj_elf_change_section() happily reuses the symbol "a" created by equals() without clearing the sy_value field: prior to this patch, it just set bsym. This caused a problem when attempting to resolve the section symbol, since resolve_symbol_value() ended up resolving the symbol as if it were the original symbol created by equals(), which ends up leaving the section symbol in the undefined section instead of in section a, hence the call to abort() in S_SET_SEGMENT(). gas/ChangeLog: * config/obj-elf.c (obj_elf_change_section): When repurposing an existing symbol, ensure that we set sy_value as per other (fresh) section symbols. * testsuite/gas/elf/elf.exp: Add new test. * testsuite/gas/elf/section-symbol-redef.d: New test. * testsuite/gas/elf/section-symbol-redef.s: Input for test.
2020-08-12[PATCH] gas: arm: Fix IT-predicated MVE vcvtJoe Ramsay5-0/+23
* config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for NS_FD shape when MVE is present * testsuite/gas/arm/mve-vcvtne-it-bad.d: New test. * testsuite/gas/arm/mve-vcvtne-it-bad.l: New test. * testsuite/gas/arm/mve-vcvtne-it-bad.s: New test. * testsuite/gas/arm/mve-vcvtne-it.d: New test. * testsuite/gas/arm/mve-vcvtne-it.s: New test.
2020-08-12aarch64: Add support for MPAM system registersAlex Coplan5-0/+74
This patch adds support for the system registers introduced in the Armv8-A MPAM extension. See https://developer.arm.com/documentation/ddi0598/latest for the Arm ARM supplement documenting this extension. gas/ChangeLog: * testsuite/gas/aarch64/mpam-bad.d: New test. * testsuite/gas/aarch64/mpam-bad.l: Error output. * testsuite/gas/aarch64/mpam-bad.s: Input. * testsuite/gas/aarch64/mpam.d: New test. * testsuite/gas/aarch64/mpam.s: Input. opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
2020-08-10aarch64: Don't assert on long sysreg namesAlex Coplan3-0/+7
This patch fixes an assertion failure on long system register operands in the AArch64 backend. See the new testcase for an input which reproduces the issue. gas/ChangeLog: * config/tc-aarch64.c (parse_sys_reg): Don't assert when parsing a long system register. (parse_sys_ins_reg): Likewise. (sysreg_hash_insert): New. (md_begin): Use sysreg_hash_insert() to ensure all system registers are no longer than the maximum length at startup. * testsuite/gas/aarch64/invalid-sysreg-assert.d: New test. * testsuite/gas/aarch64/invalid-sysreg-assert.l: Error output. * testsuite/gas/aarch64/invalid-sysreg-assert.s: Input. include/ChangeLog: * opcode/aarch64.h (AARCH64_MAX_SYSREG_NAME_LEN): New.
2020-08-10[aarch64] GAS doesn't validate the architecture version for any tlbi ↵Przemyslaw Wirkus3-0/+6
registers. Fixed with this patch. * gas/config/tc-aarch64.c (parse_sys_reg): Call to aarch64_sys_ins_reg_supported_p instead of aarch64_sys_reg_supported_p. (parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check. * include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions paramaters changed. (aarch64_sys_reg_supported_p): Function removed. (aarch64_sys_ins_reg_supported_p): Functions paramaters changed. * opcodes/aarch64-opc.c (aarch64_print_operand): (aarch64_sys_reg_deprecated_p): Functions paramaters changed. (aarch64_sys_reg_supported_p): Function removed. (aarch64_sys_ins_reg_supported_p): Functions paramaters changed. (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p into this function. * gas/testsuite/gas/aarch64/illegal-sysreg-5.d: New test. * gas/testsuite/gas/aarch64/illegal-sysreg-5.l: New test. * gas/testsuite/gas/aarch64/sysreg-5.s: New test.
2020-08-10Implement missing powerpc extended mnemonicsAlan Modra4-0/+12
gas/ * testsuite/gas/ppc/power8.d, * testsuite/gas/ppc/power8.s: Add miso. * testsuite/gas/ppc/power9.d, * testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru. opcodes/ * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru. Enable icbt for power5, miso for power8.
2020-08-10Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassemblyAlan Modra2-200/+200
gas/ * testsuite/gas/ppc/power8.d: Update. * testsuite/gas/ppc/vsx2.d: Update. opcodes/ * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over mtvsrd, and similarly for mfvsrd.
2020-08-10Error on lmw, lswi and related PowerPC insns when LEAlan Modra9-1075/+1088
* config/tc-ppc.c (md_assemble): Error for lmw, stmw, lswi, lswx, stswi, or stswx in little-endian mode. * testsuite/gas/ppc/476.d, * testsuite/gas/ppc/476.s: Delete lmw, stmw, lswi, lswx, stswi, stswx. * testsuite/gas/ppc/a2.d, * testsuite/gas/ppc/a2.s: Move lmw, stmw, lswi, lswx, stswi, stswx.. * testsuite/gas/ppc/be.d, * testsuite/gas/ppc/be.s: ..to here, new big-endian only test. * testsuite/gas/ppc/le_error.d, * testsuite/gas/ppc/le_error.l: New little-endian test. * testsuite/gas/ppc/ppc.exp: Run new tests.
2020-08-06gas: Fix internal error on long local labelsAlex Coplan4-0/+7
Prior to this commit, on an input such as "88888888888:", GAS hits a signed integer overflow and likely an assertion failure. I see: $ echo "88888888888:" | bin/aarch64-none-elf-as {standard input}: Assembler messages: {standard input}:1: Internal error in fb_label_name at ../gas/symbols.c:2049. Please report this bug. To fix this issue, I've taken two steps: 1. Change the type used for processing local labels in read_a_source_file() from int to long, to allow representing more local labels, and also since all uses of this variable (temp) are actually of type long. 2. Detect if we would overflow and bail out with an error message instead of actually overflowing and hitting the assertion in fb_label_name(). gas/ChangeLog: 2020-08-06 Alex Coplan <alex.coplan@arm.com> * read.c (read_a_source_file): Use long for local labels, detect overflow and raise an error for overly-long labels. * testsuite/gas/all/gas.exp: Add local-label-overflow test. * testsuite/gas/all/local-label-overflow.d: New test. * testsuite/gas/all/local-label-overflow.l: Error output. * testsuite/gas/all/local-label-overflow.s: Input.
2020-08-04Z8k: fix sout/soudb opcodes with direct addressChristian Groessler1-2/+2
Problem found by Tadashi G. Takaoka. 2020-08-04 Christian Groessler <chris@groessler.org> Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com> * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs" opcodes (special "out" to absolute address). * z8k-opc.h: Regenerate. 2020-08-04 Christian Groessler <chris@groessler.org> * gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of "sout/soutb #imm,reg"
2020-08-04gas: Revert an accidental change in x86-64-pseudos.dH.J. Lu1-1/+1
Revert an accidental change in commit 41eb8e88859b297f59f4d093aab9306d4b7057d9 Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Jul 30 16:13:02 2020 -0700 x86: Add {disp16} pseudo prefix @@ -304,7 +308,7 @@ Disassembly of section .text: +[a-f0-9]+: 40 d3 e0 rex shl %cl,%eax +[a-f0-9]+: 40 a0 01 00 00 00 00 00 00 00 rex movabs 0x1,%al +[a-f0-9]+: 40 38 ca rex cmp %cl,%dl - +[a-f0-9]+: 40 b3 01 rex mov \$(0x)?1,%bl + +[a-f0-9]+: 40 b3 01 rex mov \$(0x)1,%bl +[a-f0-9]+: f2 40 0f 38 f0 c1 rex crc32 %cl,%eax +[a-f0-9]+: 40 89 c3 rex mov %eax,%ebx +[a-f0-9]+: 41 89 c6 mov %eax,%r14d PR gas/26305 * testsuite/gas/i386/x86-64-pseudos.d: Revert an accidental change.
2020-08-04gas: Fix .debug_info CU header for --gdwarf-5Mark Wielaard5-0/+52
DWARF5 CU headers have a new unit type field and move the abbrev offset to the end of the header. gas/ChangeLog: * dwarf2dbg.c (out_debug_info): Emit unit type and abbrev offset for DWARF5. * gas/testsuite/gas/elf/dwarf-4-cu.d: New file. * gas/testsuite/gas/elf/dwarf-4-cu.s: Likewise. * gas/testsuite/gas/elf/dwarf-5-cu.d: Likewise. * gas/testsuite/gas/elf/dwarf-5-cu.s: Likewise. * testsuite/gas/elf/elf.exp: Run dwarf-4-cu and dwarf-5-cu.
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu9-10/+125
Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo prefixes. gas/ PR gas/26305 * config/tc-i386.c (_i386_insn::disp_encoding): Add disp_encoding_16bit. (parse_insn): Check Prefix_XXX for pseudo prefixes. Handle {disp16}. (build_modrm_byte): Handle {disp16}. (i386_index_check): Check invalid {disp16} and {disp32} pseudo prefixes. * doc/c-i386.texi: Update {disp32} documentation and document {disp16}. * testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo. * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16} tests. * testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps tests with 128-byte displacement. Add {disp16} tests. * testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32} vmovaps test. Add (%r13)/(%r13d) tests. * testsuite/gas/i386/x86-64-inval-pseudo.l: New file. * testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise. * testsuite/gas/i386/inval-pseudo.l: Updated. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/26305 * i386-opc.h (Prefix_Disp8): New. (Prefix_Disp16): Likewise. (Prefix_Disp32): Likewise. (Prefix_Load): Likewise. (Prefix_Store): Likewise. (Prefix_VEX): Likewise. (Prefix_VEX3): Likewise. (Prefix_EVEX): Likewise. (Prefix_REX): Likewise. (Prefix_NoOptimize): Likewise. * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}. * i386-tbl.h: Regenerated.
2020-07-30x86: Pass --gdwarf-3 to assemblerH.J. Lu6-5/+6
Pass --gdwarf-3 to assembler for commit 4d8ee860737005517be588f4771c358593fa421c Author: Nick Clifton <nickc@redhat.com> Date: Thu Jul 30 08:39:14 2020 +0100 Prevent the generation of DWARF level 0 line number tables... binutils/ * testsuite/binutils-all/i386/compressed-1a.d: Pass --gdwarf-3 to assembler. * testsuite/binutils-all/i386/compressed-1b.d: Likewise. * testsuite/binutils-all/i386/compressed-1c.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1a.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1b.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1c.d: Likewise. gas/ * testsuite/gas/elf/dwarf2-3.d:Pass --gdwarf-3 to assembler. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/i386/dw2-compress-3a.d: Likewise. * testsuite/gas/i386/dw2-compress-3b.d: Likewise. * testsuite/gas/i386/dw2-compressed-3a.d: Likewise. * testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
2020-07-29MIPS: Make the IRIX naming of local section symbols consistentMaciej W. Rozycki7-0/+83
Make the MIPS/IRIX naming of local section symbols consistent between files produced by generic ELF code and ELF linker code, complementing commit 174fd7f95561 ("New bfd elf hook: force naming of local section symbols"), <https://sourceware.org/ml/binutils/2004-02/msg00072.html>. Local section symbols have no names in the standard ELF gABI, however the lack of a name causes problems with IRIX's MIPSpro linker. To work around the issue we give them names, however we do that in generic ELF code only, based on what the `elf_backend_name_local_section_symbols' hook returns if present. That makes objects created by GAS or `objdump' work correctly, however not ones created by `ld -r'. That would not normally cause issues with IRIX systems using GAS and `objdump' only with the MIPSpro linker, however if GNU LD was used for whatever reason in producing objects later fed to IRIX's MIPSpro linker, then things would break. Modify ELF linker code accordingly then, using the same hook. Adjust the `ld-elf/64ksec-r' test accordingly so that it also accepts a section symbol with a name. Also modify the hook itself so that only actual ET_REL objects have names assigned to local section symbols. Other kinds of ELF files are not ever supposed to be relocated with the MIPSpro linker, so we can afford producing more standard output. Add suitable GAS, LD and `objcopy' test cases to the relevant testsuites to keep these tools consistently verified. This change also fixes: FAIL: objcopy executable (pr25662) across MIPS targets using the IRIX compatibility mode. bfd/ * elflink.c (bfd_elf_final_link): Give local symbols a name if so requested. * elfxx-mips.c (_bfd_mips_elf_name_local_section_symbols): Only return TRUE if making ET_REL output. binutils/ * testsuite/binutils-all/mips/global-local-symtab-sort-o32.d: New test. * testsuite/binutils-all/mips/global-local-symtab-sort-o32t.d: New test. * testsuite/binutils-all/mips/global-local-symtab-sort-n32.d: New test. * testsuite/binutils-all/mips/global-local-symtab-sort-n32t.d: New test. * testsuite/binutils-all/mips/global-local-symtab-sort-n64.d: New test. * testsuite/binutils-all/mips/global-local-symtab-sort-n64t.d: New test. * testsuite/binutils-all/mips/global-local-symtab-final-o32.d: New test. * testsuite/binutils-all/mips/global-local-symtab-final-n32.d: New test. * testsuite/binutils-all/mips/global-local-symtab-final-n64.d: New test. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/global-local-symtab-sort-o32.d: New test. * testsuite/gas/mips/global-local-symtab-sort-o32t.d: New test. * testsuite/gas/mips/global-local-symtab-sort-n32.d: New test. * testsuite/gas/mips/global-local-symtab-sort-n32t.d: New test. * testsuite/gas/mips/global-local-symtab-sort-n64.d: New test. * testsuite/gas/mips/global-local-symtab-sort-n64t.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-elf/sec64k.exp: Also accept a section symbol with a name. * testsuite/ld-mips-elf/global-local-symtab-sort-o32.d: New test. * testsuite/ld-mips-elf/global-local-symtab-sort-o32t.d: New test. * testsuite/ld-mips-elf/global-local-symtab-sort-n32.d: New test. * testsuite/ld-mips-elf/global-local-symtab-sort-n32t.d: New test. * testsuite/ld-mips-elf/global-local-symtab-sort-n64.d: New test. * testsuite/ld-mips-elf/global-local-symtab-sort-n64t.d: New test. * testsuite/ld-mips-elf/global-local-symtab-final-o32.d: New test. * testsuite/ld-mips-elf/global-local-symtab-final-n32.d: New test. * testsuite/ld-mips-elf/global-local-symtab-final-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2020-07-29MIPS/LD: Set symtab's `sh_info' correctly for IRIX emulationsMaciej W. Rozycki7-0/+52
Correct ELF linker code so as to set the `sh_info' value of the static symbol table section according to the section symbols vs other symbols split where required by the selection of the IRIX compatibility mode for MIPS target. Add a `elf_backend_elfsym_local_is_section' hook for that purpose, returning TRUE if it is only STB_LOCAL/STT_SECTION symbols that are to be considered local for the purpose of this split rather than all STB_LOCAL symbols. We do it already in generic ELF code, and have done it since 1993, with the `elf_backend_sym_is_global' hook, affecting GAS and `objcopy', so these tools produce correct ELF output in the IRIX compatibility mode, however if such output is fed as input to `ld -r', then the linker's output is no longer valid for that mode. The relevant changes to generic ELF code are: commit 062189c6eab72c7ba1bab1cf30fdb27d67a7d668 Author: Ian Lance Taylor <ian@airs.com> Date: Thu Nov 18 17:12:47 1993 +0000 and: commit 6e07e54f1b347f885cc6c021c3fd912c79bdaf55 Author: Ian Lance Taylor <ian@airs.com> Date: Thu Jan 6 20:01:42 1994 +0000 (split across two GIT commits likely due to repository conversion peculiarities). The `elf_backend_sym_is_global' hook however operates on BFD rather than ELF symbols, making it unsuitable for the ELF linker as the linker does not convert any symbol tables processed into the BFD format. Converting the hook to operate on ELF symbols would in principle be possible, but it would still require a considerable rewrite of `bfd_elf_final_link' to adapt to the interface. Therefore, especially given that no new use for the IRIX compatibility mode is expected, minimize changes made to the ELF linker code and just add an entirely new hook, and wire it in the o32 and n32 MIPS backends accordingly; the n64 backend never uses the IRIX compatibility mode. Since we have no coverage here at all add suitable GAS, LD and `objcopy' test cases to the relevant testsuites to keep these tools consistently verified. bfd/ * elf-bfd.h (elf_backend_data): Add `elf_backend_elfsym_local_is_section' member. * elfxx-target.h (elf_backend_elfsym_local_is_section): New macro. (elfNN_bed): Add `elf_backend_elfsym_local_is_section' member. * elflink.c (bfd_elf_final_link): Use it to determine whether set the `.symtab' section's `sh_info' value to the index of the first non-local or non-section symbol. * elf32-mips.c (mips_elf32_elfsym_local_is_section): New function. (elf_backend_elfsym_local_is_section): New macro. * elfn32-mips.c (mips_elf_n32_elfsym_local_is_section): New function. (elf_backend_elfsym_local_is_section): New macro. binutils/ * testsuite/binutils-all/mips/global-local-symtab-o32.d: New test. * testsuite/binutils-all/mips/global-local-symtab-o32t.d: New test. * testsuite/binutils-all/mips/global-local-symtab-n32.d: New test. * testsuite/binutils-all/mips/global-local-symtab-n32t.d: New test. * testsuite/binutils-all/mips/global-local-symtab-n64.d: New test. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/global-local-symtab-o32.d: New test. * testsuite/gas/mips/global-local-symtab-o32t.d: New test. * testsuite/gas/mips/global-local-symtab-n32.d: New test. * testsuite/gas/mips/global-local-symtab-n32t.d: New test. * testsuite/gas/mips/global-local-symtab-n64.d: New test. * testsuite/gas/mips/global-local-symtab.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/global-local-symtab-o32.d: New test. * testsuite/ld-mips-elf/global-local-symtab-o32t.d: New test. * testsuite/ld-mips-elf/global-local-symtab-n32.d: New test. * testsuite/ld-mips-elf/global-local-symtab-n32t.d: New test. * testsuite/ld-mips-elf/global-local-symtab-n64.d: New test. * testsuite/ld-mips-elf/global-local-symtab.ld: New test linker script. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2020-07-28x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)H.J. Lu4-0/+70
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. Note: Since there is no disp32 on 0(%bp), use disp16 instead. PR gas/26305 * config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on (%bp)/(%ebp)/(%rbp) for {disp32}. * doc/c-i386.texi: Update {disp32} documentation. * testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests. * testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests. * testsuite/gas/i386/pseudos.d: Updated. * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
2020-07-22MIPS/GAS/testsuite: Fix JALR relocation tests for IRIX targetsMaciej W. Rozycki25-12/+1819
With IRIX targets the JALR hint relocation is not produced for the o32 ABI, where it is considered a GNU extension. Consequently several tests fail as the output produced by GAS fails to match patterns expecting the relocation to be present where appropriate, even though output produced is indeed correct. As the absence of the relocation is expected, fix the tests by providing respective alternative dump patterns with any JALR relocations removed, removing numerous failures with `*-*-irix*' targets: FAIL: MIPS jal-svr4pic (interaptiv-mr2) FAIL: MIPS jal-svr4pic (micromips) FAIL: MIPS jal-svr4pic (mips1) FAIL: MIPS jal-svr4pic (mips2) FAIL: MIPS jal-svr4pic (mips3) FAIL: MIPS jal-svr4pic (mips4) FAIL: MIPS jal-svr4pic (mips5) FAIL: MIPS jal-svr4pic (mips32) FAIL: MIPS jal-svr4pic (mips32r2) FAIL: MIPS jal-svr4pic (mips32r3) FAIL: MIPS jal-svr4pic (mips32r5) FAIL: MIPS jal-svr4pic (mips32r6) FAIL: MIPS jal-svr4pic (mips64) FAIL: MIPS jal-svr4pic (mips64r2) FAIL: MIPS jal-svr4pic (mips64r3) FAIL: MIPS jal-svr4pic (mips64r5) FAIL: MIPS jal-svr4pic (mips64r6) FAIL: MIPS jal-svr4pic (octeon) FAIL: MIPS jal-svr4pic (octeon2) FAIL: MIPS jal-svr4pic (octeon3) FAIL: MIPS jal-svr4pic (octeonp) FAIL: MIPS jal-svr4pic (r3000) FAIL: MIPS jal-svr4pic (r3900) FAIL: MIPS jal-svr4pic (r4000) FAIL: MIPS jal-svr4pic (r5900) FAIL: MIPS jal-svr4pic (sb1) FAIL: MIPS jal-svr4pic (vr5400) FAIL: MIPS jal-svr4pic (xlr) FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2) FAIL: MIPS jal-svr4pic noreorder (micromips) FAIL: MIPS jal-svr4pic noreorder (mips1) FAIL: MIPS jal-svr4pic noreorder (mips2) FAIL: MIPS jal-svr4pic noreorder (mips3) FAIL: MIPS jal-svr4pic noreorder (mips4) FAIL: MIPS jal-svr4pic noreorder (mips5) FAIL: MIPS jal-svr4pic noreorder (mips32) FAIL: MIPS jal-svr4pic noreorder (mips32r2) FAIL: MIPS jal-svr4pic noreorder (mips32r3) FAIL: MIPS jal-svr4pic noreorder (mips32r5) FAIL: MIPS jal-svr4pic noreorder (mips32r6) FAIL: MIPS jal-svr4pic noreorder (mips64) FAIL: MIPS jal-svr4pic noreorder (mips64r2) FAIL: MIPS jal-svr4pic noreorder (mips64r3) FAIL: MIPS jal-svr4pic noreorder (mips64r5) FAIL: MIPS jal-svr4pic noreorder (mips64r6) FAIL: MIPS jal-svr4pic noreorder (octeon) FAIL: MIPS jal-svr4pic noreorder (octeon2) FAIL: MIPS jal-svr4pic noreorder (octeon3) FAIL: MIPS jal-svr4pic noreorder (octeonp) FAIL: MIPS jal-svr4pic noreorder (r3000) FAIL: MIPS jal-svr4pic noreorder (r3900) FAIL: MIPS jal-svr4pic noreorder (r4000) FAIL: MIPS jal-svr4pic noreorder (r5900) FAIL: MIPS jal-svr4pic noreorder (sb1) FAIL: MIPS jal-svr4pic noreorder (vr5400) FAIL: MIPS jal-svr4pic noreorder (xlr) FAIL: MIPS R3000 jal-xgot FAIL: MIPS -mabi=32 test 2 (SVR4 PIC) FAIL: gas/mips/jalr2 FAIL: Relax microMIPS branches (pic) FAIL: Relax microMIPS branches (insn32 mode, pic) Strictly speaking no MIPSr6 or microMIPS target is supported by IRIX, but GAS supports such configurations on the basis of uniformity, so provide the relevant patterns too rather than excluding the combinations from testing. gas/ * testsuite/gas/mips/jal-svr4pic-irix.d: New file. * testsuite/gas/mips/mips1@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/mipsr6@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/micromips@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/r3000@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/mips1@jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/micromips@jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/r3000@jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/mips1@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/micromips@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/r3000@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/jal-xgot-irix.d: New file. * testsuite/gas/mips/jalr2-irix.d: New file. * testsuite/gas/mips/micromips-branch-relax-insn32-pic-irix.d: New file. * testsuite/gas/mips/micromips-branch-relax-pic-irix.d: New file. * testsuite/gas/mips/mips-abi32-pic2-irix.d: New file. * testsuite/gas/mips/jal-svr4pic-local.d: Don't exclude `*-*-irix*' targets. Add source file designator. * testsuite/gas/mips/mips1@jal-svr4pic-local.d: Don't exclude `*-*-irix*' targets. * testsuite/gas/mips/r3000@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/jalr2.d: Add name designator. * testsuite/gas/mips/mips.exp: Use respective IRIX variants for tests involving the JALR relocation throughout.
2020-07-22MIPS/GAS/testsuite: Use a helper variable for IRIX/non-IRIX test selectionMaciej W. Rozycki1-5/+2
Define a helper variable for IRIX/non-IRIX test selection and use it with the PR 14798 test case. gas/ * testsuite/gas/mips/mips.exp: Use a helper variable for IRIX/non-IRIX test selection.
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich3-13/+13
This reverts commit 04c662e2b66bedd050f97adec19afe0fcfce9ea7. In my underlying suggestion I neglected the fact that in those cases (,%eiz,1) is the only visible indication that 32-bit addressing is in effect.
2020-07-21Revert "x86: Replace evex-no-scale.s with evex-no-scale-[32|64].s"Jan Beulich5-9/+15
This reverts commit 19449d7c67690c641b1ec9c13ff3531677a5afcc, addressing the issue that was run into back then: There was no relationship to i686-* and/or cross builds on 64-bit hosts. The sole problem was the use of / as as comment character in certain ELF targets. Instead of division, use a comparison operation. At the same time also revert the ELF related part of 99c2d522f7a7 ("x86: Update assembler tests for non-ELF targets") by replacing the construct that's problematic for non-ELF, and by adding the "#pass" patterns to the expected output files to cover for the tail padding generated into COFF output.
2020-07-20x86: handle SVR4 escaped binary operatorsJan Beulich3-0/+63
PR gas/4572 When / is a comment character, its use as binary "divide" operator needs escaping by a backslash. Besides the scrubber needing to support this (addressed in an earlier change), there are also a few provisions needed in target specific operator handling. As the spec calls for % and * to also be escaped because of being "overloaded", also recognize these, despite the overloading there not really preventing their use as operators in most (%) or all (*) cases, given the way how the rest of the assembler works. To bring source and testsuite in line, also drop the TE_I386AIX part of the respective conditional, as i?86-*-aix* support had been removed a while ago.
2020-07-20x86: honor absolute section when emitting codeJan Beulich4-0/+100
Various provisions exist for insns to be placed in the absolute section, yet actually trying to do so didn't work. While data emission (of non- zero values) is not allowed by generic code, I think this functionality is useful for the programmer to be able to determine the size of insns. Therefore, rather than turning the silnet failure into a verbose one, make things mostly work; the one class of insns not supported (yet) are branches (JMP and Jcc) with dynamically determined displacement widths. In this one case, an error now gets reported instead of silently ignoring the code. Also avoid recording ISA / feature usage for insns emitted to the absolute section.
2020-07-20ix86: enable more ELF tests for VxWorksJan Beulich1-9/+14
The tree-wide is_elf_format predicate excludes VxWorks, but the majority of ELF specific tests is quite fine for this target.
2020-07-19x86: Change PLT32 reloc against section to PC32H.J. Lu2-2/+2
Commit 292676c1 resolved PLT32 reloc aganst local symbol to section. Since PLT32 relocation must be against symbols, turn such PLT32 relocation into PC32 relocation. gas/ PR gas/26263 * config/tc-i386.c (i386_validate_fix): Change PLT32 reloc against section to PC32 reloc. * testsuite/gas/i386/relax-5.d: Updated. * testsuite/gas/i386/x86-64-relax-4.d: Likewise. ld/ PR gas/26263 * testsuite/ld-i386/i386.exp: Run PR gas/26263 test. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr26263.d: New file. * testsuite/ld-x86-64/pr26263.d: Likewise. * testsuite/ld-x86-64/pr26263.s: Likewise.
2020-07-15x86: Don't display eiz with no scaleH.J. Lu3-13/+13
Change 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx to 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx in AT&T syntax and 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef] to 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef in Intel syntax. gas/ PR gas/26237 * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Don't display eiz with no scale without base nor index registers.
2020-07-15x86-64: adjust stack insn test caseJan Beulich4-17/+17
The value chosen for the 16-/32-bit immediate cases didn't work well with the subsequent insn's REX prefix - we ought to pick a value the upper two bytes of which evaluate to a 2-byte insn. Bump the values accordingly, allowing the subsequent insn to actually have the intended REX.W.
2020-07-15x86: avoid attaching suffixes to unambiguous insnsJan Beulich71-487/+489
"Unambiguous" is is in particular taking as reference the assembler, which also accepts certain insns - despite them allowing for varying operand size, and hence in principle being ambiguous - without any suffix. For example, from the very beginning of the life of x86-64 I had trouble understanding why a plain and simple RET had to be printed as RETQ. In case someone really used the 16-bit form, RETW disambiguates the two quite fine.
2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu7-54/+36
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to 64 bits, change disassembler to zero-extend the lower 32 bits displacement to 64 bits when there is no base nor index registers. gas/ PR gas/26237 * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around address. * testsuite/gas/i386/x86-64-addr32.s: Likewise. * testsuite/gas/i386/addr32.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Without base nor index registers, 32-bit displacement to 64 bits.
2020-07-14x86/Intel: debug registers are named DRnJan Beulich4-7/+7
%db<n> is an AT&T invention; the Intel documentation and MASM have only ever specified DRn (in line with CRn and TRn). (In principle gas also shouldn't accept the names in Intel mode, but at least for now I've kept things as they are. Perhaps as a first step this should just be warned about.)
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-4/+4
The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich2-4/+4
The operands don't allow disambiguating the insn in 64-bit mode, and hence suffixes need to be emitted not just in AT&T mode. Achieve this by re-using %LQ while dropping PCMPESTR_Fixup().
2020-07-14x86: don't disassemble MOVBE with two suffixesJan Beulich3-0/+52
MOVBE_Fixup() is entirely redundant with the S macro already used on the mnemonics, leading to double suffixes in suffix-always mode. Drop the function.
2020-07-14x86: avoid attaching suffix to register-only CRC32Jan Beulich32-675/+133
Just like other insns with GPR operands, CRC32 with only register operands should not get a suffix added unless in suffix-always mode. Do away with CRC32_Fixup() altogether, using other more generic logic instead.
2020-07-14x86-64: don't hide an empty but meaningless REX prefixJan Beulich4-8/+14
Unlike for non-zero values passed to USED_REX(), where rex_used gets updated only when the respective bit was actually set in the encoding, zero getting passed in is not further guarded, yet such a (potentially "empty") REX prefix takes effect only when there are registers numbered 4 and up.
2020-07-14x86: drop dead code from OP_IMREG()Jan Beulich2-0/+4
There's only a very limited set of modes that this function gets invoked with - avoid it being more generic than it needs to be. This may, down the road, allow actually doing away with the function altogether. This eliminates a first improperly used "USED_REX (0)".
2020-07-14x86-64: fold ILP32 test expectationsJan Beulich16-7806/+16
Various of the test expectations get adjusted later in this and a subsequent series, so in order to avoid having to adjust more instances than necessary fold respective test ILP32 expectations with their main 64-bit counterparts where they're identical anyway.
2020-07-13gas DWARF2 test XPASSesAlan Modra4-8/+4
git commit af2b318648 introduced a number of XPASSes. This removes them. (It also introduces a FAIL on ft32-elf but the comment in the .d file didn't adequately explain why the failure should be expected.) * testsuite/gas/elf/dwarf2-7.d: Remove most xfails. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise.
2020-07-11x86: Support GNU_PROPERTY_X86_FEATURE_2_TMMH.J. Lu7-0/+36
Support GNU_PROPERTY_X86_FEATURE_2_TMM in https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/1 #define GNU_PROPERTY_X86_FEATURE_2_TMM (1U << 10) binutils/ * readelf.c (decode_x86_feature_2): Handle GNU_PROPERTY_X86_FEATURE_2_TMM. gas/ * config/tc-i386.c (output_insn): Check i.xstate to set GNU_PROPERTY_X86_FEATURE_2_TMM. * testsuite/gas/i386/i386.exp: Run x86-64-property-7, x86-64-property-8 and x86-64-property-9. * testsuite/gas/i386/x86-64-property-7.d: New file. * testsuite/gas/i386/x86-64-property-7.s: Likewise. * testsuite/gas/i386/x86-64-property-8.d: Likewise. * testsuite/gas/i386/x86-64-property-8.s: Likewise. * testsuite/gas/i386/x86-64-property-9.d: Likewise. * testsuite/gas/i386/x86-64-property-9.s: Likewise. include/ * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_TMM): New.
2020-07-10x86: Extract extended states from instruction templateH.J. Lu4-0/+23
Extract extended states from operand types in instruction template. Set xstate_zmm for master register move. * config/tc-i386.c (_i386_insn): Remove has_regmmx, has_regxmm, has_regymm, has_regzmm and has_regtmm. Add xstate. (md_assemble): Set i.xstate from operand types in instruction template. (build_modrm_byte): Updated. (output_insn): Check i.xstate. * testsuite/gas/i386/i386.exp: Run property-6 and x86-64-property-6. * testsuite/gas/i386/property-6.d: New file. * testsuite/gas/i386/property-6.s: Updated. * testsuite/gas/i386/x86-64-property-6.d: Likewise.
2020-07-10gas/i386/property-5.d: Correct test nameH.J. Lu1-1/+1
* testsuite/gas/i386/property-5.d: Correct test name.
2020-07-10x86: Add support for Intel AMX instructionsLili Cui10-0/+339
gas/ * doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile. * config/tc-i386.c (i386_error): Add invalid_sib_address. (cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile. (cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile. (match_simd_size): Add tmmword check. (operand_type_match): Add tmmword. (type_names): Add rTMM. (i386_error): Add invalid_tmm_register_set. (check_VecOperands): Handle invalid_sib_address and invalid_tmm_register_set. (match_template): Handle invalid_sib_address. (build_modrm_byte): Handle non-vector SIB and zmmword. (i386_index_check): Disallow RegIP for non-vector SIB. (check_register): Handle zmmword. * testsuite/gas/i386/i386.exp: Add AMX new tests. * testsuite/gas/i386/intel-regs.d: Add tmm. * testsuite/gas/i386/intel-regs.s: Add tmm. * testsuite/gas/i386/x86-64-amx-intel.d: New. * testsuite/gas/i386/x86-64-amx-inval.l: New. * testsuite/gas/i386/x86-64-amx-inval.s: New. * testsuite/gas/i386/x86-64-amx.d: New. * testsuite/gas/i386/x86-64-amx.s: New. * testsuite/gas/i386/x86-64-amx-bad.d: New. * testsuite/gas/i386/x86-64-amx-bad.s: New. opcodes/ * i386-dis.c (TMM): New. (EXtmm): Likewise. (VexTmm): Likewise. (MVexSIBMEM): Likewise. (tmm_mode): Likewise. (vex_sibmem_mode): Likewise. (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise. (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise. (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise. (PREFIX_VEX_0F3849_X86_64): Likewise. (PREFIX_VEX_0F384B_X86_64): Likewise. (PREFIX_VEX_0F385C_X86_64): Likewise. (PREFIX_VEX_0F385E_X86_64): Likewise. (X86_64_VEX_0F3849): Likewise. (X86_64_VEX_0F384B): Likewise. (X86_64_VEX_0F385C): Likewise. (X86_64_VEX_0F385E): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise. (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F3849_X86_64_P_0): Likewise. (VEX_W_0F3849_X86_64_P_2): Likewise. (VEX_W_0F3849_X86_64_P_3): Likewise. (VEX_W_0F384B_X86_64_P_1): Likewise. (VEX_W_0F384B_X86_64_P_2): Likewise. (VEX_W_0F384B_X86_64_P_3): Likewise. (VEX_W_0F385C_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_0): Likewise. (VEX_W_0F385E_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_2): Likewise. (VEX_W_0F385E_X86_64_P_3): Likewise. (names_tmm): Likewise. (att_names_tmm): Likewise. (intel_operand_size): Handle void_mode. (OP_XMM): Handle tmm_mode. (OP_EX): Likewise. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (operand_type_shorthands): Add RegTMM. (operand_type_init): Likewise. (operand_types): Add Tmmword. (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. * i386-opc.h (CpuAMX_INT8): New. (CpuAMX_BF16): Likewise. (CpuAMX_TILE): Likewise. (SIBMEM): Likewise. (Tmmword): Likewise. (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile. (i386_opcode_modifier): Extend width of fields vexvvvv and sib. (i386_operand_type): Add tmmword. * i386-opc.tbl: Add AMX instructions. * i386-reg.tbl: Add AMX registers. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-07-10[readelf] Fix end_seq entry in -wL. Specifically stop the display of a line ↵Tom de Vries12-12/+12
number and is_statement/has-view fields for the End of Sequence operator, as these have no meaning. binutils* dwarf.c (display_debug_lines_decoded): Don't emit meaningless information in the end_sequence row. * testsuite/binutils-all/dw5.W: Update. * testsuite/binutils-all/objdump.WL: Update. gas * testsuite/gas/elf/dwarf2-11.d: Update expected output from readelf's line table decoding. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise. * testsuite/gas/elf/dwarf2-15.d: Likewise. * testsuite/gas/elf/dwarf2-16.d: Likewise. * testsuite/gas/elf/dwarf2-17.d: Likewise. * testsuite/gas/elf/dwarf2-18.d: Likewise. * testsuite/gas/elf/dwarf2-19.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/elf/dwarf2-6.d: Likewise. * testsuite/gas/elf/dwarf2-7.d: Likewise.
2020-07-09x86: Properly set YMM/ZMM featuresH.J. Lu7-0/+46
Since VEX/EVEX vector instructions will always update the full YMM/ZMM registers, set YMM/ZMM features for VEX/EVEX vector instructions. * config/tc-i386.c (output_insn): Set YMM/ZMM features for VEX/EVEX vector instructions. * testsuite/gas/i386/property-4.d: New file. * testsuite/gas/i386/property-4.s: Likewise. * testsuite/gas/i386/property-5.d: Likewise. * testsuite/gas/i386/property-5.s: Likewise. * testsuite/gas/i386/x86-64-property-4.d: Likewise. * testsuite/gas/i386/x86-64-property-5.d: Likewise.
2020-07-09Remove powerpc PE supportAlan Modra2-3/+1
Plus some leftover powerpc lynxos support. bfd/ * coff-ppc.c: Delete. * pe-ppc.c: Delete. * pei-ppc.c: Delete. * Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Remove PE PPC. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags): Remove PPCMAGIC code. (coff_write_object_contents): Remove PPC_PE code. * config.bfd: Move powerpcle-pe to removed targets. * configure.ac: Remove powerpc PE entries. * libcoff-in.h (ppc_allocate_toc_section): Delete. (ppc_process_before_allocation): Delete. * peXXigen.c: Remove POWERPC_LE_PE code and comments. * targets.c: Remove powerpc PE vectors. * po/SRC-POTFILES.in: Regenerate. * libcoff.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * dlltool.c: Remove powerpc PE support and comments. * configure.ac: Remove powerpc PE dlltool config. * configure: Regenerate. gas/ * config/obj-coff.h: Remove TE_PE support. * config/tc-ppc.c: Likewise. * config/tc-ppc.h: Likewise. * configure.tgt: Remove powerpc PE and powerpc lynxos. * testsuite/gas/cfi/cfi.exp (cfi-common-6): Remove powerpc PE condition. * testsuite/gas/macros/macros.exp: Don't xfail powerpc PE. include/ * coff/powerpc.h: Delete. ld/ * emulparams/ppcpe.sh: Delete. * scripttempl/ppcpe.sc: Delete. * emulparams/ppclynx.sh: Delete. * Makefile.am (ALL_EMULATION_SOURCES): Remove ppc PE and lynxos. * configure.tgt: Likewise. * emultempl/beos.em: Remove powerpc PE support. * emultempl/pe.em: Likewise. * po/BLD-POTFILES.in: Regenerate. * Makefile.in: Regenerate.
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich3-0/+104
Just like other VEX-encoded scalar insns do. Besides a testcase for this behavior also introduce one to verify that XOP scalar insns don't honor -mavxscalar=256, as they don't ignore XOP.L.
2020-07-07arc: Improve error messages when assemblingClaudiu Zissulescu5-12/+12
gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): Add error messages. * testsuite/gas/arc/add_s-err.s: Update test. * testsuite/gas/arc/asm-errors.err: Likewise. * testsuite/gas/arc/cpu-em-err.s: Likewise. * testsuite/gas/arc/hregs-err.s: Likewise. * testsuite/gas/arc/warn.s: Likewise.
2020-07-07arc: Update vector instructions.Claudiu Zissulescu1-2/+2
Update vadd2, vadd4h, vmac2h, vmpy2h, vsub4h vector instructions arguments to discriminate between double/single register operands. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_rbd): New function. (RBD): Define. (RBDdup): Likewise. * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update instructions. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2020-07-07Use is_xcoff_format in gas testsuiteAlan Modra3-5/+5
* testsuite/gas/all/gas.exp: Use is_xcoff_format. * testsuite/gas/ppc/ppc.exp: Likewise. * testsuite/gas/all/weakref1l.d: Likewise.
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