aboutsummaryrefslogtreecommitdiff
path: root/gas/testsuite
AgeCommit message (Expand)AuthorFilesLines
2022-07-09gas: arm -mwarn-syms duplicatesAlan Modra1-0/+1
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI13-32/+64
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI2-0/+12
2022-07-07RISC-V: Fix requirement handling on Zhinx+{D,Q}Tsukasa OI1-1/+1
2022-07-06x86: fix 3-operand insn reverse-matchingJan Beulich2-16/+15
2022-07-06x86: introduce a state stack for .archJan Beulich3-0/+78
2022-07-06x86: permit "default" with .archJan Beulich3-0/+34
2022-07-04gas/testsuite: properly exclude aout in all/weakref1uJan Beulich1-1/+1
2022-07-04x86-64: improve handling of branches to absolute addressesJan Beulich4-0/+47
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess6-56/+56
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI11-0/+111
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI11-0/+809
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI11-0/+511
2022-06-27drop XC16x bitsJan Beulich46-2169/+0
2022-06-22RISC-V: Reorder the prefixed extensions which are out of order.Nelson Chu6-15/+0
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu11-308/+352
2022-06-16Restore readelf -wFAlan Modra1-1/+1
2022-06-16PR29250, readelf erases CIE initial register stateAlan Modra3-1/+56
2022-06-03x86: exclude certain ISA extensions from v3/v4 ISAJan Beulich7-0/+36
2022-05-31Trailing spaces in objdump -r headerAlan Modra106-142/+142
2022-05-30Fix failing test for armeb-gnu-eabiLuis Machado1-18/+2
2022-05-30RISC-V: Add zhinx extension supports.jiawei2-0/+125
2022-05-27opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess203-1666/+1666
2022-05-27x86/Intel: allow MASM representation of embedded rounding / SAEJan Beulich10-1938/+1977
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich2-0/+46
2022-05-27x86/Intel: adjust representation of embedded rounding / SAEJan Beulich36-9924/+9924
2022-05-27x86/Intel: allow MASM representation of embedded broadcastJan Beulich22-4128/+4158
2022-05-27x86/Intel: adjust representation of embedded broadcastJan Beulich50-16765/+16765
2022-05-25RISC-V: Fix RV32Q conflictTsukasa OI7-3/+19
2022-05-25opcodes: introduce BC field; fix iselDmitry Selyutin4-4/+4
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen1-0/+36
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI3-0/+8
2022-05-19arm: Fix system register fpcxt_ns and fpcxt_s naming convention.Srinath Parvathaneni2-0/+77
2022-05-18arm: Add unwind support for mixed register listsVictor Do Nascimento3-9/+23
2022-05-18gas: avoid octal numbers being accepted when processing .linefileJan Beulich2-0/+4
2022-05-18gas: avoid bignum related errors when processing .linefileJan Beulich3-0/+12
2022-05-18gas: don't ignore .linefile inside false conditionalsJan Beulich3-0/+22
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu5-0/+180
2022-05-12Re: IBM zSystems: Accept (. - 0x100000000) PCRel32 operandsAlan Modra1-2/+2
2022-05-09IBM zSystems: Accept (. - 0x100000000) PCRel32 operandsIlya Leoshkevich5-1/+17
2022-04-27x86: Disable 2 tests with large memory requirementH.J. Lu1-1/+2
2022-04-27x86: VFPCLASSSH is Evex.LLIGJan Beulich5-0/+52
2022-04-20x86: reject all invalid SAE variantsJan Beulich2-0/+10
2022-04-20Revert "as: Reject unknown -gXXX option" testsuiteAlan Modra4-6/+0
2022-04-19as: Reject unknown -gXXX optionH.J. Lu4-0/+6
2022-04-19x86: don't mistake ordinary immediates for SAE / rounding controlJan Beulich2-3/+10
2022-04-19x86: VCMPSH is Evex.LLIGJan Beulich5-0/+61
2022-04-19x86/Intel: test non-legacy VCVT{,U}SI2SH insn formsJan Beulich2-6/+6
2022-04-19x86: correct and simplify NOP disassemblyJan Beulich3-43/+12
2022-04-12gas: further adjust file/line handling for .macroJan Beulich1-6/+6
generated by cgit v1.1 at 2025-01-09 17:00:05 +0000