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2021-04-13m68hc11 gas testsuite wartAlan Modra1-13/+9
Writing to a potentially read-only source directory is not good. * testsuite/gas/m68hc11/m68hc11.exp (gas_m68hc11_message): Don't write to $srcdir. Use gas_host_run and read output file rather than gas_start/gas_finish.
2021-04-12Power10 bignum operandsAlan Modra2-0/+29
When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux and other 32-bit powerpc targeted binutils fail to assemble some power10 prefixed instructions with 34-bit fields. A typical error seen when running the testsuite is .../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid In practice this doesn't matter for addresses: 32-bit programs don't need or use the top 2 bits of a d34 field when calculating addresses. However it may matter when loading or adding 64-bit constants with paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs. So this patch enables limited support for O_big PowerPC operands, and corrects sign extension of 32-bit constants using X_extrabit. * config/tc-ppc.c (insn_validate): Use uint64_t for operand values. (md_assemble): Likewise. Handle bignum operands. (ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer check. * expr.c: Delete unnecessary forward declarations. (generic_bignum_to_int32): Return uint32_t. (generic_bignum_to_int64): Return uint64_t. Compile always. (operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and clear X_extrabit for unary '!'. * expr.h (generic_bignum_to_int32): Declare. (generic_bignum_to_int64): Declare. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12RISC-V: Support to parse the multi-letter prefix in the architecture string.Nelson Chu22-23/+31
The original discussion is as follows, https://github.com/riscv/riscv-isa-manual/issues/637 I never considered the prefixes may have multiple letters, like zxm. But the ISA spec has been updated for a long time that I haven't noticed. This patch rewrites the part of architecture parser to support parsing the multi-letter prefixes. Besides, I also improve the parser to report errors in details. One of the most obvious improvement is - Do not parse the prefixed extensions according to the orders in the parse_config. If we do so, then we used to get "unexpected ISA string at end" errors, but the message is a little bit hard to know what is happening. I Remove the confused message, and let riscv_parse_prefixed_ext to report the details. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Moved forward. (riscv_std_s_ext_strtab): Likewise. (riscv_std_h_ext_strtab): Likewise. (riscv_std_zxm_ext_strtab): Added for the zxm prefix. (enum riscv_prefix_ext_class): Moved forward and renamed from riscv_isa_ext_class. Reorder them according to the parsing order, since the enum values are used to check the orders in the riscv_compare_subsets. (struct riscv_parse_prefix_config): Moved forward and renamed from riscv_parse_config_t. Also removed the ext_valid_p field, the related functions are replaced by riscv_valid_prefixed_ext. (parse_config): Moved forward and updated. The more letters of the prefix string, the more forward it must be defined. Otherwise, we will get the wrong mapping when using strncmp in riscv_get_prefix_class. (riscv_get_prefix_class): Moved forward. Support to parse the multi-letter prefix, like zxm. (riscv_known_prefixed_ext): New function, check if the prefixed extension is supported according to the right riscv_std_*_ext_strtab. (riscv_valid_prefixed_ext): New function, used to replace the riscv_ext_*_valid_p functions. (riscv_init_ext_order): Do not set the values for prefix keywords since they may have multiple letters for now. (riscv_compare_subsets): Set the order values of prefix keywords to negative numbers according to the riscv_prefix_ext_class. (riscv_parse_std_ext): Call riscv_get_prefix_class to see if we have parsed the prefixed extensions. (riscv_parse_prefixed_ext): Updated and removed the parameter config. Report error when the prefix is unknown. (riscv_parse_subset): Do not parse the prefixed extensions according to the orders in the parse_config. Remove the confused message and let riscv_parse_prefixed_ext to report the details. * elfxx-riscv.h (enum riscv_isa_ext_class): Moved to elfxx-riscv.c. (riscv_get_prefix_class): Removed to static. gas/ * testsuite/gas/riscv/march-fail-order-x-std.d: Renamed from march-fail-porder-x-std.d. * testsuite/gas/riscv/march-fail-order-z-std.d: Renamed from march-fail-porder-z-std.d. * testsuite/gas/riscv/march-fail-order-x-z.d: Renamed from march-fail-porder-x-z.d. * testsuite/gas/riscv/march-fail-order-zx-std.l: Added to replace march-fail-porder.l. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Updated. * testsuite/gas/riscv/march-fail-order-z.l: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h.d: Renamed from march-fail-single-char-h.d. * testsuite/gas/riscv/march-fail-single-prefix-s.d: Renamed from march-fail-single-char-s.d. * testsuite/gas/riscv/march-fail-single-prefix-x.d: Renamed from march-fail-single-char-x.d. * testsuite/gas/riscv/march-fail-single-prefix-z.d: Renamed from march-fail-single-char-z.d. * testsuite/gas/riscv/march-fail-single-prefix-zmx.d: Added. * testsuite/gas/riscv/march-fail-single-prefix.l: Added to replace march-fail-single-prefix.l. * testsuite/gas/riscv/march-fail-unknown-zxm.d: Added. * testsuite/gas/riscv/march-fail-unknown-std.l: Updated. * testsuite/gas/riscv/march-fail-unknown.l: Likewise.
2021-04-09AArch64: Fix Diagnostic messaging for LD/ST Exclusive.Tejas Belagod2-6/+7
A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' gas/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages for LD/ST Exclusive instructions. * testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP. * testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
2021-04-09PowerPC disassembly of pcrel referencesAlan Modra3-51/+51
This adds some annotation to Power10 pcrel instructions, displaying the target address (ie. pc + D34 field) plus a symbol if there is one at exactly that target address. pld from the .got or .plt will also look up the entry and display it, symbolically if there is a dynamic relocation on the entry. include/ * dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount. binutils/ * objdump.c (struct objdump_disasm_info): Delete dynrelbuf and dynrelcount. (find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move. (disassemble_section, disassemble_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Add "special". (POWERPC_DIALECT): Delete. Replace uses with.. (private_data): ..this. New inline function. (disassemble_init_powerpc): Init "special" names. (skip_optional_operands): Add is_pcrel arg, set when detecting R field of prefix instructions. (bsearch_reloc, print_got_plt): New functions. (print_insn_powerpc): For pcrel instructions, print target address and symbol if known, and decode plt and got loads too. gas/ * testsuite/gas/ppc/prefix-pcrel.d: Update expected output. * testsuite/gas/ppc/prefix-reloc.d: Likewise. * gas/testsuite/gas/ppc/vsx_32byte.d: Likewise. ld/ * testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output. * testsuite/ld-powerpc/inlinepcrel-2.d: Likewise. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pcrelopt.d: Likewise. * testsuite/ld-powerpc/startstop.d: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/weak1.d: Likewise. * testsuite/ld-powerpc/weak1so.d: Likewise.
2021-04-08PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra5-4/+155
Note that this doesn't implement the ISA to the letter regarding dcbtds (and dcbtstds), which says that the TH field may be zero. That doesn't make sense because allowing TH=0 would mean you no long have a dcbtds but rather a dcbtct instruction. I'm interpreting the ISA wording about allowing TH=0 to mean that the TH field of dcbtds is optional (in which case the TH value is 0b1000). opcodes/ PR 27676 * ppc-opc.c (DCBT_EO): Move earlier. (insert_thct, extract_thct, insert_thds, extract_thds): New functions. (powerpc_operands): Add THCT and THDS entries. (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. gas/ * testsuite/gas/ppc/pr27676.d, * testsuite/gas/ppc/pr27676.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/dcbt.d: Update. * testsuite/gas/ppc/power4_32.d: Update.
2021-04-07Fix pr27217 testcase failureAlan Modra1-3/+3
aarch64_be-linux-gnu_ilp32 +FAIL: PR27212 PR 27217 * testsuite/gas/aarch64/pr27217.d: Correct name. Accept ilp32 relocs.
2021-04-06Fix a problem assembling AArch64 sources when a relocation is generated ↵Nick Clifton2-0/+31
against a symbol that has a defined value. PR 27217 * config/tc-aarch64.c (my_get_expression): Rename to aarch64_get_expression. Add a fifth argument to enable deferring of expression resolution. (parse_typed_reg): Update calls to my_get_expression. (parse_vector_reg_list): Likewise. (parse_immediate_expression): Likewise. (parse_big_immediate): Likewise. (parse_shift): Likewise. (parse_shifter_operand_imm): Likewise. (parse_operands): Likewise. (parse_shifter_operand_reloc): Update calls to my_get_expression and call aarch64_force_reloc to determine the value of the new fifth argument. (parse_address_main): Likewise. (parse_half): Likewise. (parse_adrp): Likewise. (aarch64_force_reloc): New function. Contains code extracted from... (aarch64_force_relocation): ... here. * testsuite/gas/aarch64/pr27217.s: New test case. * testsuite/gas/aarch64/pr27217.d: New test driver.
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich3-2/+4
In commit 79dec6b7baa2 ("x86-64: optimize certain commutative VEX-encoded insns") I missed the fact that there being subtraction involved here doesn't matter, as absolute differences get summed up.
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich3-0/+25
While all of MMX, SSE, and SSE2 are included in "generic64", they can be individually disabled. There are two MOVQ forms lacking respective attributes. While the MMX one would get refused anyway (due to MMX registers not recognized with .nommx), the assembler did happily accept the SSE2 form. Add respective CPU settings to both, paralleling what the MOVD counterparts have.
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer2-0/+14
The code was checking wrong bit for sign extension. It caused it to zero-extend instead of sign-extend the immediate value. 2021-03-25 Abid Qadeer <abidh@codesourcery.com> opcodes/ * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of immediate in br.n instruction. gas/ * testsuite/gas/nios2/brn.s: New. * testsuite/gas/nios2/brn.d: New.
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich11-176/+73
For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich2-1/+5
This combination makes no sense and is documented to cause #UD.
2021-03-25x86: fix AMD Zen3 insnsJan Beulich6-23/+77
For INVLPGB the operand count was wrong (besides %edx there's also %ecx which is an input to the insn). In this case I see little sense in retaining the bogus 2-operand template. Plus swapping of the operands wasn't properly suppressed for Intel syntax. For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates were specified. These get retained, as the address operand is the only one really needed to expressed non-default address size, but only for compatibility reasons. Proper multi-operand insn get introduced and the testcases get adjusted / extended accordingly. While at it also drop the redundant definition of __amd64__ - we already have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
2021-03-25x86-64: limit breakage from gcc movdir64b et al workaroundJan Beulich14-33/+149
This is only a partial fix for PR/gas 27419, in that it limits the bad behavior of accepting mismatched operands to just x32 mode. The full fix would be to revert commits 27f134698ac5 and b3a3496f83a1, and to address the issue in gcc instead.
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra2-8/+8
opcodes/ PR 27647 * ppc-opc.c (XLOCB_MASK): Delete. (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using XLBH_MASK. (powerpc_opcodes): Accept a BH field on all extended forms of bclr, bclrl, bcctr, bcctrl, bctar, bctarl. gas/ PR 27647 * testsuite/gas/ppc/a2.d: Update expected output. * testsuite/gas/ppc/power8.d: Likewise.
2021-03-23x86: unbreak certain MPX insn operand formsJan Beulich2-18/+28
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") dropped the mandatory prefix bytes from legacy encoded insn templates, but failed to also adjust affected MPX-specific checks in two places. For the expressions to remain halfway readable, introduce local variables to hold current_templates->start.
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen4-0/+148
bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc. gas/ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc. (riscv_multi_subset_supports): Add INSN_CLASS_ZB*. * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext.d: Likewise. include/ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus5-0/+51
This patch adds few missing system registers to GAS: LORC_EL1, LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2. gas/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/illegal-sysreg-7.d: New test. * testsuite/gas/aarch64/illegal-sysreg-7.l: New test. * testsuite/gas/aarch64/illegal-sysreg-7.s: New test. * testsuite/gas/aarch64/sysreg-7.d: New test. * testsuite/gas/aarch64/sysreg-7.s: New test. opcodes/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich6-930/+930
Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich7-16/+2363
All encodings not used in this range are (reserved) NOPs. Hence their decoding should be fully consistent. For this to work the PREFIX_IGNORED logic needs slightly extending, such that the attribute will also - have an effect when used inside prefix_table[], yet without always falling back to using slot 0, - cause prefixes marked as ignored while decoding through prefix_table[] to no longer be considered decoded, when encountered in a subsequent decoding step. In adjacent code also drop meaningless PREFIX_OPCODE.
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich11-7/+21
Despite SYSEXIT being an Intel-only insn in long mode, its behavior there is similar to SYSRET's: Depending on REX.W execution continues in either 64-bit or compatibility mode. Hence distinguishing by suffix is as necessary here as it is there.
2021-02-26Correct an error message in the ARM assembler.Nick Clifton3-0/+22
PR 27411 * config/tc-arm.c (do_t_add_sub): Correct error message. * testsuite/gas/arm/pr27411.s: New test. * testsuite/gas/arm/pr27411.d: New test driver. * testsuite/gas/arm/pr27411.l: Expected error output for new test.
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2-19/+31
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-02-17h8300 complains about new section defined without attributesAlan Modra1-0/+1
* testsuite/gas/elf/section28.d: xfail h8300.
2021-02-16gas: Allow SHF_GNU_RETAIN on all sectionsH.J. Lu5-0/+43
Since SHF_GNU_RETAIN is allowed on all sections, strip SHF_GNU_RETAIN when checking incorrect section attributes. PR gas/27412 * config/obj-elf.c (obj_elf_change_section): Strip SHF_GNU_RETAIN when checking incorrect section attributes. * testsuite/gas/elf/elf.exp: Run section28 and section29. * testsuite/gas/elf/section28.d: New file. * testsuite/gas/elf/section28.s: Likewise. * testsuite/gas/elf/section29.d: Likewise. * testsuite/gas/elf/section29.s: Likewise.
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich14-93/+147
CVTPI2PD with a memory operand, unlike CVTPI2PS, doesn't engage MMX logic. Therefore it - has a proper AVX equivalent (CVTDQ2PD) and hence can be subject to SSE2AVX translation and SSE checking, - should not record MMX use in the respective ELF note.
2021-02-16x86: honor template rather than actual operands when updating i.xstateJan Beulich3-3/+3
This undoes a change to md_assemble() that 32930e4edbc0 ("x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker") did without any explanation. This broke a CVTPI2PS property test that a subsequent test will add, and the updates to existing tests also demonstrate what was wrong: For example, AVX insns update the full YMM, even if a Vex128 variant is in use.
2021-02-16x86: record register use for SIMD insns without respective explicit operandsJan Beulich7-0/+36
VZERO{ALL,UPPER} modify YMM registers despite having no operands. While {,V}{LD,ST}MXCSR don't modify XMM registers, MXCSR and XMMn collectively form underlying machine state.
2021-02-16x86: make common property tests commonJan Beulich10-108/+10
There's no need to run the exact same test twice. Move the tests which don't differ between 32- and 64-bit to the "Common tests" section.
2021-02-16x86: make 16-bit ENQCMD test actually test ENQCMDJan Beulich2-12/+17
2021-02-15IBM Z: Implement instruction set extensionsAndreas Krebbel3-0/+56
opcodes/ * s390-mkopc.c (main): Accept arch14 as cpu string. * s390-opc.txt: Add new arch14 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH14. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch14. * doc/c-s390.texi: Document arch14 march option. * testsuite/gas/s390/s390.exp: Run the arch14 related tests. * testsuite/gas/s390/zarch-arch14.d: New test. * testsuite/gas/s390/zarch-arch14.s: New test.
2021-02-12Change the readelf and objdump programs so that they will automatically ↵Nick Clifton2-2/+2
follow links to separate debug info files. * configure.ac (follow-debug-links): Add option to enable or disable the following of debug links by default. Set the default for the option to be 'follow'. * dwarf.c (do_follow_links): Initialise with DEFAULT_FOR_FOLLOW_LINKS. (dwarf_select_sections_by_names): Add no-follow-links option. (dwarf_select_sections_by_letter): Add 'N' option. * objdump.c (usage): Add conditional text describing the follow links option. (slurp_symtab): Ensure that there is a NULL entry at the end of the symbol table. (slurp_dynamic_symtab): Likewise. (dump_bfd): When extending the symbol table, ensure that there is still a NULL entry at the end. * readelf.c (usage): Add conditional text describing the follow links option. * doc/binutils.texi: Update documentation for objcopy and readelf. * doc/debug.options.texi: Update documentation of the follow-links option. * config.in: Regenerate. * configure: Regenerate. * testsuite/binutils-all/compress.exp: Add the -WN option to objdump command lines that are not expecting to follow links. * testsuite/binutils-all/readelf.exp: Add the --debug-dump=no-follow-links option to tests that are not expecting to follow debug links. gas * testsuite/gas/mach-o/sections-1.d: Stop automatic debug link following. * testsuite/gas/xgate/insns-dwarf2.d: Likewise. ld * testsuite/ld-elf/sec64k.exp: Stop readelf from automatically following debug links.
2021-02-12gas testsuite: adjust recently added tests for hppaAlan Modra5-12/+12
Some hppa gas targets treat anything starting in the first column as a label, so directives can't start there. Also, binutils_assemble and run_dump_test cleverly edit test source to suit the hppa .comm directive which has a different syntax to most targets. The editing means we can't match source file names in dumps. Finally, hppa gas complains if instructions are emitted without a ".text" or similar directive. * testsuite/gas/all/pr27381.err: Don't match source file name. * testsuite/gas/all/pr27381.s: Don't start directive in first column. * testsuite/gas/all/pr27384.err: Don't match source file name. Adjust line number. * testsuite/gas/all/pr27384.s: Add ".text" directive. * testsuite/gas/elf/pr27355.err: Don't match source file name.
2021-02-09Add a sanity check of files include by .incbin.Nick Clifton4-0/+8
PR 27381 * read.c (s_incbin): Check that the file to be included is a regular, non-directory file. * testsuite/gas/all/pr27381.s: New test source file. * testsuite/gas/all/pr27381.d: New test control file. * testsuite/gas/all/pr27381.err: Expected error output for the new test. * testsuite/gas/all/gas.exp: Run the new test.
2021-02-09Remove arm-symbianelfAlan Modra10-10/+10
* configure.ac: Delete arm*-*-symbianelf* entry. * configure: Regenerate. bfd/ * config.bfd (arm*-*-symbianelf*): Move from obsolete to removed. * configure.ac: Delete symbian entries. * elf-bfd.h (enum elf_target_os): Delete is_symbian. * elf32-arm.c: Remove symbian support. Formatting. * targets.c: Delete symbian entries. * configure: Regenerate. binutils/ * testsuite/lib/binutils-common.exp (supports_gnu_osabi): Remove symbianelf. gas/ * Makefile.am (TARG_ENV_HFILES): Remove config/te-symbian.h. * config/tc-arm.c (elf32_arm_target_format): Remove TE_SYMBIAN support. * config/te-symbian.h: Delete. * configure.tgt: Remove arm-*-symbianelf*. * testsuite/gas/arm/arch4t-eabi.d: Don't mention symbianelf in target selection. * testsuite/gas/arm/arch4t.d: Likewise. * testsuite/gas/arm/got_prel.d: Likewise. * testsuite/gas/arm/mapdir.d: Likewise. * testsuite/gas/arm/mapmisc.d: Likewise. * testsuite/gas/arm/mapsecs.d: Likewise. * testsuite/gas/arm/mapshort-eabi.d: Likewise. * testsuite/gas/arm/thumb-eabi.d: Likewise. * testsuite/gas/arm/thumb.d: Likewise. * testsuite/gas/arm/thumbrel.d: Likewise. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove earmsymbian.c. Don't include symbian dep file. * configure.tgt: Remove arm*-*-symbianelf* entry. * emulparams/armsymbian.sh: Delete. * ld.texi: Don't mention symbian. * scripttempl/armbpabi.sc: Delete. * testsuite/ld-arm/symbian-seg1.d: Delete. * testsuite/ld-arm/symbian-seg1.s: Delete. * testsuite/ld-arm/arm-elf.exp: Don't run symbian-seg1. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2021-02-09Prevent a bad .Psize expression from triggering a memory access violation.Nick Clifton4-0/+13
PR 27384 * listing.c (listing_psize): Check the result of the width expression before assigning it to paper_width. * testsuite/gas/all/pr27384.s: New test source file. * testsuite/gas/all/pr27384.d: New test control file. * testsuite/gas/all/pr27384.err: Expected errors from new test. * testsuite/gas/all/gas.exp: Run the new test.
2021-02-09Add a test for PR 27355 - where corrupt assembler .file directives could ↵Nick Clifton4-0/+13
trigger a segmentation fault. PR 27355 * testsuite/gas/elf/pr27355.s: New test source file. * testsuite/gas/elf/pr27355.d: New test control file. * testsuite/gas/elf/pr27355.err: Expected errors from new test. * testsuite/gas/elf/elf.exp: Run the new test.
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu3-150/+0
bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Removed INSN_CLASS_ZB*. * testsuite/gas/riscv/bitmanip-insns-32.d: Removed. * testsuite/gas/riscv/bitmanip-insns-64.d: Removed. * testsuite/gas/riscv/bitmanip-insns.s: Removed. include/ * opcode/riscv-opc.h: Removed macros for zb* extensions. * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (MASK_RVB_IMM): Removed. (riscv_opcodes): Removed zb* instructions. (riscv_ext_version_table): Removed versions for zb*.
2021-01-26nios2: Don't disable relaxation with --gdwarf-NH.J. Lu2-0/+30
GCC 11 passes --gdwarf-5 to assembler to enable DWARF5 debug info. Don't disable relaxation when --gdwarf-N is specified. The assembler generated debug information will treat the sequence of the relaxed instructions as a single instruction. PR gas/27243 * config/tc-nios2.c (md_begin): Don't disable relaxation with --gdwarf-N. * testsuite/gas/nios2/relax.d: New file. * testsuite/gas/nios2/relax.s: Likewise.
2021-01-26gas testsuite tidyAlan Modra28-31/+32
This replaces skip and notarget in a number of gas tests with xfail, the idea being that running tests might expose segmentation faults or other serious errors even when we don't expect a test to pass. Doing so showed a number of cases where tests now pass, which is another reason to avoid profligate use of notarget and skip. * testsuite/gas/all/local-label-overflow.d: Use xfail rather than notarget all except hppa. Comment. * testsuite/gas/all/sleb128-2.d: Use xfail rather than notarget. * testsuite/gas/all/sleb128-4.d: Likewise. Don't skip msp430. * testsuite/gas/all/sleb128-5.d: Use xfail rather than notarget. * testsuite/gas/all/sleb128-7.d: Likewise. * testsuite/gas/all/sleb128-9.d: Likewise. * testsuite/gas/elf/bignums.d: Likewise. * testsuite/gas/elf/group0c.d: Likewise. * testsuite/gas/elf/group1a.d: Likewise. * testsuite/gas/elf/section-symbol-redef.d: Likewise. * testsuite/gas/elf/section15.d: Likewise. * testsuite/gas/elf/section4.d: Likewise. * testsuite/gas/elf/section7.d: Likewise. * testsuite/gas/macros/irp.d: Likewise. * testsuite/gas/macros/repeat.d: Likewise. * testsuite/gas/macros/rept.d: Likewise. * testsuite/gas/macros/test2.d: Likewise. * testsuite/gas/macros/vararg.d: Likewise. * testsuite/gas/all/string.d: Use xfail rather than skip. * testsuite/gas/elf/missing-build-notes.d: Likewise. * testsuite/gas/elf/section0.d: Likewise. * testsuite/gas/elf/section1.d: Likewise. * testsuite/gas/elf/section10.d: Likewise. * testsuite/gas/elf/section11.d: Likewise. * testsuite/gas/elf/section6.d: Likewise. * testsuite/gas/elf/symtab.d: Use xfail rather than skip, adjust hppa. * testsuite/gas/elf/symtab.s: Don't start directives in first column. * testsuite/gas/macros/test3.d: Don't notarget nds32.
2021-01-26gas byte testAlan Modra4-14/+0
skip *-*-* is a little silly, delete the test. * testsuite/gas/all/byte.d, * testsuite/gas/all/byte.l, * testsuite/gas/all/byte.s: Delete. * testsuite/gas/all/gas.exp: Don't run byte test.
2021-01-26pr27228 testcaseAlan Modra2-2/+4
This failed on ft32, hppa, and mips-irix targets. In the case of ft32 the problem was iterating over an array in reverse and not using the proper condition, so BFD_RELOC_NONE was not recognised. bfd/ * elf32-ft32.c (ft32_reloc_type_lookup): Don't miss ft32_reloc_map[0]. gas/ PR 27282 * testsuite/gas/all/none.d: Replace skip with xfail, don't xfail ft32. * testsuite/gas/elf/pr27228.d: xfail hppa and allow OBJECT match.
2021-01-24gas: Add a testcase for PR gas/27228H.J. Lu3-0/+14
PR gas/27228 * testsuite/gas/elf/elf.exp: Run pr27228. * testsuite/gas/elf/pr27228.d: New file. * testsuite/gas/elf/pr27228.s: Likewise.
2021-01-21PR27221, 058430b4a1 warnings while assembling the Linux kernelAlan Modra4-20/+0
PR 27221 * dwarf2dbg.c (dwarf2_gen_line_info_1): Don't warn about ignored line number info when gas is generating it. * testsuite/gas/elf/dwarf2-20.d: Adjust to not expect warnings. * testsuite/gas/m68hc11/indexed12.d: Likewise. * testsuite/gas/elf/elf.exp: Don't run warn-2. * gas/testsuite/gas/elf/warn-2.s: Delete.
2021-01-20PowerPC: Don't generate unused section symbolsAlan Modra3-3/+0
PowerPC version of git commit d1bcae833b. bfd/ * elf32-ppc.c: Delete outdated comment. (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): Define. * elf64-ppc.c (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): Define. gas/ * testsuite/gas/ppc/power4.d: Adjust for removal of section sym. * testsuite/gas/ppc/test1elf32.d: Likewise. * testsuite/gas/ppc/test1elf64.d: Likewise. ld/ * testsuite/ld-powerpc/relbrlt.s: Make symbols global. * testsuite/ld-powerpc/relbrlt.d: Adjust to suit. * testsuite/ld-powerpc/tlsget.d: Adjust for reordered stubs. * testsuite/ld-powerpc/tlsget.wf: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsget2.wf: Likewise. * testsuite/ld-powerpc/tlsexe.r: Adjust for removed section syms. * testsuite/ld-powerpc/tlsexe32.r: Likewise. * testsuite/ld-powerpc/tlsexe32no.r: Likewise. * testsuite/ld-powerpc/tlsexeno.r: Likewise. * testsuite/ld-powerpc/tlsexenors.r: Likewise. * testsuite/ld-powerpc/tlsexers.r: Likewise. * testsuite/ld-powerpc/tlsexetoc.r: Likewise. * testsuite/ld-powerpc/tlsexetocrs.r: Likewise. * testsuite/ld-powerpc/tlsso.r: Likewise. * testsuite/ld-powerpc/tlsso32.r: Likewise. * testsuite/ld-powerpc/tlstocso.r: Likewise.
2021-01-18as: Automatically enable DWARF5 supportH.J. Lu2-3/+1
Currently $ as -o x.o x.s fails when x.s contains DWARF5 ".file 0" or ".loc 0" directives. Update assembler to automatically enable DWARF5 support so that $ gcc -S -g -c x.c $ gcc -c x.s works. PR gas/27195 * dwarf2dbg.c (dwarf2_gen_line_info): Set dwarf_level to 5 if needed. (dwarf2_directive_filename): Likewise. (dwarf2_directive_loc): Likewise. * testsuite/gas/elf/dwarf-5-file0.d: Pass --gdwarf-3. * testsuite/gas/lns/lns-diag-1.l: Remove the "Error: file number less than one" errors.
2021-01-18PR27198, segv in S_IS_WEAKAlan Modra4-0/+9
Fix a NULL dereference seen when assembling invalid input. PR 27198 * config/tc-i386.c (need_plt32_p): Return FALSE for NULL symbol. * testsuite/gas/i386/pr27198.d, * gas/testsuite/gas/i386/pr27198.err, * gas/testsuite/gas/i386/pr27198.s: New test. * gas/testsuite/gas/i386/i386.exp: Run it.
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu7-234/+234
Error and warning messages usually starting with lower case letter, and without the period at the end. Besides, add the prefixed "internel:" at the beginning of the messages when they are caused internally. Also fix indents and typos. bfd/ * elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages. gas/ * config/tc-riscv.c: Error and warning messages tidy. * testsuite/gas/riscv/priv-reg-fail-fext.l: Updated. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. opcodes/ * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
2021-01-13x86: Don't generate GOT_symbol for PLT relocationsH.J. Lu5-0/+48
Don't generate the _GLOBAL_OFFSET_TABLE_ symbol for PLT relocations since it isn't needed. PR gas/27178 * config/tc-i386.c (lex_got::gotrel): Add need_GOT_symbol. Don't generate GOT_symbol for PLT relocations. * testsuite/gas/i386/i386.exp: Run PR gas/27178 tests. * testsuite/gas/i386/no-got.d: New file. * testsuite/gas/i386/no-got.s: Likewise. * testsuite/gas/i386/x86-64-no-got.d: Likewise. * testsuite/gas/i386/x86-64-no-got.s: Likewise.
generated by cgit v1.1 at 2024-12-21 08:45:13 +0000