aboutsummaryrefslogtreecommitdiff
path: root/gas/testsuite
AgeCommit message (Expand)AuthorFilesLines
2021-12-09RISC-V: Clarify the behavior of .option arch directive.Nelson Chu8-9/+13
2021-12-02aarch64: Add BC instructionRichard Sandiford5-0/+86
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford3-0/+174
2021-12-02aarch64: Add support for +mopsRichard Sandiford5-0/+1557
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford5-0/+46
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford5-0/+8
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford2-0/+7
2021-12-02aarch64: Provide line info for unclosed sequencesRichard Sandiford3-3/+3
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford9-39/+66
2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford10-6/+877
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford4-1/+13
2021-11-30aarch64: Remove ZIDR_EL1Richard Sandiford3-7/+0
2021-11-30aarch64: Allow writes to MFAR_EL3Richard Sandiford5-20/+13
2021-11-30aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford5-3/+8
2021-11-30aarch64: Remove duplicate system register entriesRichard Sandiford2-4/+0
2021-11-30aarch64: Check for register aliases before mnemonicsRichard Sandiford5-1/+9
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2-0/+13
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2-68/+28
2021-11-29PR28629 NIOS2 falloutAlan Modra1-1/+1
2021-11-26gas: Update commit 4780e5e4933H.J. Lu1-1/+1
2021-11-26[gas] Fix file 0 dir with -gdwarf-5Tom de Vries1-1/+1
2021-11-22RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu15-18/+18
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu10-0/+80
2021-11-19Re: Add multibyte character warning option to the assembler.Alan Modra1-10/+10
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu4-0/+42
2021-11-18Add multibyte character warning option to the assembler.Nick Clifton6-0/+30
2021-11-18RISC-V: Add testcases for z[fdq]inxjiawei6-0/+222
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus5-0/+270
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus5-0/+61
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus5-0/+74
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus15-0/+694
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus5-0/+230
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus14-0/+357
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus9-0/+746
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu18-3/+3884
2021-11-16x86: Don't allow KMOV in TLS code sequencesH.J. Lu5-0/+16
2021-11-16RISC-V: Scalar crypto instruction and entropy source CSR testcases.jiawei41-3/+490
2021-11-15Deal with full path in .file 0 directiveEric Botcazou5-4/+130
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu3-5/+5
2021-11-10arm: enable Cortex-A710 CPUPrzemyslaw Wirkus1-0/+6
2021-11-10PR 28447: implement multiple parameters for .file on XCOFFClément Chigot4-0/+30
2021-11-02ARM: match armeb output for unwind-pacbti-m testAlan Modra1-3/+3
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus2-1/+18
2021-10-29Re: arm: add unwinder encoding support for PACBTIAlan Modra3-0/+59
2021-10-28ARM assembler: Allow up to 32 single precision registers in the VPUSH and VPO...Markus Klein2-0/+9
2021-10-25x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu3-12/+69
2021-10-24LoongArch gas supportliuzhensong24-1/+1973
2021-10-22x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu4-0/+62
2021-10-14Re: s12z/disassembler: call memory_error_func when appropriateAlan Modra1-1/+2
2021-10-07RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich4-0/+26
generated by cgit v1.1 at 2025-03-04 23:15:59 +0000