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AgeCommit message (Expand)AuthorFilesLines
2020-06-08x86: also allow %st(N) in CFI directivesJan Beulich1-0/+1
2020-06-08x86: restrict use of register aliasesJan Beulich5-0/+41
2020-06-05RISC-V: Don't generate the ELF privilege attributes when no CSR are used.Nelson Chu14-30/+24
2020-06-04tcl global directive outside proc body does nothing (gas)Alan Modra6-7/+0
2020-06-02gas: Fix checking for backwards .org with negative offsetAlex Coplan6-0/+14
2020-05-28Fix all unexpected failures in gas testsuite for pdp11-aout.Stephen Casner4-3/+110
2020-05-27Fix PR gas/26001 (pdp11-*-*)Stephen Casner3-0/+22
2020-05-26gas: Adjust x86 tests for PECOFFH.J. Lu3-1/+5
2020-05-26S/390: z13: Accept vector alignment hintsStefan Schulze Frielinghaus2-8/+16
2020-05-21Replace "if (x) free (x)" with "free (x)", gasAlan Modra1-4/+2
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu35-333/+1377
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner4-0/+82
2020-05-19Fix the ARM assembler to generate a Realtime profile for armv8-r.Alexander Fedotov4-4/+4
2020-05-18Don't handle lret/iret when -mlfence-before-ret=[or|not|shl|yes] since they a...liuhongt12-167/+1
2020-05-15Fix tight loop on recursively-defined symbolsAlan Modra4-0/+20
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra3-0/+23
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra3-0/+28
2020-05-11Power10 test lsb by byte operationAlan Modra3-0/+28
2020-05-11Power10 string operationsAlan Modra3-0/+33
2020-05-11Power10 Set boolean extensionPeter Bergner3-0/+21
2020-05-11Power10 bit manipulation operationsAlan Modra3-0/+38
2020-05-11Power10 VSX PCV generate operationsAlan Modra3-0/+21
2020-05-11Power10 VSX Mask Manipulation OperationsAlan Modra3-0/+53
2020-05-11Power10 Reduced precision outer product operationsAlan Modra5-0/+185
2020-05-11Power10 SIMD permute class operationsAlan Modra3-0/+91
2020-05-11Power10 128-bit binary integer operationsAlan Modra3-0/+77
2020-05-11Power10 VSX 32-byte storage accessAlan Modra3-0/+51
2020-05-11Power10 vector integer multiply, divide, modulo insnsAlan Modra3-0/+47
2020-05-11Power10 byte reverse instructionsPeter Bergner3-0/+19
2020-05-11Power10 Copy/Paste ExtensionsPeter Bergner2-0/+6
2020-05-11Power10 Add new L operand to the slbiag instructionPeter Bergner3-0/+19
2020-05-11PowerPC Rename powerxx to power10Alan Modra3-8/+8
2020-05-05Restore readelf's warnings that describe real problems with the file being ex...Nick Clifton1-2/+2
2020-05-04gas: PR 25863: Fix scalar vmul inside it block when assembling for MVEAndre Simoes Dias Vieira2-0/+16
2020-05-04Fix an illegal memory access in the assembler when generating a DWARF5 file/d...Nick Clifton3-0/+14
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan5-0/+27
2020-04-29Update expected disassembly after recent update.Nick Clifton1-1/+1
2020-04-29Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ...Nick Clifton2-0/+4
2020-04-27x86: Add i386 PE big-object supportTamar Christina2-3/+2
2020-04-26Improve -mlfence-after-loadliuhongt18-4/+455
2020-04-22xtensa: fix PR ld/25861Max Filippov1-1/+1
2020-04-22.symver fixesAlan Modra3-8/+3
2020-04-21symver11.s: Add ".balign 8"H.J. Lu1-0/+1
2020-04-21Disallow PC relative for CMPI on MC68000/10Andreas Schwab3-0/+33
2020-04-21BFD: Exclude sections with no content from compress check.Tamar Christina2-0/+19
2020-04-21gas: Extend .symver directiveH.J. Lu24-8/+172
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das3-7/+15
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das5-16/+1
2020-04-16Stop the MIPS assembler from accepting ifunc symbols.Nick Clifton2-3/+4
2020-04-16cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust3-0/+57
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