aboutsummaryrefslogtreecommitdiff
path: root/gas/testsuite/ChangeLog
AgeCommit message (Collapse)AuthorFilesLines
2016-09-21Fix misplaced ChangeLogRichard Sandiford1-11/+0
2016-09-21[AArch64][SVE 32/32] Add SVE testsRichard Sandiford1-0/+11
This patch adds new tests for SVE. It also extends diagnostic.[sl] with checks for some inappropriate uses of MUL and MUL VL in base AArch64 instructions. gas/testsuite/ * gas/aarch64/diagnostic.s, gas/aarch64/diagnostic.l: Add tests for invalid uses of MUL VL and MUL in base AArch64 instructions. * gas/aarch64/sve-add.s, gas/aarch64/sve-add.d, gas/aarch64/sve-dup.s, gas/aarch64/sve-dup.d, gas/aarch64/sve-invalid.s, gas/aarch64/sve-invalid.d, gas/aarch64/sve-invalid.l, gas/aarch64/sve-reg-diagnostic.s, gas/aarch64/sve-reg-diagnostic.d, gas/aarch64/sve-reg-diagnostic.l, gas/aarch64/sve.s, gas/aarch64/sve.d: New tests.
2016-05-11Skip new ARM security extension tests on non-ELF based targets.Nick Clifton1-25/+0
* testsuite/gas/arm/archv8m-cmse-base.d: Skip for non-ELF ARM targets. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-0/+25
This patch enables Intel RDPID instruction described in Intel64 and IA-32 Architectures Software Developer's Manual, April 2016. gas/ * config/tc-i386.c (cpu_arch): Add RDPID. * doc/c-i386.texi: Document RDPID. gas/testsuite/ * gas/i386/i386.exp: Run RDPID tests. * gas/i386/prefix.d: Adjust. * gas/i386/rdpid.s: New test. * gas/i386/rdpid.d: Ditto. * gas/i386/rdpid-intel.d: Ditto. * gas/i386/x86-64-rdpid.s: Ditto. * gas/i386/x86-64-rdpid.d: Ditto. * gas/i386/x86-64-rdpid-intel.d: Ditto. opcodes/ * i386-dis.c (prefix_table): Add RDPID instruction. * i386-gen.c (cpu_flag_init): Add RDPID flag. (cpu_flags): Add RDPID bitfield. * i386-opc.h (enum): Add RDPID element. (i386_cpu_flags): Add RDPID field. * i386-opc.tbl: Add RDPID instruction. * i386-init.h: Regenerate. * i386-tbl.h: Regenerate.
2016-03-17testsuite/ChangeLog is no longer supposed to existAlan Modra1-13/+0
move entries to main ChangeLog
2016-03-10PR gas/19744: Thumb-1 pcrop relocations don't work on Thumb-2 targetsMickael Guene1-0/+8
gas/ * config/tc-arm.c (do_arit): Protect against bad relocations usage. (do_mov): Likewise. (do_t_add_sub): Allow pcrop relocations for Thumb-2 targets. (do_t_mov_cmp): Likewise. (do_t_add_sub): Protect against bad relocations usage. (do_t_mov_cmp): Likewise. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local-armv7-m.s: New. * gas/arm/adds-thumb1-reloc-local-armv7-m.d: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.s: New. * gas/arm/movs-thumb1-reloc-local-armv7-m.d: New. ld/ * testsuite/ld-arm/arm-elf.exp: New tests. * testsuite/ld-arm/thumb1-adds-armv7-m.s: New. * testsuite/ld-arm/thumb1-movs-armv7-m.s: New.
2016-02-16[ARC] Enable .cfi_* pseudo-ops.Claudiu Zissulescu1-0/+5
gas/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (tc_arc_frame_initial_instructions): New function. (tc_arc_regname_to_dw2regnum): Likewise. * config/tc-arc.h (TARGET_USE_CFIPOP): Define (tc_cfi_frame_initial_instructions): Likewise. (tc_regname_to_dw2regnum): Likewise. gas/testsuite 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * gas/cfi/cfi-arc-1.d: New file. * gas/cfi/cfi-arc-1.s: Likewise. * gas/cfi/cfi.exp: Allow running tests for arc. binutils/ 2016-02-16 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (is_32bit_pcrel_reloc): Add R_ARC_32_PCREL.
2016-01-01binutils ChangeLog rotationAlan Modra1-1709/+0
2015-12-30Fix assorted ChangeLog errorsAlan Modra1-8/+13
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme1-0/+7
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards to merging with ARMv8-M Baseline. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch value. gas/ * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions shared between ARMv6T2 and ARMv8-M. (move_or_literal_pool): Check mov.w/mvn and movw availability against arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking arm_arch_t2. (do_t_branch): Error out for wide conditional branch instructions if targetting ARMv8-M Baseline. (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions in ARMv8-M Baseline. (wide_insn_ok): New function. (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and adapt error message for unsupported wide instruction to ARMv8-M Baseline. (insns): Reorganize instructions shared by ARMv8-M Baseline and ARMv6t2 architecture. (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and marvell-whitney cores. (arm_archs): Define armv8-m.base architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version. (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well. gas/testsuite/ * gas/arm/archv8m-base.d: New file. * gas/arm/attr-march-armv8m.base.d: Likewise. * gas/arm/armv8m.base-idiv.d: Likewise. * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare. include/opcode/ * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. (ARM_AEXT2_V8A): New architecture extension bitfield. (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_AEXT_V8M_BASE): New architecture extension bitfield. (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension bitfield. (ARM_ARCH_V6KT2): Likewise. (ARM_ARCH_V6ZT2): Likewise. (ARM_ARCH_V6KZT2): Likewise. (ARM_ARCH_V7): Likewise. (ARM_ARCH_V7A): Likewise. (ARM_ARCH_V7VE): Likewise. (ARM_ARCH_V7R): Likewise. (ARM_ARCH_V7M): Likewise. (ARM_ARCH_V7EM): Likewise. (ARM_ARCH_V8A): Likewise. (ARM_ARCH_V8M_BASE): New architecture bitfield. (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension bitfield and reindent. (ARM_ARCH_V7A_MP_SEC): Likewise. (ARM_ARCH_V7R_IDIV): Likewise. (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme1-0/+8
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in comb array. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch value. (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use value. gas/ * config/tc-arm.c (arm_ext_m): Include ARMv8-M. (arm_ext_v8m): New feature for ARMv8-M. (arm_ext_atomics): New feature for ARMv8 atomics. (do_tt): New encoding function for TT* instructions. (insns): Add new entries for ARMv8-M specific instructions and reorganize the ones shared by ARMv8-M Mainline and ARMv8-A. (arm_archs): Define armv8-m.main architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and clarify the ordering rule. (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile to 'A' if extension bit for atomic instructions is set, unless it is ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0 for ARMv8-M Mainline. gas/testsuite/ * gas/arm/archv8m.s: New file. * gas/arm/archv8m-main.d: Likewise. * gas/arm/attr-march-armv8m.main.d: Likewise. * gas/arm/any-armv8m.s: Likewise. * gas/arm/any-armv8m.d: Likewise. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare. (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN. (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15. include/opcode/ * arm.h (ARM_EXT2_ATOMICS): New extension bit. (ARM_EXT2_V8M): Likewise. (ARM_EXT_V8): Adjust comment with regards to atomics and remove mention of legacy use for that bit. (ARM_AEXT2_V8_1A): New architecture extension bitfield. (ARM_AEXT2_V8_2A): Likewise. (ARM_AEXT_V8M_MAIN): Likewise. (ARM_AEXT2_V8M): Likewise. (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield. (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A. (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A. (ARM_ARCH_V8M_MAIN): New architecture feature bitfield. (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield and reindent. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of feature bits. (ARM_ARCH_V8_1A_SIMD): Likewise. (ARM_ARCH_V8_1A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of ARM_EXT_V8. (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24Add tests for gas arch autodetection on ARMThomas Preud'homme1-0/+25
2015-12-09 Andre Vieira <andre.simoesdiasvieira@arm.com> gas/testsuite/ * gas/arm/automatic-bw.d: New. * gas/arm/automatic-bw.s: New. * gas/arm/automatic-cbz.d: New. * gas/arm/automatic-cbz.s: New. * gas/arm/automatic-clrex.d: New. * gas/arm/automatic-clrex.s: New. * gas/arm/automatic-lda.d: New. * gas/arm/automatic-lda.s: New. * gas/arm/automatic-ldaex.d: New. * gas/arm/automatic-ldaex.s: New. * gas/arm/automatic-ldaexb.d: New. * gas/arm/automatic-ldaexb.s: New. * gas/arm/automatic-ldrex.d: New. * gas/arm/automatic-ldrex.s: New. * gas/arm/automatic-ldrexd.d: New. * gas/arm/automatic-ldrexd.s: New. * gas/arm/automatic-movw.d: New. * gas/arm/automatic-movw.s: New. * gas/arm/automatic-sdiv.d: New. * gas/arm/automatic-sdiv.s: New. * gas/arm/automatic-strexb.d: New. * gas/arm/automatic-strexb.s: New.
2015-12-17Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:Christophe Lyon1-0/+7
2015-12-16 Mickael Guene <mickael.guene@st.com> bfd/ * bfd-in2.h: Regenerate. * reloc.c: Add new relocations. * libbfd.h (bfd_reloc_code_real_names): Add new relocations display names. * elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new relocations. (elf32_arm_reloc_map): Add bfd/arm mapping for new relocations. (elf32_arm_final_link_relocate): Implement new relocations resolution. gas/ * doc/c-arm.texi: Add documentation about new directives * config/tc-arm.c (group_reloc_table): Add mapping between gas syntax and new relocations. (do_t_add_sub): Keep new relocations for add operand. (do_t_mov_cmp): Keep new relocations for mov operand. (insns): Use 'shifter operand with possible group relocation' operand parse code for movs operand. (md_apply_fix): Implement mov and add encoding when new relocations on them. (tc_gen_reloc): Add new relocations. (arm_fix_adjustable): Since offset has a limited range ([0:255]) we disable adjust_reloc_syms() for new relocations. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local.d: New * gas/arm/adds-thumb1-reloc-local.s: New * gas/arm/movs-thumb1-reloc-local.d: New * gas/arm/movs-thumb1-reloc-local.s: New include/ * elf/arm.h: Add new arm relocations. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests_common): Add new relocations tests. * ld-arm/thumb1-adds.d: New * ld-arm/thumb1-adds.s: New * ld-arm/thumb1-movs.d: New * ld-arm/thumb1-movs.s: New
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato1-0/+65
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate ↵Matthew Wahab1-0/+6
instructions. ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Scalar Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Hd>, <Hs>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift by immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD scalar shift by immediate group. Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab1-0/+9
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The new instructions legal make some uses of the 4h vector type that had been invalid. This patch adjusts a test that checks for these uses. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, #<imm> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace tests for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_VSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD shift by immediate group. Change-Id: I3480f63883d54db46562573185da6982f2365ee8
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab1-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Scalar Pairwise, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar Pairwise instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_PAIR_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp, fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group. Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab1-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds an FP16 instruction to the group Adv.SIMD Modified Immediate, making it available when +simd+fp16 is enabled. The instruction added is: FMOV. The form of this instructions is <OP> <Hd>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SIMD_IMM_H): New. (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD modified immediate group. Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab1-0/+8
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Across Lanes, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV. The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. The new instructions valid make uses of the 8H and 4H that were previously illegal. The patch adjusts a test for illegal uses of vector types to take this into account. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace test for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_XLANES_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv, fminnmv, fminv to the Adv.SIMD across lanes group. Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab1-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <Hd>, <Hs>, <V>.h[<idx>] gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the scalar indexed element group. Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab1-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <V>.<T>, <V>.<T>, <V>.h[<idx>] where T is 4h or 8h gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_ELEMENT_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the vector indexed element group. Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab1-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX. The general form for these instructions is <OP> <Hd>, <Hs> or <OP> <Hd>, <Hs>, #0.0 Tested the series for aarch64-none-linux-gnu with cross-compiled check-binutils and check-gas. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_FCMP_H_0): new. (QL_S_2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe, frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu, fcvtzu and frsqrte to the scalar two register misc. group. Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab1-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS, FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of frintn, frintm, fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp, frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte and fsqrt to the vector register misc. group. Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab1-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FRECPS and FRSQRTS. The general form for these instructions is <OP> <Hd>, <Hs>, <Hm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt to the scalar three same group. Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab1-0/+5
ARMv8.2 adds 16-bit floating point operations as an optional extension to floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA, FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: New. * gas/aarch64/advsimd-fp16.s: New. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V3SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd, fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts, fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd, fcmgt, facgt and fminp to the vector three same group. Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-12Fix SH gas testsuite invalid assembly exposed by ec9ab52cAlan Modra1-0/+5
* gas/sh/tlsd.s: Use .tdata not .tbss. * gas/sh/tlsnopic.s: Likewise.
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab1-0/+7
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds the instruction to binutils as a HINT alias that takes an operand. A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the operand to PSB. A parser for the operand type is added to the assembler and a printer to the disassembler. The operand name "csync" is added to the list of HINT options with HINT number #17. Encoding and decoding of the operand is handled by the ins_hint/ext_hint functions added in the preceding patches. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_hint_opt_hsh): New. (parse_barrier_psb): New. (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB. (md_begin): Set up aarch64_hint_opt_hsh. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: Enable the statistical profiling extension. Update the expected output. * gas/aarch64/system-2.s: Add tests for PSB CSYNC. * gas/aarch64/system.d: Update the expected output. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): Add "csync". (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_feature_stat_profile): New. (STAT_PROFILE): New. (aarch64_opcode_table): Add "psb". (AARCH64_OPERANDS): Add "BARRIER_PSB". Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.Matthew Wahab1-0/+7
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers. This patch adds the registers to binutils, making them available when the architecture extension "+profile" is enabled. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1, pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1, pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and pmscr_el2. (aarch64_sys_reg_supported_p): Add architecture feature tests for the new registers. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.s: Add tests for the statistical profiling system registers. * gas/aarch64/sysreg-2.d: Enable the statistical profiling extension and update the expected output. Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb
2015-12-10[Aarch64] Support ARMv8.2 AT instructionsMatthew Wahab1-0/+6
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This patch adds support for the instructions, making them available when -march=armv8.2-a is selected. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and AT S1E1WP. * gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp". (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register feature test for "s1e1rp" and "s1e1wp". Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab1-0/+5
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support for the instruction to binutils, enabled when -march=armv8.2-a is selected. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_sys_ins_reg): Add check of architectural support for system register. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for dc instruction. * gas/aarch64/sysreg-2.s: Add uses of dc instruction. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". (aarch64_sys_ins_reg_supported_p): New. Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.Matthew Wahab1-0/+6
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for this bit to binutils, following the same basic pattern as for PSTATE.PAN. The new control bit is only available when -march=armv8.2-a is specified. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/uao-directive.d: New. * gas/aarch64/uao.d: New. * gas/aarch64/uao.s: New. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "uao". (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao". (aarch64_pstatefields): Add "uao". (aarch64_pstatefield_supported_p): Add checks for "uao". Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
2015-12-10[AArch64][PATCH 2/2] Add RAS system registers.Matthew Wahab1-0/+6
The ARMv8.2 RAS extension adds a number of new registers. This patch adds the registers and makes them available whenever the RAS extension is enabled, as it is when -march=armv8.2-a is selected. The new registers are: erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1, erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and vdisr_el2. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for new registers. * gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with tabs. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1", "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1", "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2". (aarch64_sys_reg_supported_p): Add architecture feature tests for new registers. Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab1-0/+6
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias and the preferred form of HINT 16. This patch adds an architectural feature flag for the RAS extension and includes it in the features selected enabled by -march=armv8.2-a. It also adds the ESB instruction, making it available whenever the RAS feature is enabled. Because ESB is the preferred form and because the target architecture isn't available to the disassembler, HINT 16 will be disassembled as ESB even when the target has no support for the RAS extension. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: New. * gas/aarch64/system-2.s: New. * gas/aarch64/system.d: Adjust expected output for HINT 16. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_RAS): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-tbl.h (aarch64_feature_ras): New. (RAS): New. (aarch64_opcode_table): Add "esb". Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-0/+7
This patch implements Intel OSPKE instructions documented in Intel64 and IA-32 Architectures Software Developer’s Manual Volume 2, September 2015. gas/testsuite/ * gas/i386/i386.exp: Run ospke and x86-64-ospke. * gas/i386/ospke.d: New file. * gas/i386/ospke.s: Likewise. * gas/i386/x86-64-ospke.d: Likewise. opcodes/ * i386-dis.c (MOD_0F01_REG_5): New. (RM_0F01_REG_5): Likewise. (reg_table): Use MOD_0F01_REG_5. (mod_table): Add MOD_0F01_REG_5. (rm_table): Add RM_0F01_REG_5. * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS. (cpu_flags): Add CpuOSPKE. * i386-opc.h (CpuOSPKE): New. (i386_cpu_flags): Add cpuospke. * i386-opc.tbl: Add rdpkru and wrpkru instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-12-09gas/ELF: slightly relax elf/file*.d expectationsJan Beulich1-0/+6
Despite the re-ordering done for the file symbols, some targets manage to put section symbols ahead of it.
2015-12-08gas: consistently emit diagnostics for non-zero data emission to .bss/.structJan Beulich1-0/+6
2015-12-08ELF: don't re-order SHF_FILE symbolsJan Beulich1-0/+7
.file directives may be used to identify the scope of local symbols, the purpose of which gets subverted when re-ordering them. Only allow the first of them to be moved to the first position.
2015-12-04Fix GAS testsuite failures for COFF/PE based ARM targets.Nick Clifton1-0/+6
PR gas/19276 gas * config/tc-arm.h (SUB_SEGMENT_ALIGN): Do not define for COFF/PE targets. testsuite * gas/arm/align64.d: Skip for COFF/PE targets. * gas/arm/bundle-lock.d: Adjust for COFF/PE targets.
2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu1-0/+22
gas * config/tc-arc.c (arc_option): Sets all internal gas options when parsing .cpu directive. (declare_register_set): Declare all 64 registers. (md_section_align): Refactor. (md_pcrel_from_section): Remove assert. (pseudo_operand_match): Fix pseudo operand match. (find_reloc): Use flags filed, extend matching. * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT relocation. testsuite * gas/arc/bic.d: Update test. * gas/arc/add_s-err.s: New file. * gas/arc/cpu-warn1.s: Likewise. * gas/arc/pcl-relocs.d: Likewise. * gas/arc/pcl-relocs.s: Likewise. * gas/arc/pcrel-relocs.d: Likewise. * gas/arc/pcrel-relocs.s: Likewise. * gas/arc/pic-relocs.d: Likewise. * gas/arc/pic-relocs.s: Likewise. * gas/arc/plt-relocs.d: Likewise. * gas/arc/plt-relocs.s: Likewise. * gas/arc/pseudos.d: Likewise. * gas/arc/pseudos.s: Likewise. * gas/arc/sda-relocs.d: Likewise. * gas/arc/sda-relocs.s: Likewise. * gas/arc/sda-relocs2.d: Likewise. * gas/arc/sda-relocs2.s: Likewise. * gas/arc/tls-relocs.d: Likewise. * gas/arc/tls-relocs.s: Likewise. opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32]. opcodes * arc-dis.c (special_flag_p): Match full mnemonic. * arc-opc.c (print_insn_arc): Check section size to read appropriate number of bytes. Fix printing. * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without arguments.
2015-12-02Fix ldah being disassembled as ldaexhAndre Vieira1-0/+5
2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> opcodes/ * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo... <ldah>: ... to this. gas/testsuite/ * gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ... <ldah>: ... to this.
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-0/+5
ARMv8.2 adds 16-bit floating point operations as an optional extension to the ARMv8 FP support. This patch adds the new FP16 instructions, making them available when the architecture extension +fp+fp16 is specified. The instructions added are: - Comparisons and conditionals: FCMP, FCCMPE, FCMP, FCMPE and FCSEL. - Arithmetic: FABS, FNEG, FSQRT, FMUL, FDIV, FADD, FSUB, FMADD, FMSUB, FNMADD and FNMSUB. - Rounding: FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX and FRINTI. - Conversions: SCVTF (fixed-point), SCVTF (integer), UCVTF (fixed-point) UCVTF (integer), FCVTZS (fixed-point), FCVTZS (integer), FCVTZU (fixed-point), FCVTZU (integer), FCVTNS, FCVTNU, FCVTAS, FCVTAU, FCVTPS, FCVTPU, FCVTMS and FCVTMU. - Scalar FMOV: immediate, general and register gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/float-fp16.d: New. * gas/aarch64/float-fp16.s: New. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New. (QL_INT2FP_H, QL_FP2INT_H): New. (QL_FP2_H, QL_FP3_H, QL_FP4_H): New (QL_DST_H): New. (QL_FCCMP_H): New. (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf, fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau, fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp, fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm, frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax, fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and fcsel. Change-Id: Ie6d40bd1b215a9bc024e12ba75e52afbe1675eb7
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-0/+5
This patch adds the alias REV64 <Rd>, <Rs> as an alias for REV <Rd>, <Rs>. However, REV is still the preferred form for the instruction. gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/alias-2.d: Add tests for REV. * gas/aarch64/alias-2.s: Likewise. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add "rev64". Change-Id: I331567c8d3618ba9fec1673c6e0b5977222dde61
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-0/+5
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as an alias for REV. This patch set adds support for these to binutils, enabled when the -march=armv8.2-a is given. It depends on the support for an instruction being its preferred form which was added in an earlier patch. This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred form for BFM when the source is a zero register and the conditions for using the BFI form are met (in other words, BFC is the preferred form for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register). gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/alias-2.d: New. * gas/aarch64/alias-2.s: New. include/opcode/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_op): Add OP_BFC. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-asm.c (convert_bfc_to_bfm): New. (convert_to_real): Add case for OP_BFC. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c: (convert_bfm_to_bfc): New. (convert_to_alias): Add case for OP_BFC. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert to allow width operand in three-operand instructions. * aarch64-tbl.h (QL_BF1): New. (aarch64_feature_v8_2): New. (ARMV8_2): New. (aarch64_opcode_table): Add "bfc". Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
2015-11-27[Aarch64] Support an ARMv8.2 system register.Matthew Wahab1-0/+5
ARMv8.2 adds a new system register id_aa64mmfr2_el1. This patch adds support for the register to binutils, making it available when -march=armv8.2-a is selected. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1". (aarch64_sys_reg_supported_p): Add ARMv8.2 system register feature test. gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: New. * gas/aarch64/sysreg-2.s: New. Change-Id: I767f18a60e2bd70ce74c89f6abfe07afdc9e601f
2015-11-24[GAS, ARM] Invalid LDR immediate transformationChristophe Monat1-0/+9
2015-11-24 Christophe Monat <christophe.monat@st.com> * config/tc-arm.c (move_or_literal_pool): Do not transform ldr ri,=imm into movs when ri is a high register in T1. 2015-11-24 Christophe Monat <christophe.monat@st.com> * gas/arm/thumb2_ldr_immediate_armv6t2.s: Added high register tests. * gas/arm/thumb2_ldr_immediate_armv6t2.d: Accounted for new test cases. * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: New. * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: New.
2015-11-24[ARM][GAS] Fix invalid arm-wince-pe tests.Matthew Wahab1-0/+13
There are a number of failures for the arm-wince-pe targets, most are due to the test being invalid for the target. This patch adjusts the invalid tests to either make them valid or to set them as skipped for arm-wince-pe targets. gas/testsuite 2015-11-24 Matthew Wahab <matthew.wahab@arm.com> * gas/arm/armv7e-m+fpv5-d16.d: Skip test for *-*-pe, *-wince-* and for *-*-coff targets. * gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise. * gas/arm/blx-bl-convert.d: Likewise. * gas/arm/ldst-offset0.d: Likewise. * gas/arm/thumb2_ldr_immediate_armv6t2.d: Likewise. * gas/arm/armv8-a+pan.s: Adjust test to make it valid for non-ELF targets. * gas/arm/wince.d: Add assembler option "-mccs". * gas/arm/wince_inst.d: Update expected output. Change-Id: I33a356e97eace3f8e1d581a46ec6413898105bef
2015-11-20MIPS/GAS/testsuite: Tighten negative-match NaN testsMaciej W. Rozycki1-0/+8
Fix a test quality regression introduced with commit 351cdf24 [[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensions] where MIPS ABI flags match patterns have been added to negative-match tests covering ELF file header flags. Negative-match tests succeed whenever there is a failure in matching output produced and consequently the likelihood of a false success increases when patterns to match irrelevant output are added. Therefore remove the irrelevant paterns so that the tests complete as soon as the line concerned has been seen. gas/testsuite/ * gas/mips/nan-legacy-1.d: Remove MIPS ABI flags match patterns. * gas/mips/nan-legacy-2.d: Likewise. * gas/mips/nan-legacy-3.d: Likewise. * gas/mips/nan-legacy-4.d: Likewise. * gas/mips/nan-legacy-5.d: Likewise.
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab1-0/+6
The ARMv8.1 architecture includes the Virtualization Host Extensions which add a number of system registers. This patch adds support for these system registers, making them available when -march=armv8.1-a is selected. include/opcode/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_V8_1): New. (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1. opcodes/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, amair_el12, vbar_el12, contextidr_el2, contextidr_el12, cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, cnthv_ctl_el2, cnthv_cval_el2. (aarch64_sys_reg_supported_p): Update for the new system registers. gas/testsuite/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/virthostext-directive.d: New. * gas/aarch64/virthostext.d: New. * gas/aarch64/virthostext.s: New. Change-Id: Iecb370591b1b6e9e00d81c8ccd9ae3b0f71794a2
2015-11-20Stop the ARM short mapping symbol test being run for the symbianelf target.Matthew Wahab1-0/+4
* gas/arm/mapshort-elf.d: Fix typo in exclusion list.
2015-11-19[AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab1-0/+6
The support for accessing the ARMv8.1 PSTATE field PAN allows instructions of the form MSR PAN, #<imm> with <imm> any unsigned 4-bit integer. However, the architecture specification requires that the immediate is either 0 or 1. This patch implements the constraint on the immediate, generating an error if the immediate operand is invalid, and adds tests for the illegal forms. opcodes/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Check validity of MSR PAN immediate operand. gas/testsuite/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/pan-illegal.d: New. * gas/aarch64/pan-illegal.l: New. * gas/aarch64/pan.s: Add tests for invalid immediates. Change-Id: Ibb3056c975eb792104da138d94594224f56a993e
generated by cgit v1.1 at 2024-11-23 04:44:42 +0000