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2016-09-29Add .cfi_val_offset GAS command.Andreas Krebbel1-0/+3
This patch adds support for .cfi_val_offset GAS pseudo command which maps to DW_CFA_val_offset and DW_CFA_val_offset_sf. gas/ChangeLog: 2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * doc/as.texinfo: Add docu for .cfi_val_offset. * dw2gencfi.c (cfi_add_CFA_val_offset): New function. (dot_cfi): Add case for DW_CFA_val_offset. (output_cfi_insn): Likewise. (cfi_pseudo_table): Add entry for cfi_val_offset. * dw2gencfi.h: Add prototype for cfi_add_CFA_val_offset. * testsuite/gas/cfi/cfi-common-8.d: New test. * testsuite/gas/cfi/cfi-common-8.s: New test. * testsuite/gas/cfi/cfi.exp: Run cfi-common-8 testcase. binutils/ChangeLog: 2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * dwarf.c (display_debug_frames): Adjust output line.
2016-09-26When building target binaries, ensure that the warning flags selected for ↵Vlad Zakharov1-0/+1
the command line match the target compiler. bfd * warning.m4 (AC_EGREP_CPP_FOR_BUILD): Introduce macro to verify CC_FOR_BUILD compiler. (AM_BINUTILS_WARNINGS): Introduce ac_cpp_for_build variable and add CC_FOR_BUILD compiler checks. * Makefile.in: Regenerate. * configure: Likewise. * doc/Makefile.in: Likewise. binutils * Makefile.am: Replace AM_CLFAGS with AM_CFLAGS_FOR_BUILD when building with CC_FOR_BUILD compiler. * Makefile.in: Regenerate. * configure: Likewise. * doc/Makefile.in: Likewise. gas * Makefile.in: Regenerate. * configure: Likewise. * doc/Makefile.in: Likewise. gold * Makefile.in: Regenerate. * configure: Likewise. * testsuite/Makefile.in: Likewise. gprof * Makefile.in: Regenerate. * configure: Likewise. ld * Makefile.in: Regenerate. * configure: Likewise. opcodes * Makefile.in: Regenerate. * configure: Likewise.
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+2
This patch adds the SVE instruction definitions and associated OP_* enum values. include/ * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro. (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi) (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P) (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops. opcodes/ * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) (OP_SVE_XWU, OP_SVE_XXU): New macros. (aarch64_feature_sve): New variable. (SVE): New macro. (_SVE_INSN): Likewise. (aarch64_opcode_table): Add SVE instructions. * aarch64-opc.h (extract_fields): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. * aarch64-asm-2.c: Regenerate. * aarch64-dis.c (extract_fields): Make global. (do_misc_decoding): Handle the new SVE aarch64_ops. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document the "sve" feature. * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type. (get_reg_expected_msg): Handle it. (parse_operands): When parsing operands of an SVE instruction, disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP. (aarch64_features): Add an entry for SVE.
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi2-7/+24
Before SPARC V9 the effect of having a delayed branch instruction in the delay slot of a conditional delayed branch was undefined. In SPARC V9 DCTI couples are well defined. However, starting with the UltraSPARC Architecture 2005, DCTI couples (of all kind) are deprecated and should not be used, as they may be slow or behave differently to what the programmer expects. This patch adds a new command line option --dcti-couples-detect to `as', disabled by default, that makes the assembler to warn the user if an unpredictable DCTI couple is found. Tests and documentation are included. gas/ChangeLog: 2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (md_assemble): Detect and warning on unpredictable DCTI couples in certain arches. (dcti_couples_detect): New global. (md_longopts): Add command line option -dcti-couples-detect. (md_show_usage): Document -dcti-couples-detect. (md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests. * testsuite/gas/sparc/dcti-couples.s: New file. * testsuite/gas/sparc/dcti-couples-v9c.d: Likewise. * testsuite/gas/sparc/dcti-couples-v8.d: Likewise. * testsuite/gas/sparc/dcti-couples-v9.d: Likewise. * testsuite/gas/sparc/dcti-couples-v9c.l: Likewise. * testsuite/gas/sparc/dcti-couples-v8.l: Likewise. * doc/as.texinfo (Overview): Document --dcti-couples-detect. * doc/c-sparc.texi (Sparc-Opts): Likewise.
2016-09-12S/390: Add alternate processor names.Andreas Krebbel2-16/+32
This patch adds alternate CPU names which adhere to the number of the architecture document. So instead of having z196, zEC12, and z13 you can use arch9, arch10, and arch11. The old cpu names stay valid and should primarily be used. The alternate names are supposed to improve compatibility with the IBM XL compiler toolchain which uses the arch numbering. opcodes/ChangeLog: 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Support alternate arch strings. gas/ChangeLog: 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Support alternate arch strings. * doc/as.texinfo: Document new arch strings. * doc/c-s390.texi: Likewise.
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+2
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures Software Developer’s Manual, June 2016. gas/ * config/tc-i386.c (cpu_arch): Add .ptwrite. * doc/c-i386.texi: Document ptwrite and .ptwrite. * testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel, x86-64-ptwrite and x86-64-ptwrite-intel. * testsuite/gas/i386/ptwrite-intel.d: New file. * testsuite/gas/i386/ptwrite.d: Likewise. * testsuite/gas/i386/ptwrite.s: Likewise. * testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.s: Likewise. opcodes/ * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. (PREFIX_MOD_3_0FAE_REG_4): Likewise. (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. (cpu_flags): Add CpuPTWRITE. * i386-opc.h (CpuPTWRITE): New. (i386_cpu_flags): Add cpuptwrite. * i386-opc.tbl: Add ptwrite instruction. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-06-27Add command line option to stop the assembler from padding the end of ↵Nick Clifton1-1/+17
sections to their alignment boundary. PR gas/20247 * as.h (do_not_pad_sections_to_alignment): New global variable. * as.c (show_usage): Add --no-pad-sections. (parse_args): Likewise. * write.c (size_seg): Skip padding the end of the section if requested from the command line. (SUB_SEGMENT_ALIGN): Likewise. * doc/as.texinfo: Document the new option. * NEWS: Mention the new feature. * testsuite/gas/elf/section11.s: New test. * testsuite/gas/elf/section11.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test.
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall2-4/+22
gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.
2016-06-13Accept vulcan as a cpu name for the AArch64 port of GAS.Virendra Pathak1-0/+1
* config/tc-aarch64.c (aarch64_cpus): Add Broadcom Vulcan. * doc/c-aarch64.texi: Document that vulcan is a valid processor name.
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab1-0/+2
This patch adds the architecture extension "+ras" to enable RAS support. It is enabled by default for -march=armv8.2-a and available but disabled by default for armv8-a and armv8.1-a. gas/ * config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras. (arm_ext_ras): Renamed from arm_ext_v8_2. (insns): Update for arm_ext_v8_2 renaming. (arm_extensions): Add "ras". * doc/c-arm.texi (ARM Options): Add an entry for "ras". * testsuite/gas/arm/armv8-a+ras.d: New. * testsuite/gas/arm/armv8_2-a.d: Add explicit command line options. include/ * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding entries. (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS. opcodes/ * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with ARM_EXT_RAS in relevant entries.
2016-06-03[AArch64][gas] Add support for Cortex-A73Kyrylo Tkachov1-0/+1
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry. * doc/c-aarch64.texi (-mcpu): Document cortex-a73 value.
2016-06-03[ARM][gas] Add support for Cortex-A73Kyrylo Tkachov1-0/+1
* config/tc-arm.c (arm_cpus): Add cortex-a73 entry. * doc/c-arm.texi (-mcpu=): Document cortex-a73 value.
2016-05-29Add .noavx512XX directives to x86 assemblerH.J. Lu1-0/+9
Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq, .noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2. * testsuite/gas/i386/noavx512-1.l: New file. * testsuite/gas/i386/noavx512-1.s: Likewise. * testsuite/gas/i386/noavx512-2.l: Likewise. * testsuite/gas/i386/noavx512-2.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. * i386-init.h: Regenerated.
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-1/+12
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C, FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives to x86 assembler. TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_arch): Add 687. (cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. (parse_real_register): Check cpuregmmx instead of cpummx for MMX register. Check cpuregxmm instead of cpusse for XMM register. Check cpuregymm instead of cpuavx for YMM register. Check cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register. * doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. * testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx. * testsuite/gas/i386/arch-10.d (as): Likewise. * testsuite/gas/i386/arch-11.s: Add ".arch .mmx". * testsuite/gas/i386/i386.exp: Pass mmx to assembler for arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3 and noavx-4. * testsuite/gas/i386/no87-3.l: New file. * testsuite/gas/i386/no87-3.s: Likewise. * testsuite/gas/i386/noavx-3.l: Likewise. * testsuite/gas/i386/noavx-3.s: Likewise. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-4.s: Likewise. * testsuite/gas/i386/nosse-4.l: Likewise. * testsuite/gas/i386/nosse-4.s: Likewise. * testsuite/gas/i386/nosse-5.d: Likewise. * testsuite/gas/i386/nosse-5.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and CpuRegMask for AVX512. (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM and CpuRegMask. (set_bitfield_from_cpu_flag_init): New function. (set_bitfield): Remove const on f. Call set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. * i386-opc.h (CpuRegMMX): New. (CpuRegXMM): Likewise. (CpuRegYMM): Likewise. (CpuRegZMM): Likewise. (CpuRegMask): Likewise. (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm and cpuregmask. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-05-20MIPS: Add support for P6600Matthew Fortune1-0/+1
gas/ * config/tc-mips.c (mips_cpu_info_table): Update comment. Add p6600 entry. * doc/c-mips.texi: Document p6600 -march option.
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune2-2/+26
bfd/ * elfxx-mips.c (print_mips_ases): Add DSPR3. binutils/ * readelf.c (print_mips_ases): Add DSPR3. gas/ * config/tc-mips.c (options): Add OPTION_DSPR3 and OPTION_NO_DSPR3. (md_longopts): Likewise. (md_show_usage): Add help for -mdspr3 and -mno-dspr3. (mips_ases): Define availability for DSPr3. (mips_ase_groups): Add ASE_DSPR3 to the DSP group. (mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3. * doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2 formatting. * doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and .set nodspr3. Fix -mdspr2 formatting. * testsuite/gas/mips/mips32-dspr3.d: New file. * testsuite/gas/mips/mips32-dspr3.s: Likewise. * testsuite/gas/mips/mips.exp: Run mips32-dspr3 test. include/ * elf/mips.h (AFL_ASE_DSPR3): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3. * opcode/mips.h (ASE_DSPR3): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and mips64r6. * mips-opc.c (D34): New macro. (mips_builtin_opcodes): Define bposge32c for DSPr3.
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-1/+2
This patch enables Intel RDPID instruction described in Intel64 and IA-32 Architectures Software Developer's Manual, April 2016. gas/ * config/tc-i386.c (cpu_arch): Add RDPID. * doc/c-i386.texi: Document RDPID. gas/testsuite/ * gas/i386/i386.exp: Run RDPID tests. * gas/i386/prefix.d: Adjust. * gas/i386/rdpid.s: New test. * gas/i386/rdpid.d: Ditto. * gas/i386/rdpid-intel.d: Ditto. * gas/i386/x86-64-rdpid.s: Ditto. * gas/i386/x86-64-rdpid.d: Ditto. * gas/i386/x86-64-rdpid-intel.d: Ditto. opcodes/ * i386-dis.c (prefix_table): Add RDPID instruction. * i386-gen.c (cpu_flag_init): Add RDPID flag. (cpu_flags): Add RDPID bitfield. * i386-opc.h (enum): Add RDPID element. (i386_cpu_flags): Add RDPID field. * i386-opc.tbl: Add RDPID instruction. * i386-init.h: Regenerate. * i386-tbl.h: Regenerate.
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu1-0/+6
gas/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP. (arc_extinsn): Handle new introduced syntax. * testsuite/gas/arc/textinsn1op.d: New file. * testsuite/gas/arc/textinsn1op.s: Likewise. * doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP. opcodes/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. (arcExtMap_genOpcode): Likewise. * arc-opc.c (arg_32bit_rc): Define new variable. (arg_32bit_u6): Likewise. (arg_32bit_limm): Likewise. include/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_SYNTAX_1OP): Declare (ARC_SYNTAX_NOP): Likewsie. (ARC_OP1_MUST_BE_IMM): Update defined value. (ARC_OP1_IMM_IMPLIED): Likewise. (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
2016-04-20gas/doc/arc: Add nps400 references into the documentationAndrew Burgess1-2/+8
Add nps400 to the list of acceptable values for the -mcpu command line switch, and to the .cpu directive. I've added an extra cross reference from -mcpu to .cpu to improve navigation of the documentation. gas/ChangeLog: * doc/c-arc.texi (ARC Options): Add nps400 to list of valus for -mcpu. Add cross reference to .cpu directive from -mcpu option. (ARC Directives): Add NPS400 to .cpu directive list.
2016-04-20[AArch64] Support RAS extension for ARMv8 onwards.Matthew Wahab1-0/+3
The RAS extension was introduced as part of the ARMv8.2 architecture where it is a required feature. It is also available as an optional feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is currently enabled by default for -march=armv8.2-a but is not available for -march=armv8 or -march=armv8.1-a. This patch adds the feature extension '+ras' to enable the RAS extension for ARMv8 and ARMv8.1, it is disabled by default. gas/ 2016-04-20 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "ras". * doc/c-aarch64.texi (AArch64 Extensions): Add "ras". * testsuite/gas/aarch64/armv8-ras-1.d: New. * testsuite/gas/aarch64/armv8-ras-1.s: New. * testsuite/gas/aarch64/illegal-ras-1.d: New. * testsuite/gas/aarch64/illegal-ras-1.s: New. Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
2016-04-19.cfi_remember_state/.cfi_restore_state documentationMartin Galvan1-5/+48
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve documentation.
2016-04-15Regenerate Makefile.in/aclocal.m4 automake 1.11.6H.J. Lu1-29/+81
bfd/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. binutils/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. gas/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. gold/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * testsuite/Makefile.in: Likewise. gprof/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. ld/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. opcodes/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise.
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu1-3/+79
gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister.d: New file. * testsuite/gas/arc/textauxregister.s: Likewise. * testsuite/gas/arc/textcondcode.d: Likewise. * testsuite/gas/arc/textcondcode.s: Likewise. * testsuite/gas/arc/textcoreregister.d: Likewise. * testsuite/gas/arc/textcoreregister.s: Likewise. * testsuite/gas/arc/textpseudoop.d: Likewise. * testsuite/gas/arc/textpseudoop.s: Likewise. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/taux.d: Likewise. * doc/c-arc.texi (ARC Directives): Add .extCondCode, .extCoreRegister and .extAuxRegister documentation. * config/tc-arc.c (arc_extcorereg): New function. (md_pseudo_table): Add .extCondCode, .extCoreRegister and .extAuxRegister pseudo-ops. (extRegister_t): New type. (ext_condcode, arc_aux_hash): New global variable. (find_opcode_match): Check for extensions. (preprocess_operands): Likewise. (md_begin): Add aux registers in a hash. (assemble_insn): Update use arc_flags member. (tokenize_extregister): New function. (create_extcore_section): Likewise. * config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10. (arc_flags): Delete code, add flgp. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (flag_class_t): Update. (ARC_OPCODE_NONE): Define. (ARC_OPCODE_ARCALL): Likewise. (ARC_OPCODE_ARCFPX): Likewise. (ARC_REGISTER_READONLY): Likewise. (ARC_REGISTER_WRITEONLY): Likewise. (ARC_REGISTER_NOSHORT_CUT): Likewise. (arc_aux_reg): Add cpu. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format): Check for extension flags. (print_flags): New function. (print_insn_arc): Update for .extCondCode, .extCoreRegister and .extAuxRegister. * arc-ext.c (arcExtMap_coreRegName): Use LAST_EXTENSION_CORE_REGISTER. (arcExtMap_coreReadWrite): Likewise. (dump_ARC_extmap): Update printing. * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. (arc_aux_regs): Add cpu field. * arc-regs.h: Add cpu field, lower case name aux registers. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu1-4/+91
gas/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textinsn-errors.d: New File. * testsuite/gas/arc/textinsn-errors.err: Likewise. * testsuite/gas/arc/textinsn-errors.s: Likewise. * testsuite/gas/arc/textinsn2op.d: Likewise. * testsuite/gas/arc/textinsn2op.s: Likewise. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * doc/c-arc.texi (ARC Directives): Add .extInstruction documentation. * config/tc-arc.c (arcext_section): New variable. (arc_extinsn): New function. (md_pseudo_table): Add .extInstruction pseudo op. (attributes_t): New type. (suffixclass, syntaxclass, syntaxclassmod): New constant structures. (find_opcode_match): Remove arc_num_opcodes. (md_begin): Likewise. (tokenize_extinsn): New function. (arc_set_ext_seg): Likewise. (create_extinst_section): Likewise. include/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (arc_num_opcodes): Remove. (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM) (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND) (ARC_SUFFIX_FLAG): Define. (flags_none, flags_f, flags_cc, flags_ccf): Declare. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. opcodes/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): Initialize. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. (arc_opcode arc_opcodes): Null terminate the array. (arc_num_opcodes): Remove. * arc-ext.h (INSERT_XOP): Define. (extInstruction_t): Likewise. (arcExtMap_instName): Delete. (arcExtMap_insn): New function. (arcExtMap_genOpcode): Likewise. * arc-ext.c (ExtInstruction): Remove. (create_map): Zero initialize instruction fields. (arcExtMap_instName): Remove. (arcExtMap_insn): New function. (dump_ARC_extmap): More info while debuging. (arcExtMap_genOpcode): New function. * arc-dis.c (find_format): New function. (print_insn_arc): Use find_format. (arc_get_disassembler): Enable dump_ARC_extmap only when debugging. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-07Update AArch64 documentation regarding architecture extensions.James Greenhalgh1-8/+10
* doc/c-aarch64.texi (Architecture Extensions): Add entry for LSE. Correct entry for RDMA. Alpha sort entries.
2016-03-18Update description of AArch64 assembler directives.Nick Clifton1-4/+41
gas * doc/c-aarch64.texi (AArch64 Directives): Add descriptions of .cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall, .tlsdescldr and .xword directives.
2016-03-18Fix generation of as.1 manual page so that it can be converted to DocBook ↵Nick Clifton1-0/+2
format. gas * doc/as.texinfo: Place the target specific command line options into their own man page section. etc * texi2pod.pl: Add TARGET to the list of recognised man page sections.
2016-03-15Update x86 register name documentation.Ulrich Drepper1-7/+43
* doc/c-i386.texi (Register Naming): Update to details of the latest architecture version.
2016-03-07[ARM] Add support for Cortex-R8Thomas Preud'homme1-0/+1
2016-03-07 Andre Vieira <andre.simoesdiasvieira@arm.com> gas/ * config/tc-arm.c (arm_cpus): Add cortex-r8. * doc/c-arm.texi: Add cortex-r8.
2016-02-26Properly implement STT_COMMONH.J. Lu1-0/+9
The BFD configure option, --enable-elf-stt-common, can't be to used to verify STT_COMMON implementation with the normal binutils build. Instead, this patch removes it from BFD. It adds --elf-stt-common=[no|yes] to ELF assembler/objcopy and adds -z common/-z nocommon to ld. A configure option, --enable-elf-stt-common, is added to gas to specify whether ELF assembler should generate common symbols with the STT_COMMON type by default. Since BSF_KEEP_G is never used, it is renamed to BSF_ELF_COMMON for ELF common symbols. bfd/ PR ld/19645 * bfd.c (bfd): Change flags to 20 bits. (BFD_CONVERT_ELF_COMMON): New. (BFD_USE_ELF_STT_COMMON): Likewise. (BFD_FLAGS_SAVED): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. (BFD_FLAGS_FOR_BFD_USE_MASK): Likewise. * configure.ac: Remove --enable-elf-stt-common. * elf.c (swap_out_syms): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. * elfcode.h (elf_slurp_symbol_table): Set BSF_ELF_COMMON for STT_COMMON. * elflink.c (bfd_elf_link_mark_dynamic_symbol): Also check STT_COMMON. (elf_link_convert_common_type): New function. (elf_link_output_extsym): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. Set sym.st_info after sym.st_shndx. * elfxx-target.h (TARGET_BIG_SYM): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON to object_flags. (TARGET_LITTLE_SYM): Likewise. * syms.c (BSF_KEEP_G): Renamed to ... (BSF_ELF_COMMON): This. * bfd-in2.h: Regenerated. * config.in: Likewise. * configure: Likewise. binutils/ PR ld/19645 * NEWS: Mention --elf-stt-common= for objcopy. * doc/binutils.texi: Document --elf-stt-common= for objcopy. * objcopy.c (do_elf_stt_common): New. (command_line_switch): Add OPTION_ELF_STT_COMMON. (copy_options): Add --elf-stt-common=. (copy_usage): Add --elf-stt-common=. (copy_object): Also check do_elf_stt_common for ELF targets. (copy_file): Handle do_elf_stt_common. (copy_main): Handle OPTION_ELF_STT_COMMON. * readelf.c (apply_relocations): Support STT_COMMON. * testsuite/binutils-all/common-1.s: New file. * testsuite/binutils-all/common-1a.d: Likewise. * testsuite/binutils-all/common-1b.d: Likewise. * testsuite/binutils-all/common-1c.d: Likewise. * testsuite/binutils-all/common-1d.d: Likewise. * testsuite/binutils-all/common-1e.d: Likewise. * testsuite/binutils-all/common-1f.d: Likewise. * testsuite/binutils-all/common-2.s: Likewise. * testsuite/binutils-all/common-2a.d: Likewise. * testsuite/binutils-all/common-2b.d: Likewise. * testsuite/binutils-all/common-2c.d: Likewise. * testsuite/binutils-all/common-2d.d: Likewise. * testsuite/binutils-all/common-2e.d: Likewise. * testsuite/binutils-all/common-2f.d: Likewise. * testsuite/binutils-all/objcopy.exp (objcopy_test_elf_common_symbols): New proc. Run objcopy_test_elf_common_symbols for ELF targets gas/ PR ld/19645 * NEWS: Mention --enable-elf-stt-common and --elf-stt-common= for ELF assemblers. * as.c (flag_use_elf_stt_common): New. (show_usage): Add --elf-stt-common=. (option_values): Add OPTION_ELF_STT_COMMON. (std_longopts): Add --elf-stt-common=. (parse_args): Handle --elf-stt-common=. * as.h (flag_use_elf_stt_common): New. * config.in: Regenerated. * configure: Likewise. * configure.ac: Add --enable-elf-stt-common and define DEFAULT_GENERATE_ELF_STT_COMMON. * gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set. * doc/as.texinfo: Document --elf-stt-common=. * testsuite/gas/elf/common3.s: New file. * testsuite/gas/elf/common3a.d: Likewise. * testsuite/gas/elf/common3b.d: Likewise. * testsuite/gas/elf/common4.s: Likewise. * testsuite/gas/elf/common4a.d: Likewise. * testsuite/gas/elf/common4b.d: Likewise. * testsuite/gas/i386/dw2-compress-3b.d: Likewise. * testsuite/gas/i386/dw2-compressed-3b.d: Likewise. * testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a and common4b. * testsuite/gas/i386/dw2-compress-3.d: Renamed to ... * testsuite/gas/i386/dw2-compress-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/dw2-compressed-3.d: Renamed to ... * testsuite/gas/i386/dw2-compressed-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/i386.exp: Run dw2-compress-3a, dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead of dw2-compress-3 and dw2-compressed-3. include/ PR ld/19645 * bfdlink.h (bfd_link_elf_stt_common): New enum. (bfd_link_info): Add elf_stt_common. ld/ PR ld/19645 * NEWS: Mention -z common/-z nocommon for ELF targets. * emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle -z common and -z nocommon. * ld.texinfo: Document -z common/-z nocommon. * lexsup.c (elf_shlib_list_options): Add -z common/-z nocommon. * testsuite/ld-elf/tls_common.exp: Test --elf-stt-common=no and --elf-stt-common=yes with assembler. * testsuite/ld-elfcomm/common-1.s: New file. * testsuite/ld-elfcomm/common-1a.d: Likewise. * testsuite/ld-elfcomm/common-1b.d: Likewise. * testsuite/ld-elfcomm/common-1c.d: Likewise. * testsuite/ld-elfcomm/common-1d.d: Likewise. * testsuite/ld-elfcomm/common-1e.d: Likewise. * testsuite/ld-elfcomm/common-1f.d: Likewise. * testsuite/ld-elfcomm/common-2.s: Likewise. * testsuite/ld-elfcomm/common-2a.d: Likewise. * testsuite/ld-elfcomm/common-2b.d: Likewise. * testsuite/ld-elfcomm/common-2c.d: Likewise. * testsuite/ld-elfcomm/common-2d.d: Likewise. * testsuite/ld-elfcomm/common-2e.d: Likewise. * testsuite/ld-elfcomm/common-2f.d: Likewise. * testsuite/ld-elfcomm/common-3a.rd: Likewise. * testsuite/ld-elfcomm/common-3b.rd: Likewise. * testsuite/ld-i386/pr19645.d: Likewise. * testsuite/ld-i386/pr19645.s: Likewise. * testsuite/ld-x86-64/largecomm-1.s: Likewise. * testsuite/ld-x86-64/largecomm-1a.d: Likewise. * testsuite/ld-x86-64/largecomm-1b.d: Likewise. * testsuite/ld-x86-64/largecomm-1c.d: Likewise. * testsuite/ld-x86-64/largecomm-1d.d: Likewise. * testsuite/ld-x86-64/largecomm-1e.d: Likewise. * testsuite/ld-x86-64/largecomm-1f.d: Likewise. * testsuite/ld-x86-64/pr19645.d: Likewise. * testsuite/ld-x86-64/pr19645.s: Likewise. * testsuite/ld-elfcomm/elfcomm.exp: Test --elf-stt-common=yes with assembler. (assembler_generates_commons): Removed. Run -z common/-z nocommon tests. Run *.d tests. * testsuite/ld-i386/i386.exp: Run pr19645. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/dwarfreloc.exp: Test --elf-stt-common with assembler. Test STT_COMMON with readelf.
2016-02-24[ARM][gas] Add support for Cortex-A32Kyrylo Tkachov1-0/+1
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (arm_cpus): Add entry for cortex-a32. * doc/c-arm.texi (ARM Options): Document cortex-a32.
2016-02-24[ARM][doc] Document cortex-a17 mcpu optionKyrylo Tkachov1-0/+1
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * doc/c-arm.texi (ARM Options): Document cortex-a17.
2016-02-16Remove documentation of deleted function S_IS_EXTERN.Trevor Saunders1-4/+0
2016-02-16Fix formatting problems caused by previous update to as.texinfo.Nick Clifton1-6/+11
* doc/as.texinfo (Section): Fix up texinfo snafus in previous update.
2016-02-15Enhance GAS's .section directive so that it can take numeric values for the ↵Nick Clifton1-1/+24
flags and type fields. (ELF only) gas * doc/as.texinfo (.section): Document that numeric values can now be used for the flags and type fields of the ELF target's .section directive. Add notes about the restrictions on setting flags and types. * config/obj-elf.c (obj_elf_change_section): Allow known sections to be given processor specific section types. Allow processor and application specific flags of a section to be set after definition. (obj_elf_parse_section_letters): Handle parsing numeric values. (obj_elf_section_type): Handle parsing numeric values. (obj_elf_section): Allow numeric type values. * config/obj-elf.h (obj_elf_change_section): Update prototype. * testsuite/gas/elf/section10.d: New test. * testsuite/gas/elf/section10.s: Source file for new test. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise. * NEWS: Mention the new feature. bfd * elf-bfd.h (struct bfd_elf_special_section): Use unsigned values for length and type fields. Use a signed value for the suffix_length field. binutils* readelf.c (get_section_type_name): Add hex prefix to offsets printed for LOPROC and LOOS values. Ensure that a result is always returned for the V850 target, even when an unrecognised processor specific value is encountered. (process_section_headers): Display key values in the order in which they appear to the user. Add the "C (compressed)" value to the list. ld * testsuite/ld-i386/pr12718.d: Remove dependency upon the description of the flags produced by readelf. * testsuite/ld-i386/pr12921.d: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic.rd: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-sh/tlsbin-2.d: Likewise. * testsuite/ld-sh/tlspic-2.d: Likewise. * testsuite/ld-tic6x/common.d: Likewise. * testsuite/ld-tic6x/shlib-1.rd: Likewise. * testsuite/ld-tic6x/shlib-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-noindex.rd: Likewise. * testsuite/ld-tic6x/static-app-1.rd: Likewise. * testsuite/ld-tic6x/static-app-1b.rd: Likewise. * testsuite/ld-tic6x/static-app-1r.rd: Likewise. * testsuite/ld-tic6x/static-app-1rb.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/ilp32-4.d: Likewise. * testsuite/ld-x86-64/pr12718.d: Likewise. * testsuite/ld-x86-64/pr12921.d: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/split-by-file.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic.rd: Likewise. * testsuite/ld-xtensa/tlsbin.rd: Likewise. * testsuite/ld-xtensa/tlspic.rd: Likewise.
2016-02-11Allow the .cfi_sections directive to be reissued provided that CFI ↵Nick Clifton1-0/+8
generation has not yet started. PR gas/19614 * dw2gencfi.c (cfi_sections_set): Delay setting this variable until it is actually used. (cfi_set_sections): Set cfi_sections_set to true. (dot_cfi_startproc): Likewise. (dot_cfi_endproc): Likewise. (dot_cfi_fde_data): Likewise. (cfi_finish): Likewise. (dot_cfi_sections): Do not set cfi_sections_set. * doc/as.texinfo (.cfi_sections): Note that targets can provide their own cfi section name. Also note that the directive can be reissued provided that CFI generation has not started. * testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and .cfi_endproc directives so that the redefinition of .cfi_sections will trigger the generation of the error message. * testsuite/gas/mips/compact-eh-err2.l: Update expected line number of error message.
2016-02-10Add support for ARC instruction relaxation in the assembler.Claudiu Zissulescu2-0/+7
gas/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS) (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE): Define. (arc_flags, arc_relax_type): New structure. * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY) (RELAX_TABLE_ENTRY_MAX): New define. (relaxation_state, md_relax_table, arc_relaxable_insns) (arc_num_relaxable_ins): New variable. (rlx_operand_type, arc_rlx_types): New enums. (arc_relaxable_ins): New structure. (OPTION_RELAX): New option. (arc_insn): New relax member. (arc_flags): Remove. (relax_insn_p): New function. (apply_fixups): Likewise. (relaxable_operand): Likewise. (may_relax_expr): Likewise. (relaxable_flag): Likewise. (arc_pcrel_adjust): Likewise. (md_estimate_size_before_relax): Implement. (md_convert_frag): Likewise. (md_parse_option): Handle new mrelax option. (md_show_usage): Likewise. (assemble_insn): Set relax member. (emit_insn0): New function. (emit_insn1): Likewise. (emit_insn): Handle relaxation case. * NEWS: Mention the new relaxation option. * doc/c-arc.texi (ARC Options): Document new mrelax option. gas/testsuite 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> * gas/arc/relax-avoid1.d: New file. * gas/arc/relax-avoid1.s: Likewise. * gas/arc/relax-avoid2.d: Likewise. * gas/arc/relax-avoid2.s: Likewise. * gas/arc/relax-avoid3.d: Likewise. * gas/arc/relax-avoid3.s: Likewise. * gas/arc/relax-b.d: Likewise. * gas/arc/relax-b.s: Likewise. include/opcode/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes): Declare. opcodes/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New variable.
2016-02-04Remove support for creating ARM NOREAD sections.Nick Clifton1-12/+0
gas * config/obj-elf.c (obj_elf_change_section): Remove support for ARM NOREAD sections. * config/tc-arm.c (arm_elf_section_letter): Delete. * config/tc-arm.h (md_elf_section_letter): Delete. * doc/c-arm.texi (ARM Section Attribute): Delete section. * testsuite/gas/arm/section-execute-only.d: Delete. * testsuite/gas/arm/section-execute-only.s: Delete. ld * testsuite/ld-arm/arm-elf.exp: Remove ARM NOREAD section tests. * testsuite/ld-arm/thumb1-input-section-flag-match.d: Delete. * testsuite/ld-arm/thumb1-input-section-flag-match.s: Delete. * testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.d: Delete. * testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.s: Delete. * testsuite/ld-arm/thumb1-noread-present-one-section.d: Delete. * testsuite/ld-arm/thumb1-noread-present-one-section.s: Delete. * testsuite/ld-arm/thumb1-noread-present-two-section.d: Delete. * testsuite/ld-arm/thumb1-noread-present-two-section.s: Delete.
2016-02-03Add -mrelax-relocations= to x86 assemblerH.J. Lu1-0/+12
The x86 relax relocations introduced in binutils 2.26 aren't supported by linker on Solaris older than Solaris 12. To use x86 assembler with older Solaris linker, this patch adds 1. A command line option -mrelax-relocations= to x86 assembler to control whether to generate relax relocations. 2. A configure option --enable-x86-relax-relocations to decide whether x86 assembler should generate relax relocations by default. It is defaulted to yes, except for x86 Solaris targets older than Solaris 12. gas/ PR gas/19520 * NEWS: Mention new command line option -mrelax-relocations and new configure option --enable-x86-relax-relocations for x86 target. * config.in: Regenerated. * configure.ac: Add --enable-x86-relax-relocations. (ac_default_x86_relax_relocations): New. Default to 1 except for x86 Solaris targets older than Solaris 12. (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define. * configure: Likewise. * config/tc-i386.c (generate_relax_relocations): New. (OPTION_MRELAX_RELOCATIONS): Likewise. (output_disp): Don't generate relax relocations if generate_relax_relocations is 0. (md_longopts): Add -mrelax-relocations. (md_show_usage): Likewise. (md_parse_option): Handle OPTION_MRELAX_RELOCATIONS. * doc/c-i386.texi: Document -mrelax-relocations=. * testsuite/gas/i386/got-no-relax.d: New file. * testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise. * testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as. * testsuite/gas/i386/localpic.d: Likewise. * testsuite/gas/i386/mixed-mode-reloc32.d: Likewise. * testsuite/gas/i386/reloc32.d: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. * testsuite/gas/i386/i386.exp: Run got-no-relax and x86-64-gotpcrel-no-relax. ld/ PR gas/19520 * testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as. * testsuite/ld-i386/call1.d: Likewise. * testsuite/ld-i386/call2.d: Likewise. * testsuite/ld-i386/call3a.d: Likewise. * testsuite/ld-i386/call3b.d: Likewise. * testsuite/ld-i386/call3c.d: Likewise. * testsuite/ld-i386/call3d.d: Likewise. * testsuite/ld-i386/call3e.d: Likewise. * testsuite/ld-i386/call3f.d: Likewise. * testsuite/ld-i386/call3g.d: Likewise. * testsuite/ld-i386/call3h.d: Likewise. * testsuite/ld-i386/jmp1.d: Likewise. * testsuite/ld-i386/jmp2.d: Likewise. * testsuite/ld-i386/lea1c.d: Likewise. * testsuite/ld-i386/load1.d: Likewise. * testsuite/ld-i386/load2.d: Likewise. * testsuite/ld-i386/load3.d: Likewise. * testsuite/ld-i386/load4a.d: Likewise. * testsuite/ld-i386/load5a.d: Likewise. * testsuite/ld-i386/mov2b.d: Likewise. * testsuite/ld-i386/mov3.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. * testsuite/ld-x86-64/call1a.d: Likewise. * testsuite/ld-x86-64/call1b.d: Likewise. * testsuite/ld-x86-64/call1c.d: Likewise. * testsuite/ld-x86-64/call1d.d: Likewise. * testsuite/ld-x86-64/call1e.d: Likewise. * testsuite/ld-x86-64/call1f.d: Likewise. * testsuite/ld-x86-64/call1h.d: Likewise. * testsuite/ld-x86-64/call1i.d: Likewise. * testsuite/ld-x86-64/load1a.d: Likewise. * testsuite/ld-x86-64/load1b.d: Likewise. * testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it. * testsuite/ld-i386/got1.dd: Updated. * testsuite/ld-i386/got1d.S (1): Removed. * testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2016-01-29Add option -mfence-as-lock-add=[no|yes].Andrew Senkevich1-0/+12
With -mfence-as-lock-add=yes lfence, mfence and sfence will be encoded as lock addl $0x0, (%{r,e}sp). gas/: * config/tc-i386.c (avoid_fence): New. (output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence is true. (OPTION_FENCE_AS_LOCK_ADD): New. (md_longopts): Add -mfence-as-lock-add. (md_parse_option): Handle -mfence-as-lock-add. (md_show_usage): Add -mfence-as-lock-add=[no|yes]. * doc/c-i386.texi (-mfence-as-lock-add): Document. gas/testsuite/: * gas/i386/i386.exp: Run new tests. * gas/i386/fence-as-lock-add.s: New. * gas/i386/fence-as-lock-add-yes.d: Likewise. * gas/i386/fence-as-lock-add-no.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
2016-01-20Upda the documentation on assembler error message generation.Nick Clifton1-8/+27
PR 19499 * doc/as.texinfo (Errors): Correct documentation describing the interaction of .file and .line with warning and error messages.
2016-01-20Add support for an ARM specific 'y' section attribute flag to mark the ↵Mickael Guene1-0/+13
section as NOREAD. bfd/ChangeLog: * elf32-arm.c ((elf32_arm_special_sections): Remove catch of noread section using '.text.noread' pattern. gas/ChangeLog: * config/obj-elf.c (obj_elf_change_section) : Allow arm section with SHF_ARM_NOREAD section flag. * config/tc-arm.h (md_elf_section_letter) : Implement this hook to handle letter 'y'. (arm_elf_section_letter) : Declare it. * config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set SHF_ARM_NOREAD section flag. * doc/c-arm.texi (ARM section attribute 'y'): Document it. gas/testsuite/ChangeLog: * gas/arm/section-execute-only.s: New test case. * gas/arm/section-execute-only.d: Expected output. ld/testsuite/ChangeLog: * ld-arm/thumb1-noread-not-present-mixing-two-section.s: Add 'y' attribute usage. * ld-arm/thumb1-noread-present-one-section.s: Likewise. * ld-arm/thumb1-noread-present-two-section.s: Likewise. * ld-arm/thumb1-input-section-flag-match.s: Likewise. binutils/ChangeLog: * readelf.c (get_elf_section_flags): Display y letter for section with SHF_ARM_NOREAD section flag in readelf section output. (process_section_headers): Add y letter in readelf section output key mapping for ARM architecture.
2016-01-01Copyright update for binutilsAlan Modra62-64/+64
2015-12-21Fix building pdfs of assembler documentation.Nick Clifton1-11/+19
PR gas/19386 * doc/as.texinfo (Strings): Prepend a space to index entries that start with a backslash. This works around a problem in the pdf generator.
2015-12-16[ARM] Add support for thumb1 pcrop relocations.Mickael Guene1-0/+16
To support thumb1 execute-only code we need to support four new relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC). These relocations allow the static linker to finalize construction of symbol address. Typical sequence of code to get address of the symbol foo is then the following : movs r3, #:upper8_15:#foo lsls r3, #8 adds r3, #:upper0_7:#foo lsls r3, #8 adds r3, #:lower8_15:#foo lsls r3, #8 adds r3, #:lower0_7:#foo This will give following sequence of text and relocations after assembly : 4: 2300 movs r3, #0 4: R_ARM_THM_ALU_ABS_G3_NC foo 6: 021b lsls r3, r3, #8 8: 3300 adds r3, #0 8: R_ARM_THM_ALU_ABS_G2_NC foo a: 021b lsls r3, r3, #8 c: 3300 adds r3, #0 c: R_ARM_THM_ALU_ABS_G1_NC foo e: 021b lsls r3, r3, #8 10: 3300 adds r3, #0 10: R_ARM_THM_ALU_ABS_G0_NC foo
2015-12-15Remove refernces to a non-existent silicon errata.Nick Clifton1-4/+0
* doc/c-msp430.texi (MSP430 Options): Remove references to a non-existent silicon errata. * config/tc-msp430.c: Likewise.
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato1-3/+4
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
2015-12-11[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.Matthew Wahab1-0/+2
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers and a new instruction. This patch set adds support for the extension to binutils, enabled when -march=armv8.2-a+profile is given. The patches in this series: - Add the new command line option and feature flags. - Add the new system registers. - Adjust the maximum number of aliases permitted for an instruction. - Add support for HINT aliases which take operands. - Add the new instruction, an alias of the HINT instruction. This patch adds the option "profile" to the permitted architecture extensions, disabling it by default. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "profile". * doc/c-aarch64.texi (AArch64 Extensions): Add "profile". include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_PROFILE): New. Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-10gas: documentation for the SPARC %dN and %qN fp registers notationJose E. Marchesi1-0/+8
gas/ChangeLog: 2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation for floating-point registers.
2015-12-10[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.Matthew Wahab1-1/+1
ARMv8.1 includes CRC as a required extension but this isn't reflected in the features enabled by -march=armv8.1-a. The FP16 feature modifier also clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2 is missing ARMv8.1 features. This patch enables +crc for -march values of armv8.1-a and later. It also fixes the values for AARCH64_FEATURE_F16 and makes AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc. include/opcode 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_F16): Fix clash with AARCH64_FEATURE_V8_1. (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and AARCH64_FEATURE_V8_1. Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
generated by cgit v1.1 at 2024-10-16 20:59:25 +0000