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2024-01-23aarch64: Update Architecture Extensions documentationAndrew Carlotti1-116/+142
Restructure the architecture extensions table, add a new table for architecture version dependencies, add missing architecture extensions, and improve some extension descriptions.
2024-01-15aarch64: rcpc3: Add +rcpc3 architectural feature support flagVictor Do Nascimento1-0/+3
Indicating the presence of the Armv8.2-a feature adding further support for the Release Consistency Model, the `+rcpc3' architectural extension flag is added to the list of possible `-march' options in Binutils, together with the necessary macro for encoding rcpc3 instructions.
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-0/+2
Hi, This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature along with +sve2p1 optional flag to enabe this feature. Also support for following SVE2p1 instructions is added addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+2
Hi, This patch add support for FEAT_SME2p1 and "movaz" instructions along with the optional flag +sme2p1. Following "movaz" instructions are add: Move and zero two ZA tile slices to vector registers. Move and zero four ZA tile slices to vector registers. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15gas: doc: update documentation for the new listing optionIndu Bhagat1-5/+11
Add a new listing option, -i, to emit ginsn in the listing output. We may also emit other SCFI information if necessary in the future. ginsn are most useful when seen alongside the assembly instructions. Hence, they are emitted when the user includes the assembly instructions in the listing output, i.e., "-ali=FILE". gas/doc/: * as.texi: Add documentation for the new listing option, -i.
2024-01-15gas: add new command line option --scfi=experimentalIndu Bhagat1-0/+15
When the command line option --scfi=experimenta is passed to the GNU assembler, it will synthesize DWARF call frame information (CFI) for the input assembly. The option --scfi=experimental will also ignore most of the existing .cfi_* directives, if already contained in the provided input file. Only the following CFI directives will not be ignored: - .cfi_sections, - .cfi_label, - .cfi_signal_frame To use SCFI, a target will need to: - define TARGET_USE_SCFI and TARGET_USE_GINSN, and other necessary definitions, - provide means to help GAS understand the target specific instruction semantics by creating ginsns. The upcoming support for SCFI is inteded to be experimental, hence the option --scfi=experimental. The --scfi= may see more options like --scfi=[all,none] added in future, once the SCFI support in GAS is mature and robust. The offering may also see for example, an --scfi=inline option for dealing with inline asm may be added in the future. In --scfi=inline option, the GNU assembler may consume (and not ignore) the compiler generated CFI for the code surrounding the inline asm. Also document the option. gas/ * as.c (show_usage): Add support for --scfi=experimental. (parse_args): Likewise. * as.h (enum synth_cfi_type): Define new type. * doc/as.texi: Document the new option.
2024-01-09aarch64: Add +d128 architectural feature supportVictor Do Nascimento1-0/+2
Indicating the presence of the Armv9.4-a features concerning 128-bit Page Table Descriptors, 128-bit System Registers and Instructions, the "+d128" architectural extension flag is added to the list of possible -march options in Binutils, together with the necessary macro for encoding d128 instructions.
2024-01-08arm: Add support for Armv8.9-A and Armv9.4-Asrinath1-0/+2
This patch adds AArch32 support for -march=armv8.9-a and -march=armv9.4-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries for ARM_ARCH_V9_4A and ARM_ARCH_V8_9A are technically redundant but it including them for macro code consistency across architectures.
2024-01-08gas/doc: fix several typosSamuel Tardieu10-18/+18
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
2024-01-05Add AMD znver5 processor supportTejas Joshi1-1/+3
gas/ * config/tc-i386.c (cpu_arch): Add znver5 ARCH. * doc/c-i386.texi: Add znver5. * testsuite/gas/i386/arch-15.d: New. * testsuite/gas/i386/arch-15.s: Likewise. * testsuite/gas/i386/arch-15-znver5.d: Likewise. * testsuite/gas/i386/i386.exp: Add new znver5 test cases. * testsuite/gas/i386/x86-64.exp: Likewise. * testsuite/gas/i386/x86-64-arch-5.d: Likewise. * testsuite/gas/i386/x86-64-arch-5.s: Likewise. * testsuite/gas/i386/x86-64-arch-5-znver5.d: Likewise. opcodes/ * i386-gen.c (isa_dependencies): Add ZNVER5 dependencies. * i386-init.h: Re-generated.
2024-01-05Arm/doc: separate @code from @item for older makeinfoJan Beulich1-103/+103
At least 4.12 doesn't like the constructs without a separator.
2024-01-05gas: correct .bss documentation for non-ELFJan Beulich1-1/+12
Only ELF permits the specification of a subsection, and even there not consistently: csky, mcore, and spu handle .bss similar to .lcomm.
2024-01-05Arm64: drop .bss overrideJan Beulich1-5/+0
The comment looks bogus (perhaps simply stale, perhaps wrongly copied from Arm in the first place), and there are also no other precautions against subsections being used on ELF with .bss. It also doesn't look to be a good idea to override the custom handlers that ELF and COFF have (afaict doing so further broke .previous on ELF). As to the mapping state update - such also doesn't appear to be done for other section switching, so its original purpose was at best questionable as well.
2024-01-05Arm: drop .bss overrideJan Beulich1-5/+0
The comment looks bogus (perhaps simply stale), and there are also no other precautions against subsections being used on ELF with .bss. It also doesn't look to be a good idea to override the custom handlers that ELF and COFF have (afaict doing so further broke .previous on ELF).
2024-01-04Update year range in copyright notice of binutils filesAlan Modra65-67/+67
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-1/+6
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-22RISC-V: drop .bss overrideJan Beulich1-4/+0
It doesn't look to be a good idea to override the custom handler that ELF has; afaict doing so broke .previous, and a sub-section specifier wasn't accepted either.
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo1-0/+2
This patch add support for FEAT_ITE "Instrumentation Extension" adding the "trcit" instruction. This is enabled by the +ite march flag.
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo1-0/+2
This patch add supports for FEAT_SPECRES2 "Enhanced speculation restriction instructions" adding the "cosp" instruction. This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+. It is enabled by the +predres2 march flag.
2023-12-15arm: reformat -march option section in gas documentationMatthieu Longo1-110/+129
Hi, This patch contains a reformatting of -march option section in gas documentation. For instance (see https://sourceware.org/binutils/docs-2.41/as.html#ARM-Options), before all the options were on one line: For armv8-a: +crc: Enables CRC32 Extension. +simd: Enables VFP and NEON for Armv8-A. +crypto: Enables Cryptography Extensions for Armv8-A, implies +simd. +sb: Enables Speculation Barrier Instruction for Armv8-A. +predres: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. +nofp: Disables all FPU, NEON and Cryptography Extensions. +nocrypto: Disables Cryptography Extensions. Now, the readability is improved thanks to the itemization of the options: For armv8-a: +crc: Enables CRC32 Extension. +simd: Enables VFP and NEON for Armv8-A. +crypto: Enables Cryptography Extensions for Armv8-A, implies +simd. +sb: Enables Speculation Barrier Instruction for Armv8-A. +predres: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. +nofp: Disables all FPU, NEON and Cryptography Extensions. +nocrypto: Disables Cryptography Extensions. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu.
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo1-0/+1
Hi, This patch adds support for the Cortex-X3 CPU to binutils. Gas regression testing for aarch64-none-linux-gnu target and found no regressions. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu.
2023-12-15arm: document -march=armv9.[123]-a binutils optionsMatthieu Longo1-0/+3
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu1-0/+7
SiFive has define as set of flexible instruction for extending vector coprocessor, it able to encoding opcode like .insn but with predefined format. List of instructions: sf.vc.x sf.vc.i sf.vc.vv sf.vc.xv sf.vc.iv sf.vc.fv sf.vc.vvv sf.vc.xvv sf.vc.ivv sf.vc.fvv sf.vc.vvw sf.vc.xvw sf.vc.ivw sf.vc.fvw sf.vc.v.x sf.vc.v.i sf.vc.v.vv sf.vc.v.xv sf.vc.v.iv sf.vc.v.fv sf.vc.v.vvv sf.vc.v.xvv sf.vc.v.ivv sf.vc.v.fvv sf.vc.v.vvw sf.vc.v.xvw sf.vc.v.ivw sf.vc.v.fvw Spec of Xsfvcp https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-authored-by: Hau Hsu <hau.hsu@sifive.com> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2023-11-30gas: support double-slash line comments in BPF assemblyJose E. Marchesi1-2/+2
This patch makes the BPF assembler to support double-slash line comments, like the llvm BPF assembler does. At this point both assemblers support the same commenting styles: - Line comments preceded by # or //. - Non-nestable block comments delimited by /* and */. This patch also adds a couple of tests to make sure all the comment styles work in both normal and pseudoc syntax. The manual is also updated to mention double-slash line comments.
2023-11-28gas: change meaning of ; in the BPF assemblerJose E. Marchesi1-3/+10
The BPF assembler in clang uses semi-colon (;) to separate statements, not to be begin line comments. This patch adapts the GNU assembler accordingly. Testsuite and documentation updated accordingly. 2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c: Semicolon does not start a comment, but separates multiple commands on a single line. * testsuite/gas/bpf/alu-pseudoc.s: Adapt test accordingly. * testsuite/gas/bpf/spacing-pseudoc.s: Likewise. * testsuite/gas/bpf/offset16-overflow.s: Likewise. * testsuite/gas/bpf/jump-relax-jump.s: Likewise. * testsuite/gas/bpf/jump-relax-ja.s: Likewise. * testsuite/gas/bpf/imm32-overflow.s: Likewise. * testsuite/gas/bpf/disp32-overflow.s: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.s: Likewise. * testsuite/gas/bpf/disp16-overflow.s: Likewise. * doc/c-bpf.texi (BPF Special Characters): Update.
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma1-0/+6
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the sub-extension "XTheadZvamo" for the "XTheadVector" extension, and it provides AMO instructions for T-Head VECTOR vendor extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadZvamo" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-zvamo.d: New test. * testsuite/gas/riscv/x-thead-vector-zvamo.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma1-0/+5
T-Head has a range of vendor-specific instructions ([2]). Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the "XTheadVector" extension, a collection of T-Head-specific vector instructions. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). Here are some things that need to be explained: The "XTheadVector" extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the "TheadVector" instructions overlaps with those of the 'V' extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the "XTheadVector" extension and the 'V' extension are in conflict. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 [2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): The "XTheadVector" extension and the 'V' extension are in conflict. (riscv_multi_subset_supports): Likewise.. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-fail.d: New test. * testsuite/gas/riscv/x-thead-vector-fail.l: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class):
2023-11-18gas: bpf: do not allow referring to register names as symbols in operandsJose E. Marchesi1-1/+6
2023-11-18 Jose E. Marchesi <jemarch@gnu.org> * config/tc-bpf.c (parse_bpf_register): Move before bpf_parse_name. (bpf_parse_name): Do not allow using symbols that are also register names as operands in pseudo-c syntax. * testsuite/gas/bpf/regs-for-symbols-pseudoc.d: New file. * testsuite/gas/bpf/regs-for-symbols-pseudoc.s: Likewise. * testsuite/gas/bpf/regs-for-symbols-pseudoc.l: Likewise. * doc/c-bpf.texi (BPF Registers): Document that it is not possible to refer to register names as symbols in instruction operands.
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-1/+2
This patch also adds support for: 1. FEAT_RASv2 feature and "ERXGSR_EL1" system register. RASv2 feature is enabled by passing +rasv2 to -march (eg: -march=armv8-a+rasv2). 2. FEAT_SCTLR2 and following system registers. SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3. 3. FEAT_FGT2 and following system registers. HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2 4. FEAT_PFAR and following system registers. PFAR_EL1, PFAR_EL2 and PFAR_EL12. FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default enabled from Armv9.4-A architecture. This patch also adds support for two read only system registers id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from Armv8-A Architecture.
2023-11-13Add documentation for the MIPS assembler's -march=from-abi command line optionNick Clifton1-0/+5
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+2
Enable the `+lse128' feature modifier which, together with new internal feature flags, enables LSE128 instructions, which are represented via the new `_LSE128_INSN' macro. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add new "lse128" entry. include/ChangeLog: * include/opcode/aarch64.h (enum aarch64_feature_bit): New AARCH64_FEATURE_LSE128 feature bit. (enum aarch64_insn_class): New lse128_atomic instruction class. opcodes/ChangeLog: * opcodes/aarch64-tbl.h (aarch64_feature_lse128): New. (LSE128): Likewise. (_LSE128_INSN): Likewise.
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento1-0/+3
Add Binutils support for system registers associated with the Translation Hardening Extension (THE). In doing so, we also add core feature support for THE, enabling its associated feature flag and implementing the necessary feature-checking machinery. Regression tested on aarch64-linux-gnu, no regressions. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add "+the" feature modifier. * doc/c-aarch64.texi (AArch64 Extensions): Update documentation for `the' option. * testsuite/gas/aarch64/sysreg-8.s: Add tests for `the' associated system registers. * testsuite/gas/aarch64/sysreg-8.d: Likewise. include/ChangeLog: * opcode/aarch64.h (enum aarch64_feature_bit): Add AARCH64_FEATURE_THE. opcode/ChangeLog: * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Add `the' system register check support. * aarch64-sys-regs.def: Add `rcwmask_el1' and `rcwsmask_el1' * aarch64-tbl.h: Define `THE' preprocessor macro.
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCValu as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-alu-boundaries.d: New test. * testsuite/gas/riscv/cv-alu-boundaries.l: New test. * testsuite/gas/riscv/cv-alu-boundaries.s: New test. * testsuite/gas/riscv/cv-alu-fail-march.d: New test. * testsuite/gas/riscv/cv-alu-fail-march.l: New test. * testsuite/gas/riscv/cv-alu-fail-march.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. * testsuite/gas/riscv/cv-alu-insns.d: New test. * testsuite/gas/riscv/cv-alu-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble xcb operand. * riscv-opc.c: Defined the MASK and added XCValu instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCValu. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for XCValu. (enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCVmac as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mac-fail-march.d: New test. * testsuite/gas/riscv/cv-mac-fail-march.l: New test. * testsuite/gas/riscv/cv-mac-fail-march.s: New test. * testsuite/gas/riscv/cv-mac-fail-operand.d: New test. * testsuite/gas/riscv/cv-mac-fail-operand.l: New test. * testsuite/gas/riscv/cv-mac-fail-operand.s: New test. * testsuite/gas/riscv/cv-mac-insns.d: New test. * testsuite/gas/riscv/cv-mac-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble information with the EXTRACT macro implemented. * riscv-opc.c: Defined the MASK and added XCVmac instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCVmac. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for uimm. (enum riscv_insn_class): Added the XCVmac instruction class.
2023-11-02aarch64: Add support for GCS extension.srinath1-0/+2
This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is optional from Armv9.4-A architecture and enabled by passing +gcs option to -march (eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file. Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx, gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni1-0/+2
This patch adds support for Check Feature Status Extension (CHK) which is mandatory from Armv8.0-A. Also this patch supports "chkfeat" instruction (hint #40).
2023-11-02aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures.srinath1-2/+2
This patch adds AArch64 support for Armv8.9-A architecture (-march=armv8.9-a) and Armv9.4-A architecture (-march=armv9.4-a).
2023-10-31Support Intel USER_MSRHu, Lin11-1/+2
This patches aims to support Intel USER_MSR. In addition to the usual support, this patch includes encoding and decoding support for MAP7 and immediate numbers as the last operand (ATT style). gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit mode. (build_vex_prefix): Add VEXMAP7. (md_assemble): Handling the imm32 of USER_MSR. (match_template): Handling the unusual immediate. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.l: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add a new attribute has_skipped_modrm. (Gq): New. (Rq): Ditto. (q_mm_mode): Ditto. (Nq): Change mode from q_mode to q_mm_mode. (VEX_LEN_TABLE): (get_valid_dis386): Add VEX_MAP7 in VEX prefix. and handle the map7_f8 for save space. (OP_Skip_MODRM): Set has_skipped_modrm. (OP_E): Skip codep++ when has skipped modrm byte. (OP_R): Support q_mode and q_mm_mode. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated.
2023-10-16RISC-V: Add "lp64e" ABI supportTsukasa OI1-3/+2
Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise.
2023-10-05aarch64: Enable Cortex-X4 CPUSaurabh Jha1-1/+2
2023-09-28Added support in gas for mlittle-endian and mbig-endian flags as options.Michael J. Eager2-1/+17
Updated show usage for MicroBlaze specific assembler options to include new entries. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> --- V1->V2: - removed new options which were unnecessary - added documentation for MicroBlaze specific options Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-1/+14
Recognize "/<number>" suffixes on both -march=+avx10.1 and the corresponding .arch directive, setting an upper bound on the vector size that insns may use. Such a restriction can be reset by setting a new base architecture, by using a suffix-less form, by disabling AVX10, or by enabling any other VEX/EVEX-based vector extension. While for most insns we can suppress their use with too wide operands via registers becoming unavailable (or in Intel syntax memory operand size specifiers not being recognized), mask register insns have to have their minimum required vector size specified in a new attribute. (Of course this new attribute could also be used on other insns.) Note that .insn continues to be permitted to emit EVEX{512,256} (and VEX256 ones) encodings regardless of vector size restrictions in place. Of course these can't be expressed using zmm (or ymm) operands then, but need using the EVEX.512.* forms (broadcast forms may be usable right now, but this may go away so shouldn't be relied upon). This is why no assertions should be added to build_{e,}vex_prefix().
2023-09-14x86: support AVX10.1/512Jan Beulich1-1/+2
Since this is merely a re-branding of certain AVX512* features, there's little code to be added. The main aspect here are new testcases. In order to be able to re-use some of the existing testcases, several of them need their start symbols adjusted. Note that 256- and 128-bit tests want adding here, as these need to work right away. Subsequently they'll gain vector length constraints. Since it was missing and is wanted here, also add an AVX512VL+VPOPCNTDQ test.
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu1-1/+2
The vendor operands should be named starting with `X', and preferably the second letter (or multiple following letters) is enough to differentiate them from other vendors. Therefore, added letter `t' after `X' for t-head operands, to differentiate from future different vendor's operands. bfd/ * elfxx-riscv.c (riscv_supported_vendor_x_ext): Removed the vendor document link since it should already be recorded in the gas/doc/c-riscv.texi. gas/ * config/tc-riscv.c (validate_riscv_insn): Added `t' after `X' for t-head operands. Minor updates for indents and comments. (riscv_ip): Likewise. * doc/c-riscv.texi: Minor updates. opcodes/ * riscv-dis.c (print_insn_args): Added `t' after `X' for t-head operands. Minor updates for indents and comments. * riscv-opc.c (riscv_opcode): Likewise.
2023-08-25gas/ELF: allow "inheriting" section attributes and typeJan Beulich1-0/+12
While --sectname-subst is nice, it isn't enough to e.g. mimic -f{function,data}-sections in assembly code, when such use is to be optional (e.g. dependent upon some configuration setting). Assign meaning to '+' and '-' as section attribute letters, allowing to inherit the prior section's attributes (and possibly type) along with adding or removing some. Note that documenting the interaction with '?' as undefined is a precautionary measure. While touching the function invocation, stop using |= on the result of obj_elf_parse_section_letters(): "attr" is firmly zero ahead of the call.
2023-08-21bpf: correct neg and neg32 instruction encodingDavid Faust1-16/+0
The neg/neg32 BPF instructions always use BPF_SRC_K (=0) in their header source bit, despite operating on registers. If BPF_SRC_X (=1) is set, the instructions are rejected by the kernel. Because of this there are also no neg/neg32 instructions which operate on immediates, so remove them. bd434cc4d94ec3d2f9fc1e7c00c27b074f962bc1 was a similar fix in the old CGEN-based port, but was not carried forward in the new port. include/ * opcode/bpf.h (enum bpf_insn_id): Remove spurious entries BPF_INSN_NEGI and BPF_INSN_NEG32I. opcodes/ * bpf-opc.c (bpf_opcodes): Remove erroneous NEGI and NEG32I instructions. gas/ * doc/c-bpf.texi (BPF Instructions): Remove erroneous neg and neg32 instructions operating on immediates. * testsuite/gas/bpf/alu.s: Adapt accordingly. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-08-17bpf: gas: consolidate handling of immediate overflowsJose E. Marchesi1-0/+8
This commit changes the BPF GAS port in order to handle immediate overflows the same way than the clang BPF assembler: - For an immediate field of N bits, any written number (positive or negative) whose two's complement encoding fit in N its is accepted. This means that -2 is the same than 0xffffffe. It is up to the instructions to decide how to interpret the encoded value. - Immediate fields in jump instructions are no longer relaxed. Relaxing to jump instructions with wider range is only performed when expressions are involved. - The manual is updated to document this, and testsuite adapted accordingly. Tested in x86_64-linux-gnu host, bpf-unknown-none target. gas/ChangeLog: 2023-08-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (check_immediate_overflow): New function. (encode_insn): Use check_immediate_overflow. (md_assemble): Do not relax instructions with constant disp16 fields. * doc/c-bpf.texi (BPF Instructions): Add note about how numerical literal values are interpreted for instruction immediate operands. * testsuite/gas/bpf/disp16-overflow.s: Adapt accordingly. * testsuite/gas/bpf/jump-relax-jump.s: Likewise. * testsuite/gas/bpf/jump-relax-jump.d: Likewise. * testsuite/gas/bpf/jump-relax-jump-be.d: Likewise. * testsuite/gas/bpf/jump-relax-ja.s: Likewise. * testsuite/gas/bpf/jump-relax-ja.d: Likewise. * testsuite/gas/bpf/jump-relax-ja-be.d: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.l: Likewise. * testsuite/gas/bpf/imm32-overflow.s: Likewise. * testsuite/gas/bpf/disp32-overflow.s: Likewise. * testsuite/gas/bpf/disp16-overflow.l: Likewise. * testsuite/gas/bpf/disp32-overflow.l: Likewise. * testsuite/gas/bpf/imm32-overflow.l: Likewise. * testsuite/gas/bpf/offset16-overflow.l: Likewise.
2023-08-16kvx: New port.Paul Iannetta4-0/+156
2023-08-16aarch64: Enable Cortex-A720 CPURichard Ball1-0/+1
This patch adds support for the Cortex-A720 CPU to binutils. bfd/ChangeLog: * cpu-aarch64.c: Add Cortex-A720. gas/ChangeLog: * NEWS: Update docs. * config/tc-aarch64.c: Add Cortex-A720. * doc/c-aarch64.texi: Update docs. * testsuite/gas/aarch64/cpu-cortex-a720.d: New test.
2023-08-10aarch64: Enable Cortex-A520 CPURichard Ball1-0/+1
This patch adds support for the Cortex-A520 CPU to gas. No regressions on aarch64-none-elf. gas/ChangeLog: * NEWS: Update docs. * config/tc-aarch64.c: Add Cortex-A520. * doc/c-aarch64.texi: Update docs.
generated by cgit v1.1 at 2024-11-29 19:43:03 +0000