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2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-3/+8
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-1/+7
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-1/+3
2020-10-14x86: Support Intel UINTRLili Cui1-1/+3
2020-10-05Fix spelling mistakesSamanta Navarro2-2/+2
2020-10-05GAS: Update the .section directive so that a numeric section index can be pro...Nick Clifton1-2/+5
2020-10-02arm: add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+2
2020-10-01Add new directive to GAS: .attach_to_group.Nick Clifton1-1/+11
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+2
2020-09-30aarch64: Add support for Neoverse N2 CPUAlex Coplan1-0/+1
2020-09-28This patch adds support for Cortex-X1 for ARM.Przemyslaw Wirkus1-0/+1
2020-09-28This patch adds support for Cortex-X1Przemyslaw Wirkus1-1/+2
2020-09-24arm: Add support for Neoverse V1 CPUAlex Coplan1-0/+1
2020-09-24aarch64: Add support for Neoverse V1 CPUAlex Coplan1-0/+1
2020-09-24arm: Add support for Neoverse N2 CPUAlex Coplan1-0/+1
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+3
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+5
2020-09-14Add a new ".nop" directive to the assembler to allow the creation of no-op in...Nick Clifton2-11/+31
2020-09-11gas: Don't error when .debug_line already exists, unless .loc was usedMark Wielaard1-2/+5
2020-09-08aarch64: Add -mcpu option for Cortex-R82Alex Coplan1-1/+2
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-1/+1
2020-09-01ELF: Document the .tls_common directiveH.J. Lu1-0/+13
2020-08-20Remove --reduce-memory-overheads and --hash-size arguments.Martin Liska2-45/+0
2020-08-12The description for -mno-csr-check talks about "cheching" rather than "checki...Nick Clifton1-1/+1
2020-08-04gas: Fix as.texi typo infortmationMark Wielaard1-3/+3
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-1/+4
2020-07-30Unify Solaris procfs and largefile handlingRainer Orth1-0/+1
2020-07-28x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)H.J. Lu1-1/+1
2020-07-27doc: Replace preceeded with precededH.J. Lu1-1/+1
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+7
2020-07-07x86: Remove an incorrect AVX2 entryH.J. Lu1-10/+0
2020-06-26m68k: tag floating-point ABI usedPat Bernardi1-0/+16
2020-06-16x86: Correct noavx512_vp2intersectCui,Lili1-0/+1
2020-06-15xtensa: allow runtime ABI selectionMax Filippov2-0/+9
2020-06-09[PATCH] gas/doc: improve AVR modifiers wording.Seth Girvan1-14/+23
2020-06-06Power10 tidiesAlan Modra1-0/+3
2020-06-03* gas/doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe.Stephen Casner1-1/+1
2020-06-02RISC-V: Fix minor bugs in .insn docs.Jim Wilson1-7/+6
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-0/+16
2020-05-06Section "3.1 Preprocessing" of the online GAS manual has a wrong reference to...Nick Clifton1-2/+3
2020-04-27x86: Add i386 PE big-object supportTamar Christina1-1/+2
2020-04-26Improve -mlfence-after-loadliuhongt1-4/+8
2020-04-22.symver fixesAlan Modra1-4/+3
2020-04-21gas: Extend .symver directiveH.J. Lu1-4/+12
2020-04-08x86: Correct -mlfence-before-indirect-branch= documentationH.J. Lu1-3/+3
2020-04-07gas/doc/c-z80.texi: Fix @xref warningsH.J. Lu1-5/+9
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-1/+3
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+2
2020-03-20Add support for the xdef and xref pseudo-ops to the Z80 assembler.Sergey Belyashov1-27/+56
2020-03-11i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]H.J. Lu1-0/+43
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