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2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-2/+0
This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-06RISC-V: Mention -mbig-endian and -mlittle-endian in docMarcus Comstedt2-0/+9
gas/ * doc/as.texi: Add -mlittle-endian and -mbig-endian to docs. * doc/c-riscv.texi: Likewise.
2021-01-01PR27116, Spelling errors found by Debian style checkerAlan Modra2-2/+2
PR 27116 bfd/ * xcofflink.c: Correct spelling in comments. binutils/ * coffgrok.c (do_type): Correct spelling of auxiliary in errors. * doc/binutils.texi: Correct grammar. * readelf.c (process_version_sections): Correct spelling of auxiliary in warning. * testsuite/binutils-all/vax/objdump.exp: Comment grammar fix. config/ * override.m4: Correct comment grammar. gas/ * config/tc-i386.c: Correct comment spelling. * config/tc-riscv.c: Likewise. * config/tc-s390.c: Correct comment grammar. * doc/c-i386.texi: Correct spelling. * doc/c-s390.texi: Correct grammar. gold/ * tilegx.cc: Correct comment spelling. gprof/ * README: Correct grammar. * gprof.texi: Likewise. include/ * coff/internal.h: Correct comment spelling. * coff/sym.h: Likewise. * opcode/aarch64.h: Likewise. ld/ * configure.tgt: Correct comment grammar. * emultempl/m68hc1xelf.em: Likewise. * ld.texi: Correct grammar.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra65-67/+67
2020-12-25gas: Update 80387 floating point 's' suffixH.J. Lu1-1/+1
Update 80387 floating point 's' suffix to read: * Integer constructors are '.word', '.long' or '.int', and '.quad' for the 16-, 32-, and 64-bit integer formats. The corresponding instruction mnemonic suffixes are 's' (short), 'l' (long), and 'q' (quad). instead of 's' (single). PR gas/27106 * doc/c-i386.texi: Update 80387 floating point 's' suffix
2020-11-23aarch64: Add support for Cortex-A78CPrzemyslaw Wirkus1-0/+1
This patch adds support for -mcpu=cortex-a78c command line option. For more information about this processor, see [0]: [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
2020-11-18Re: Stop Gas from generating line info or address rangesAlan Modra1-5/+9
* doc/as.texi (.nop): Document optional size arg. * dwarf2dbg.c (dwarf2_gen_line_info_1): Only check SEC_ALLOC when ELF. Warn whenever dwarf line number information is ignored. * frags.c (frag_offset_ignore_align_p): New function. * frags.h (frag_offset_ignore_align_p): Declare. * read.c (s_nop): Extend to support optional size arg. * testsuite/gas/elf/dwarf2-20.d: Expect warnings, and exact range. * testsuite/gas/elf/dwarf2-20.s: Emit 16 bytes worth of nops. * testsuite/gas/m68hc11/indexed12.d: Expect warnings.
2020-11-18Support SHF_GNU_RETAIN ELF section flagJozef Lawrynowicz1-0/+3
The SHF_GNU_RETAIN section flag is an extension to the GNU ELF OSABI. It is defined as follows: ========================================================= Section Attribute Flags +-------------------------------------+ | Name | Value | +-------------------------------------+ | SHF_GNU_RETAIN | 0x200000 (1 << 21) | +-------------------------------------+ SHF_GNU_RETAIN The link editor should not garbage collect the section. ========================================================= The .section directive accepts the "R" flag, which indicates SHF_GNU_RETAIN should be applied to the section. There is not a direct mapping of SHF_GNU_RETAIN to the BFD section flag SEC_KEEP. Keeping these flags distinct allows SHF_GNU_RETAIN sections to be explicitly removed by placing them in /DISCARD/. bfd/ChangeLog: * elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_retain. (struct elf_obj_tdata): Increase has_gnu_osabi to 4 bits. * elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_retain for SHF_GNU_RETAIN. (_bfd_elf_final_write_processing): Report if SHF_GNU_RETAIN is not supported by the OSABI. Adjust error messages. * elflink.c (elf_link_input_bfd): Copy enabled has_gnu_osabi bits from input BFD to output BFD. (bfd_elf_gc_sections): gc_mark the section if SHF_GNU_RETAIN is set. binutils/ChangeLog: * NEWS: Announce SHF_GNU_RETAIN support. * readelf.c (get_elf_section_flags): Handle SHF_GNU_RETAIN. Recognize SHF_GNU_RETAIN and SHF_GNU_MBIND only for supported OSABIs. * testsuite/binutils-all/readelf.exp: Run new tests. Don't run run_dump_test when there isn't an assembler available. * testsuite/lib/binutils-common.exp (supports_gnu_osabi): Adjust comment. * testsuite/binutils-all/readelf-maskos-1a.d: New test. * testsuite/binutils-all/readelf-maskos-1b.d: New test. * testsuite/binutils-all/readelf-maskos.s: New test. * testsuite/binutils-all/retain1.s: New test. * testsuite/binutils-all/retain1a.d: New test. * testsuite/binutils-all/retain1b.d: New test. gas/ChangeLog: * NEWS: Announce SHF_GNU_RETAIN support. * config/obj-elf.c (obj_elf_change_section): Merge SHF_GNU_RETAIN bit between section declarations. (obj_elf_parse_section_letters): Handle 'R' flag. Handle numeric flag values within the SHF_MASKOS range. (obj_elf_section): Validate SHF_GNU_RETAIN usage. * doc/as.texi: Document 'R' flag to .section directive. * testsuite/gas/elf/elf.exp: Run new tests. * testsuite/gas/elf/section10.d: Unset SHF_GNU_RETAIN bit. * testsuite/gas/elf/section10.s: Likewise. * testsuite/gas/elf/section22.d: New test. * testsuite/gas/elf/section22.s: New test. * testsuite/gas/elf/section23.s: New test. * testsuite/gas/elf/section23a.d: New test. * testsuite/gas/elf/section23b.d: New test. * testsuite/gas/elf/section23b.err: New test. * testsuite/gas/elf/section24.l: New test. * testsuite/gas/elf/section24.s: New test. * testsuite/gas/elf/section24a.d: New test. * testsuite/gas/elf/section24b.d: New test. include/ChangeLog: * elf/common.h (SHF_GNU_RETAIN): Define. ld/ChangeLog: * NEWS: Announce support for SHF_GNU_RETAIN. * ld.texi (garbage collection): Document SHF_GNU_RETAIN. (Output Section Discarding): Likewise. * testsuite/ld-elf/elf.exp: Run new tests. * testsuite/ld-elf/retain1.s: New test. * testsuite/ld-elf/retain1a.d: New test. * testsuite/ld-elf/retain1b.d: New test. * testsuite/ld-elf/retain2.d: New test. * testsuite/ld-elf/retain2.ld: New test. * testsuite/ld-elf/retain2.map: New test. * testsuite/ld-elf/retain3.d: New test. * testsuite/ld-elf/retain3.s: New test. * testsuite/ld-elf/retain4.d: New test. * testsuite/ld-elf/retain4.s: New test. * testsuite/ld-elf/retain5.d: New test. * testsuite/ld-elf/retain5.map: New test. * testsuite/ld-elf/retain5lib.s: New test. * testsuite/ld-elf/retain5main.s: New test. * testsuite/ld-elf/retain6a.d: New test. * testsuite/ld-elf/retain6b.d: New test. * testsuite/ld-elf/retain6lib.s: New test. * testsuite/ld-elf/retain6main.s: New test.
2020-11-17When reading string arguments for the assembler's string directives treat ↵Nick Clifton1-1/+3
space separated strings as a single entity. * read.c (stringer): Treat space separated, quote enclosed strings as a single string. * doc/as.texi (asciz): Mention this behaviour in the description of the asciz directive. * testsuite/gas/all/asciz.s: New test. * testsuite/gas/all/asciz.d: New test driver. * testsuite/gas/all/gas.exp: Run the new test.
2020-11-16aarch64: Add +pauth flag for Pointer Authentication featurePrzemyslaw Wirkus1-1/+3
New -march option +pauth enables PAuth vel PAC (Pointer Authentication) feature.
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-0/+6
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A. Please note that FLAGM stays a Armv8.4-A feature but now can be assigned to other architectures or CPUs. New -march option +flagm is added to enable independently this feature.
2020-11-16arm: Add support for Cortex-A78CPrzemyslaw Wirkus1-0/+1
This patch adds support for -mcpu=cortex-a78c command line option. For more information about this processor, see [0]: [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-1/+1
This patch adds support for AArch64 -march=armv8.7-a command line option in GAS. Please note that this change ONLY extends -march= command line interface with a new "armv8.7-a" option. Architectural changes like new instructions will be added in following patches. gas/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (armv8.7-a): New arch. * doc/c-aarch64.texi (-march=armv8.7-a): Update docs. include/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask. (AARCH64_ARCH_V8_7): New arch feature set. opcodes/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (ARMV8_7): New macro.
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-3/+8
gas/ * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags. (i386_align_code): Add PROCESSOR_ZNVER cases. * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync. * gas/i386/i386.exp: Add new znver3 test cases. * gas/i386/arch-14-znver3.d: New. * gas/i386/arch-14.d: New. * gas/i386/arch-14.s: New. * gas/i386/invlpgb.d: New. * gas/i386/invlpgb64.d: New. * gas/i386/invlpgb.s: New. * gas/i386/snp.d: New. * gas/i386/snp64.d: New. * gas/i386/snp.s: New. * gas/i386/tlbsync.d: New. * gas/i386/tlbsync.s: New. * gas/i386/x86-64-arch-4-znver3.d: New. * gas/i386/x86-64-arch-4.d: New. * gas/i386/x86-64-arch-4.s: New. opcodes/ * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb. * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS, CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS. Add CPU_ZNVER3_FLAGS. (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate, rmpupdate, rmpadjust. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-1/+7
Intel AVX VNNI instructions are marked with CpuVEX_PREFIX. Without the pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded with the EVEX prefix. The pseudo {vex} prefix can be used to encode mnemonics of Intel VNNI instructions with the VEX prefix. gas/ * NEWS: Add Intel AVX VNNI. * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni. (cpu_flags_match): Support CpuVEX_PREFIX. * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to encode Intel VNNI instructions with VEX prefix. * testsuite/gas/i386/avx-vnni.d: New file. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F3850): New. (PREFIX_VEX_0F3851): Likewise. (PREFIX_VEX_0F3852): Likewise. (PREFIX_VEX_0F3853): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3852_P_2): Likewise. (VEX_W_0F3853_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851, PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853. (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2, VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2. (putop): Add support for "XV" to print "{vex3}" pseudo prefix. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and CPU_ANY_AVX_VNNI_FLAGS. (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX. * i386-opc.h (CpuAVX_VNNI): New. (CpuVEX_PREFIX): Likewise. (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix. * i386-opc.tbl: Add Intel AVX VNNI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-1/+3
gas/ * NEWS: Add Intel HRESET. * config/tc-i386.c (cpu_arch): Add .hreset. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .hreset, nohreset. * testsuite/gas/i386/i386.exp: Run HRESET tests. * testsuite/gas/i386/hreset.d: New file. * testsuite/gas/i386/x86-64-hreset.d: Likewise. * testsuite/gas/i386/hreset.s: Likewise. opcodes/ * i386-dis.c (PREFIX_0F3A0F): New. (MOD_0F3A0F_PREFIX_1): Likewise. (REG_0F3A0F_PREFIX_1_MOD_3): Likewise. (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise. (prefix_table): Add PREFIX_0F3A0F. (mod_table): Add MOD_0F3A0F_PREFIX_1. (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3. (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0. * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS, CPU_ANY_HRESET_FLAGS. (cpu_flags): Add CpuHRESET. (output_i386_opcode): Allow 4 byte base_opcode. * i386-opc.h (enum): Add CpuHRESET. (i386_cpu_flags): Add cpuhreset. * i386-opc.tbl: Add Intel HRESET instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-14x86: Support Intel UINTRLili Cui1-1/+3
gas/ * NEWS: Add Intel UINTR. * config/tc-i386.c (cpu_arch): Add .uintr. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .uintr and nouintr. * testsuite/gas/i386/i386.exp: Run UINTR tests. * testsuite/gas/i386/x86-64-uintr.d: Likewise. * testsuite/gas/i386/x86-64-uintr.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_3_0F01_REG_5_RM_4, PREFIX_MOD_3_0F01_REG_5_RM_5, PREFIX_MOD_3_0F01_REG_5_RM_6, PREFIX_MOD_3_0F01_REG_5_RM_7, X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1. (prefix_table): New instructions (see prefixes above). (rm_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS, CPU_ANY_UINTR_FLAGS. (cpu_flags): Add CpuUINTR. * i386-opc.h (enum): Add CpuUINTR. (i386_cpu_flags): Add cpuuintr. * i386-opc.tbl: Add UINTR insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-05Fix spelling mistakesSamanta Navarro2-2/+2
2020-10-05GAS: Update the .section directive so that a numeric section index can be ↵Nick Clifton1-2/+5
provided when the "o" flag is used. PR 26253 gas * config/obj-elf.c (obj_elf_section): Accept a numeric value for the "o" section flag. Interpret it as a section index. Allow an index of zero. * doc/as.texi: Document the new behaviour. * NEWS: Mention the new feature. Tidy entries. * testsuite/gas/elf/sh-link-zero.s: New test. * testsuite/gas/elf/sh-link-zero.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/section21.l: Updated expected assembler output. bfd * elf.c (_bfd_elf_setup_sections): Do not complain about an sh_link value of zero when the SLF_LINK_ORDER flag is set. (assign_section_numbers): Likewise.
2020-10-02arm: add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+2
bfd/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * cpu-arm.c: Add cortex-a78 and cortex-a78ae. gas/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores. * doc/c-arm.texi: Update docs. * NEWS: Update news. * testsuite/gas/arm/cpu-cortex-a78.d: New test. * testsuite/gas/arm/cpu-cortex-a78ae.d: New test.
2020-10-01Add new directive to GAS: .attach_to_group.Nick Clifton1-1/+11
* config/obj-elf (elf_pseudo_table): Add attach_to_group. (obj_elf_attach_to_group): New function. * doc/as.texi: Document the new directive. * NEWS: Mention the new feature. * testsuite/gas/elf/attach-1.s: New test. * testsuite/gas/elf/attach-1.d: New test driver. * testsuite/gas/elf/attach-2.s: New test. * testsuite/gas/elf/attach-2.d: New test driver. * testsuite/gas/elf/attach-err.s: New test. * testsuite/gas/elf/attach-err.d: New test driver. * testsuite/gas/elf/attach-err.err: New test error output. * testsuite/gas/elf/elf.exp: Run the new tests.
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+2
* config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores. * doc/c-aarch64.texi: Update docs. * NEWS: Update news.
2020-09-30aarch64: Add support for Neoverse N2 CPUAlex Coplan1-0/+1
This patch adds support for Arm's Neoverse N2 CPU to AArch64 binutils. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2. * doc/c-aarch64.texi: Document support for Neoverse N2.
2020-09-28This patch adds support for Cortex-X1 for ARM.Przemyslaw Wirkus1-0/+1
bfd * cpu-arm.c: (processors) Add Cortex-X1. gas * config/tc-arm.c: (arm_cpus): Add Cortex-X1. * doc/c-arm.texi: Document -mcpu=cortex-x1. * testsuite/gas/arm/cpu-cortex-x1.d: New test.
2020-09-28This patch adds support for Cortex-X1Przemyslaw Wirkus1-1/+2
gas * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1. * doc/c-aarch64.texi: Document -mcpu=cortex-x1.
2020-09-24arm: Add support for Neoverse V1 CPUAlex Coplan1-0/+1
This patch adds support for Arm's Neoverse V1 CPU to AArch32 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse V1. * doc/c-arm.texi: Document Neoverse V1 support.
2020-09-24aarch64: Add support for Neoverse V1 CPUAlex Coplan1-0/+1
This adds support for Arm's Neoverse V1 CPU to AArch64 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1. * doc/c-aarch64.texi: Document Neoverse V1 support.
2020-09-24arm: Add support for Neoverse N2 CPUAlex Coplan1-0/+1
This adds support for Arm's Neoverse N2 CPU to AArch32 binutils. The Neoverse N2 CPU builds AArch32 at EL0 and therefore needs support in the AArch32 assembler. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse N2. * doc/c-arm.texi: Document -mcpu=neoverse-n2.
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+3
gas/ * NEWS: Add TDX. * config/tc-i386.c (cpu_arch): Add .tdx. (cpu_noarch): Likewise. * doc/c-i386.texi: Document tdx. * testsuite/gas/i386/i386.exp: Run tdx tests. * testsuite/gas/i386/tdx.d: Likewise. * testsuite/gas/i386/tdx.s: Likewise. * testsuite/gas/i386/x86-64-tdx.d: Likewise. * testsuite/gas/i386/x86-64-tdx.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, X86_64_0F01_REG_1_RM_7_P_2. (prefix_table): Likewise. (x86_64_table): Likewise. (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS and CPU_ANY_TDX_FLAGS. (cpu_flags): Add CpuTDX. * i386-opc.h (enum): Add CpuTDX. (i386_cpu_flags): Add cputdx. * i386-opc.tbl: Add TDX insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+5
gas/ * NEWS: Add Key Locker. * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. (cpu_noarch): Likewise. * doc/c-i386.texi: Document kl and wide_kl. * testsuite/gas/i386/i386.exp: Run keylocker tests. * testsuite/gas/i386/keylocker-intel.d: New test. * testsuite/gas/i386/keylocker.d: Likewise. * testsuite/gas/i386/keylocker.s: Likewise. * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.s: Likewise. * testsuite/gas/i386/x86-64-property-10.d: Likewise. * testsuite/gas/i386/property-10.d: Likewise. * testsuite/gas/i386/property-10.s: Likewise. opcodes/ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. (reg_table): New instructions (see prefixes above). (prefix_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. (cpu_flags): Likewise. (operand_type_init): Likewise. * i386-opc.h (enum): Add CpuKL and CpuWide_KL. (i386_cpu_flags): Add cpukl and cpuwide_kl. * i386-opc.tbl: Add KL and WIDE_KL insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-14Add a new ".nop" directive to the assembler to allow the creation of no-op ↵Nick Clifton2-11/+31
instructions in an architeture neutral manner. * read.c (s_nop): New function. Handles the .nop directive. (potable): Add entry for "nop". (s_nops): Code tidy. * read.h (s_nop): Add prototype. * config/tc-bpf.h (md_single_noop_insn): Define. * config/tc-mmix.h (md_single_noop_insn): Define. * config/tc-or1k.h (md_single_noop_insn): Define. * config/tc-s12z.c (md_assemble): Preserve the input line pointer, rather than corrupting it. * write.c (relax_segment): Update error message regarding non-absolute values passed to .fill and .nops. * NEWS: Mention the new directive. * doc/as.texi: Document the new directive. * doc/internals.texi: Document the new internal macros used to implement the new directive. * testsuite/gas/all/nop.s: New test. * testsuite/gas/all/nop.d: New test control file. * testsuite/gas/all/gas.exp: Run the new test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test control file. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/space1.l: Adjust expected output.
2020-09-11gas: Don't error when .debug_line already exists, unless .loc was usedMark Wielaard1-2/+5
When -g was used to generate DWARF gas would error out when a .debug_line already exists. But when a .debug_info section already exists it would simply skip generating one without warning or error. Do the same for .debug_line. It is only an error when the user explicitly uses .loc directives and also generates the .debug_line table itself. The tests are unfortunately arch specific because the line table is only generated when actual instructions have been emitted. Use i386 because that is probably the most used architecture. Before this patch the new dwarf-line-2 testcase would fail, with this patch it succeeds (and doesn't try to add its own line table). gas/ChangeLog: * as.texi (-g): Explicitly mention when .debug_info and .debug_line are generated for the DWARF format. (Loc): Add that it is an error to both use a .loc directive and generate a .debug_line yourself. * dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable. (dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE. (dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting an error. Only create .debug_line if it is empty (or doesn't exist). * testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing an elf target. * testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files.
2020-09-08aarch64: Add -mcpu option for Cortex-R82Alex Coplan1-1/+2
This adds support for the Arm Cortex-R82 CPU in AArch64 GAS. For more information about this processor, see [0]. [0] : https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82 gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add Cortex-R82. * doc/c-aarch64.texi: Document -mcpu=cortex-r82.
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-1/+1
This patch adds the basic infrastructure needed to support Armv8-R in AArch64 binutils: new command-line flags, new feature bits, a new BFD architecture, and support for differentiating between architecture variants in the disassembler. The new command-line options added by this patch are -march=armv8-r in GAS and -m aarch64:armv8-r in objdump. The disassembler support is necessary since Armv8-R AArch64 introduces a system register (VSCTLR_EL2) which shares an encoding with a different system register (TTBR0_EL2) in Armv8-A. This also allows us to use the correct preferred disassembly for the new DFB alias introduced in Armv8-R. bfd/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * archures.c (bfd_mach_aarch64_8R): New. * bfd-in2.h: Regenerate. * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. (bfd_aarch64_arch_ilp32): Update tail pointer. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_archs): Add armv8-r. * doc/c-aarch64.texi: Document -march=armv8-r. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. (AARCH64_FEATURE_V8_R): New. (AARCH64_ARCH_V8): Include new A-profile feature bit. (AARCH64_ARCH_V8_R): New. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (arch_variant): New. (determine_disassembling_preference): Disassemble according to arch variant. (select_aarch64_variant): New. (print_insn_aarch64): Set feature set.
2020-09-01ELF: Document the .tls_common directiveH.J. Lu1-0/+13
Document the .tls_common directive added by commit b8871f357fdfa9c0c06d2d3e5600391d8c994f37 Author: H.J. Lu <hjl.tools@gmail.com> Date: Mon Feb 22 09:18:52 2016 -0800 Properly implement STT_COMMON * doc/as.texi: Document the .tls_common directive.
2020-08-20Remove --reduce-memory-overheads and --hash-size arguments.Martin Liska2-45/+0
* NEWS: Mention --reduce-memory-overheads and --hash-size arguments options. * as.c: Remove the options from help. * doc/as.texi: Remove options. * doc/internals.texi: Remove hash from documentation. * hash.c (struct hash_entry): Remove. (struct hash_control): Likewise. (set_gas_hash_table_size): Likewise. (hash_new_sized): Likewise. (hash_new): Likewise. (hash_die): Likewise. (hash_lookup): Likewise. (hash_insert): Likewise. (hash_jam): Likewise. (hash_replace): Likewise. (hash_find): Likewise. (hash_find_n): Likewise. (hash_delete): Likewise. (hash_traverse): Likewise. (hash_print_statistics): Likewise. (TABLES): Likewise. (STATBUFSIZE): Likewise. (main): Likewise. (what): Likewise. (destroy): Likewise. (applicatee): Likewise. (whattable): Likewise. * hash.h (struct hash_control): Likewise. (set_gas_hash_table_size): Likewise. (hash_new): Likewise. (hash_new_sized): Likewise. (hash_die): Likewise. (hash_insert): Likewise. (hash_jam): Likewise. (hash_replace): Likewise. (hash_find): Likewise. (hash_find_n): Likewise. (hash_delete): Likewise. (hash_traverse): Likewise. (hash_print_statistics): Likewise.
2020-08-12The description for -mno-csr-check talks about "cheching" rather than ↵Nick Clifton1-1/+1
"checking". PR 26346 * doc/c-riscv.texi (RISC-V-Options): Fix typo in the description of the -mno-csr-check option.
2020-08-04gas: Fix as.texi typo infortmationMark Wielaard1-3/+3
gas/ChangeLog: * doc/as.texi (--gdwarf-[345]): Fix typo.
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-1/+4
Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo prefixes. gas/ PR gas/26305 * config/tc-i386.c (_i386_insn::disp_encoding): Add disp_encoding_16bit. (parse_insn): Check Prefix_XXX for pseudo prefixes. Handle {disp16}. (build_modrm_byte): Handle {disp16}. (i386_index_check): Check invalid {disp16} and {disp32} pseudo prefixes. * doc/c-i386.texi: Update {disp32} documentation and document {disp16}. * testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo. * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16} tests. * testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps tests with 128-byte displacement. Add {disp16} tests. * testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32} vmovaps test. Add (%r13)/(%r13d) tests. * testsuite/gas/i386/x86-64-inval-pseudo.l: New file. * testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise. * testsuite/gas/i386/inval-pseudo.l: Updated. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/26305 * i386-opc.h (Prefix_Disp8): New. (Prefix_Disp16): Likewise. (Prefix_Disp32): Likewise. (Prefix_Load): Likewise. (Prefix_Store): Likewise. (Prefix_VEX): Likewise. (Prefix_VEX3): Likewise. (Prefix_EVEX): Likewise. (Prefix_REX): Likewise. (Prefix_NoOptimize): Likewise. * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}. * i386-tbl.h: Regenerated.
2020-07-30Unify Solaris procfs and largefile handlingRainer Orth1-0/+1
GDB currently doesn't build on 32-bit Solaris: * On Solaris 11.4/x86: In file included from /usr/include/sys/procfs.h:26, from /vol/src/gnu/gdb/hg/master/dist/gdb/i386-sol2-nat.c:24: /usr/include/sys/old_procfs.h:31:2: error: #error "Cannot use procfs in the large file compilation environment" #error "Cannot use procfs in the large file compilation environment" ^~~~~ * On Solaris 11.3/x86 there are several more instances of this. The interaction between procfs and large-file support historically has been a royal mess on Solaris: * There are two versions of the procfs interface: ** The old ioctl-based /proc, deprecated and not used any longer in either gdb or binutils. ** The `new' (introduced in Solaris 2.6, 1997) structured /proc. * There are two headers one can possibly include: ** <procfs.h> which only provides the structured /proc, definining _STRUCTURED_PROC=1 and then including ... ** <sys/procfs.h> which defaults to _STRUCTURED_PROC=0, the ioctl-based /proc, but provides structured /proc if _STRUCTURED_PROC == 1. * procfs and the large-file environment didn't go well together: ** Until Solaris 11.3, <sys/procfs.h> would always #error in 32-bit compilations when the large-file environment was active (_FILE_OFFSET_BITS == 64). ** In both Solaris 11.4 and Illumos, this restriction was lifted for structured /proc. So one has to be careful always to define _STRUCTURED_PROC=1 when testing for or using <sys/procfs.h> on Solaris. As the errors above show, this isn't always the case in binutils-gdb right now. Also one may need to disable large-file support for 32-bit compilations on Solaris. config/largefile.m4 meant to do this by wrapping the AC_SYS_LARGEFILE autoconf macro with appropriate checks, yielding ACX_LARGEFILE. Unfortunately the macro doesn't always succeed because it neglects the _STRUCTURED_PROC part. To make things even worse, since GCC 9 g++ predefines _FILE_OFFSET_BITS=64 on Solaris. So even if largefile.m4 deciced not to enable large-file support, this has no effect, breaking the gdb build. This patch addresses all this as follows: * All tests for the <sys/procfs.h> header are made with _STRUCTURED_PROC=1, the definition going into the various config.h files instead of having to make them (and sometimes failing) in the affected sources. * To cope with the g++ predefine of _FILE_OFFSET_BITS=64, -U_FILE_OFFSET_BITS is added to various *_CPPFLAGS variables. It had been far easier to have just #undef _FILE_OFFSET_BITS in config.h, but unfortunately such a construct in config.in is commented by config.status irrespective of indentation and whitespace if large-file support is disabled. I found no way around this and putting the #undef in several global headers for bfd, binutils, ld, and gdb seemed way more invasive. * Last, the applicability check in largefile.m4 was modified only to disable largefile support if really needed. To do so, it checks if <sys/procfs.h> compiles with _FILE_OFFSET_BITS=64 defined. If it doesn't, the disabling only happens if gdb exists in-tree and isn't disabled, otherwise (building binutils from a tarball), there's no conflict. What initially confused me was the check for $plugins here, which originally caused the disabling not to take place. Since AC_PLUGINGS does enable plugin support if <dlfcn.h> exists (which it does on Solaris), the disabling never happened. I could find no explanation why the linker plugin needs large-file support but thought it would be enough if gld and GCC's lto-plugin agreed on the _FILE_OFFSET_BITS value. Unfortunately, that's not enough: lto-plugin uses the simple-object interface from libiberty, which includes off_t arguments. So to fully disable large-file support would mean also disabling it in libiberty and its users: gcc and libstdc++-v3. This seems highly undesirable, so I decided to disable the linker plugin instead if large-file support won't work. The patch allows binutils+gdb to build on i386-pc-solaris2.11 (both Solaris 11.3 and 11.4, using GCC 9.3.0 which is the worst case due to predefined _FILE_OFFSET_BITS=64). Also regtested on amd64-pc-solaris2.11 (again on Solaris 11.3 and 11.4), x86_64-pc-linux-gnu and i686-pc-linux-gnu. config: * largefile.m4 (ACX_LARGEFILE) <sparc-*-solaris*|i?86-*-solaris*>: Check for <sys/procfs.h> incompatilibity with large-file support on Solaris. Only disable large-file support and perhaps plugins if needed. Set, substitute LARGEFILE_CPPFLAGS if so. bfd: * bfd.m4 (BFD_SYS_PROCFS_H): New macro. (BFD_HAVE_SYS_PROCFS_TYPE): Require BFD_SYS_PROCFS_H. Don't define _STRUCTURED_PROC. (BFD_HAVE_SYS_PROCFS_TYPE_MEMBER): Likewise. * elf.c [HAVE_SYS_PROCFS_H] (_STRUCTURED_PROC): Don't define. * configure.ac: Use BFD_SYS_PROCFS_H to check for <sys/procfs.h>. * configure, config.in: Regenerate. * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS. * Makefile.in, doc/Makefile.in: Regenerate. binutils: * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS. * Makefile.in, doc/Makefile.in: Regenerate. * configure: Regenerate. gas: * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS. * Makefile.in, doc/Makefile.in: Regenerate. * configure: Regenerate. gdb: * proc-api.c (_STRUCTURED_PROC): Don't define. * proc-events.c: Likewise. * proc-flags.c: Likewise. * proc-why.c: Likewise. * procfs.c: Likewise. * Makefile.in (INTERNAL_CPPFLAGS): Add LARGEFILE_CPPFLAGS. * configure, config.in: Regenerate. gdbserver: * configure, config.in: Regenerate. gdbsupport: * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS. * common.m4 (GDB_AC_COMMON): Use BFD_SYS_PROCFS_H to check for <sys/procfs.h>. * Makefile.in: Regenerate. * configure, config.in: Regenerate. gnulib: * configure.ac: Run ACX_LARGEFILE before gl_EARLY. * configure: Regenerate. gprof: * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS. * Makefile.in: Regenerate. * configure: Regenerate. ld: * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS. * Makefile.in: Regenerate. * configure: Regenerate.
2020-07-28x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)H.J. Lu1-1/+1
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. Note: Since there is no disp32 on 0(%bp), use disp16 instead. PR gas/26305 * config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on (%bp)/(%ebp)/(%rbp) for {disp32}. * doc/c-i386.texi: Update {disp32} documentation. * testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests. * testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests. * testsuite/gas/i386/pseudos.d: Updated. * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
2020-07-27doc: Replace preceeded with precededH.J. Lu1-1/+1
binutils/ * doc/binutils.texi: Replace preceeded with preceded. gas/ * doc/as.texi: Replace preceeded with preceded.
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+7
gas/ * doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile. * config/tc-i386.c (i386_error): Add invalid_sib_address. (cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile. (cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile. (match_simd_size): Add tmmword check. (operand_type_match): Add tmmword. (type_names): Add rTMM. (i386_error): Add invalid_tmm_register_set. (check_VecOperands): Handle invalid_sib_address and invalid_tmm_register_set. (match_template): Handle invalid_sib_address. (build_modrm_byte): Handle non-vector SIB and zmmword. (i386_index_check): Disallow RegIP for non-vector SIB. (check_register): Handle zmmword. * testsuite/gas/i386/i386.exp: Add AMX new tests. * testsuite/gas/i386/intel-regs.d: Add tmm. * testsuite/gas/i386/intel-regs.s: Add tmm. * testsuite/gas/i386/x86-64-amx-intel.d: New. * testsuite/gas/i386/x86-64-amx-inval.l: New. * testsuite/gas/i386/x86-64-amx-inval.s: New. * testsuite/gas/i386/x86-64-amx.d: New. * testsuite/gas/i386/x86-64-amx.s: New. * testsuite/gas/i386/x86-64-amx-bad.d: New. * testsuite/gas/i386/x86-64-amx-bad.s: New. opcodes/ * i386-dis.c (TMM): New. (EXtmm): Likewise. (VexTmm): Likewise. (MVexSIBMEM): Likewise. (tmm_mode): Likewise. (vex_sibmem_mode): Likewise. (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise. (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise. (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise. (PREFIX_VEX_0F3849_X86_64): Likewise. (PREFIX_VEX_0F384B_X86_64): Likewise. (PREFIX_VEX_0F385C_X86_64): Likewise. (PREFIX_VEX_0F385E_X86_64): Likewise. (X86_64_VEX_0F3849): Likewise. (X86_64_VEX_0F384B): Likewise. (X86_64_VEX_0F385C): Likewise. (X86_64_VEX_0F385E): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise. (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F3849_X86_64_P_0): Likewise. (VEX_W_0F3849_X86_64_P_2): Likewise. (VEX_W_0F3849_X86_64_P_3): Likewise. (VEX_W_0F384B_X86_64_P_1): Likewise. (VEX_W_0F384B_X86_64_P_2): Likewise. (VEX_W_0F384B_X86_64_P_3): Likewise. (VEX_W_0F385C_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_0): Likewise. (VEX_W_0F385E_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_2): Likewise. (VEX_W_0F385E_X86_64_P_3): Likewise. (names_tmm): Likewise. (att_names_tmm): Likewise. (intel_operand_size): Handle void_mode. (OP_XMM): Handle tmm_mode. (OP_EX): Likewise. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (operand_type_shorthands): Add RegTMM. (operand_type_init): Likewise. (operand_types): Add Tmmword. (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. * i386-opc.h (CpuAMX_INT8): New. (CpuAMX_BF16): Likewise. (CpuAMX_TILE): Likewise. (SIBMEM): Likewise. (Tmmword): Likewise. (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile. (i386_opcode_modifier): Extend width of fields vexvvvv and sib. (i386_operand_type): Add tmmword. * i386-opc.tbl: Add AMX instructions. * i386-reg.tbl: Add AMX registers. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-07-07x86: Remove an incorrect AVX2 entryH.J. Lu1-10/+0
The upper 16 vector registers were added by AVX512. PR gas/26212 * doc/c-i386.texi: Remove an incorrect AVX2 entry.
2020-06-26m68k: tag floating-point ABI usedPat Bernardi1-0/+16
This patch adds GNU attribute support to m68k and utilises it to tag the floating-point calling convention used (hard-float or soft-float). It enables the linker to ensure linked objects use a consistent floating-point ABI and allows tools like GDB to infer the ABI used from the ELF file. It is based on similar work done for PowerPC. bfd/ * elf32-m68k.c (m68k_elf_merge_obj_attributes): New function. (elf32_m68k_merge_private_bfd_data): Merge GNU attributes. binutils/ * readelf.c (display_m68k_gnu_attribute): New function. (process_arch_specific): Call display_m68k_gnu_attribute for EM_68K. gas/ * config/tc-m68k.c (m68k_elf_gnu_attribute): New function. (md_pseudo_table): Handle "gnu_attribute". * doc/as.texi: Document GNU attribute for M68K. include/ * elf/m68k.h: Add enum for GNU object attribute with floating point tag name and values. ld/ * testsuite/ld-m68k/attr-gnu-4-0.s: New file. * testsuite/ld-m68k/attr-gnu-4-1.s: Likewise. * testsuite/ld-m68k/attr-gnu-4-2.s: Likewise. * testsuite/ld-m68k/attr-gnu-4-00.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-01.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-02.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-10.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-11.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-12.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-20.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-21.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-22.d: Likewise. * testsuite/ld-m68k/m68k.exp: Run the new tests.
2020-06-16x86: Correct noavx512_vp2intersectCui,Lili1-0/+1
* config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS. * doc/c-i386.texi: Add avx512_vp2intersect.
2020-06-15xtensa: allow runtime ABI selectionMax Filippov2-0/+9
2020-06-15 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED) (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New global variable. (xtensa_abi_choice): New function. (elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of XSHAL_ABI to select PLT code. gas/ * config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (option_abi_windowed, option_abi_call0): New enum constants. (md_longopts): Add entries for --abi-windowed and --abi-call0. (md_parse_option): Add handlers for --abi-windowed and --abi-call0. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. * doc/as.texi (Target Xtensa options): Add --abi-windowed and --abi-call0 to the list of options. * doc/c-xtensa.texi: Add description for options --abi-windowed and --abi-call0. * testsuite/gas/xtensa/abi-call0.d: New test definition. * testsuite/gas/xtensa/abi-windowed.d: New test definition. * testsuite/gas/xtensa/abi.s: New test source. include/ * elf/xtensa.h (xtensa_abi_choice): New declaration. ld/ * emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition. (XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test ABI tag consistency. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. (PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED, OPTION_ABI_CALL0 and declare elf32xtensa_abi. (PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and --abi-call0. (PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and --abi-call0. (PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and --abi-call0. * ld.texi: Add description for options --abi-windowed and --abi-call0.
2020-06-09[PATCH] gas/doc: improve AVR modifiers wording.Seth Girvan1-14/+23
* doc/c-avr.texi: Improve wording.
2020-06-06Power10 tidiesAlan Modra1-0/+3
binutils/ * doc/binutils.texi (PowerPC -M option): Mention power10 and pwr10. gas/ * config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2020-06-03* gas/doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe.Stephen Casner1-1/+1
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