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2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu1-0/+13
2020-02-19RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.Nelson Chu1-0/+14
2020-02-19Various fixes for the Z80 support.Sergey Belyashov2-98/+34
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-5/+6
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-1/+3
2020-02-14Remove the old movsx and movzx documentation for AT&T syntaxH.J. Lu1-16/+0
2020-02-14x86: Document movsx/movsxd/movzx for AT&T syntaxH.J. Lu1-0/+53
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-0/+12
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson1-0/+8
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu1-1/+2
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ...Sergey Belyashov1-7/+15
2020-02-06ELF: Support the section flag 'o' in .section directiveH.J. Lu1-0/+27
2020-02-02ELF: Add support for unique section ID to assemblerH.J. Lu1-0/+12
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu1-0/+18
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich1-0/+25
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu1-2/+2
2020-01-14Fix various assembler testsuite failures for the Z80 target.Sergey Belyashov2-103/+121
2020-01-08Document the fact that the assembler's alignment pseudo-ops can be issued wit...Nick Clifton1-9/+12
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. A...Sergey Belyashov2-33/+131
2020-01-01Update year range in copyright notice of binutils filesAlan Modra65-67/+67
2019-12-17Remove tic80 supportAlan Modra1-1/+1
2019-12-12i386: Add -mbranches-within-32B-boundariesH.J. Lu1-0/+11
2019-12-12i386: Align branches within a fixed boundaryH.J. Lu1-0/+26
2019-12-12gas: Add md_generic_table_relax_fragH.J. Lu1-0/+5
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess1-0/+6
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson1-0/+1
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+6
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson1-0/+2
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+2
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-1/+1
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-1/+4
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel2-3/+4
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz2-0/+29
2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi1-1/+0
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell1-0/+1
2019-08-22Arm: Add support for missing CPUsDennis Zhang1-0/+3
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point n...Barnaby Wilks1-0/+8
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77...Dennis Zhang1-0/+5
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating poi...Barnaby Wilks1-0/+33
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford1-1/+1
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi1-0/+23
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi1-8/+8
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson1-5/+9
2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich1-0/+4
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-1/+2
2019-07-01Document the .value directive supported by the x86 and x86_64 assemblers.Nick Clifton1-0/+6
2019-07-01Correct a typo in the description of the Align and P2align directives.Nick Clifton1-2/+2
2019-07-01Fix spelling error in assembler documentation.Nick Clifton1-1/+1
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-1/+2
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-1/+4
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