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2020-07-09Remove powerpc PE supportAlan Modra3-883/+15
Plus some leftover powerpc lynxos support. bfd/ * coff-ppc.c: Delete. * pe-ppc.c: Delete. * pei-ppc.c: Delete. * Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Remove PE PPC. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags): Remove PPCMAGIC code. (coff_write_object_contents): Remove PPC_PE code. * config.bfd: Move powerpcle-pe to removed targets. * configure.ac: Remove powerpc PE entries. * libcoff-in.h (ppc_allocate_toc_section): Delete. (ppc_process_before_allocation): Delete. * peXXigen.c: Remove POWERPC_LE_PE code and comments. * targets.c: Remove powerpc PE vectors. * po/SRC-POTFILES.in: Regenerate. * libcoff.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * dlltool.c: Remove powerpc PE support and comments. * configure.ac: Remove powerpc PE dlltool config. * configure: Regenerate. gas/ * config/obj-coff.h: Remove TE_PE support. * config/tc-ppc.c: Likewise. * config/tc-ppc.h: Likewise. * configure.tgt: Remove powerpc PE and powerpc lynxos. * testsuite/gas/cfi/cfi.exp (cfi-common-6): Remove powerpc PE condition. * testsuite/gas/macros/macros.exp: Don't xfail powerpc PE. include/ * coff/powerpc.h: Delete. ld/ * emulparams/ppcpe.sh: Delete. * scripttempl/ppcpe.sc: Delete. * emulparams/ppclynx.sh: Delete. * Makefile.am (ALL_EMULATION_SOURCES): Remove ppc PE and lynxos. * configure.tgt: Likewise. * emultempl/beos.em: Remove powerpc PE support. * emultempl/pe.em: Likewise. * po/BLD-POTFILES.in: Regenerate. * Makefile.in: Regenerate.
2020-07-07arc: Improve error messages when assemblingClaudiu Zissulescu1-18/+42
gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): Add error messages. * testsuite/gas/arc/add_s-err.s: Update test. * testsuite/gas/arc/asm-errors.err: Likewise. * testsuite/gas/arc/cpu-em-err.s: Likewise. * testsuite/gas/arc/hregs-err.s: Likewise. * testsuite/gas/arc/warn.s: Likewise.
2020-07-06Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton3-6/+6
PR 26204 gas * config/tc-arm.c: Fix spelling mistake. * config/tc-riscv.c: Likewise. * config/tc-z80.c: Likewise. * po/gas.pot: Regenerate. ld * lexsup.c: Fix spelling mistake. * po/ld.pot: Regenerate. opcodes * arc-dis.c: Fix spelling mistake. * po/opcodes.pot: Regenerate.
2020-07-02x86: Add SwapSourcesH.J. Lu1-4/+2
We check register-only source operand to decide if two source operands of VEX encoded instructions should be swapped. But source operands in AMX instructions with two source operands swapped are all register-only operand. Add SwapSources to indicate two source operands should be swapped. gas/ * config/tc-i386.c (build_modrm_byte): Check vexswapsources to swap two source operands. opcodes/ * i386-gen.c (opcode_modifiers): Add VexSwapSources. * i386-opc.h (VexSwapSources): New. (i386_opcode_modifier): Add vexswapsources. * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions with two source operands swapped. * i386-tbl.h: Regenerated.
2020-07-02aarch64: Fix segfault on unicode symbolsAlex Coplan1-1/+1
This patch fixes a segfault which occurs when the AArch64 backend parses a symbol operand that begins with a register name and ends with a unicode byte (byte value > 127). For example, the following input causes the crash: x0é: udf x0é gas/ChangeLog: 2020-07-02 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (reg_name_p): Fix cast so that we don't segfault on negative chars. * testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test. * testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
2020-07-01obsolete xc16xAlan Modra1-0/+2
The xc16x md_apply_fix code is just so broken that in my opinion the target should never have been accepted, and from a quick look at commit logs for the target it appears that no one has ever contributed fixes for anything. This target has just been a 14 year burden on global binutils and cgen maintainers. That's not how free software is supposed to work. bfd/ * config.bfd: Obsolete xc16x. gas/ * config/tc-xc16x.c (md_apply_fix): Add FIXME.
2020-06-30Remove x86 NaCl target supportH.J. Lu2-5/+0
NaCl has been deprecated: https://developer.chrome.com/native-client/migration and NaCl will completely disappear in 2021: https://lists.llvm.org/pipermail/llvm-dev/2020-April/141107.html Remove x86 NaCl target support from bfd, binutils, gas and ld. bfd/ * archures.c (bfd_mach_i386_nacl): Removed. (bfd_mach_i386_i386_nacl): Likewise. (bfd_mach_x86_64_nacl): Likewise. (bfd_mach_x64_32_nacl): Likewise. * config.bfd: Remove *-*-nacl* targets. * configure.ac: Remove x86 NaCl target vectors. * cpu-i386.c (bfd_arch_i386_onebyte_nop_fill): Removed. (bfd_x64_32_nacl_arch): Likewise. (bfd_x86_64_nacl_arch): Likewise. (bfd_i386_nacl_arch): Likewise. (bfd_x64_32_arch_intel_syntax): Updated. * elf32-i386.c: Don't include "elf-nacl.h". (elf_i386_nacl_plt): Removed. (elf_i386_nacl_plt0_entry): Likewise. (elf_i386_nacl_plt_entry): Likewise. (elf_i386_nacl_pic_plt0_entry): Likewise. (elf_i386_nacl_pic_plt_entry): Likewise. (elf_i386_nacl_eh_frame_plt): Likewise. (elf_i386_nacl_plt): Likewise. (elf32_i386_nacl_elf_object_p): Likewise. (elf_i386_get_synthetic_symtab): Updated. (elf_i386_link_setup_gnu_properties): Likewise. * elf64-x86-64.c: Don't include "elf-nacl.h". (elf_x86_64_nacl_plt): Removed. (elf64_x86_64_nacl_elf_object_p): Likewise. (elf_x86_64_nacl_plt0_entry): Likewise. (elf_x86_64_nacl_plt_entry): Likewise. (elf_x86_64_nacl_eh_frame_plt): Likewise. (elf_x86_64_nacl_plt): Likewise. (elf32_x86_64_nacl_elf_object_p): Likewise. (elf_x86_64_get_synthetic_symtab): Updated. (elf_x86_64_link_setup_gnu_properties): Likewise. * elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Likewise. * targets.c: Remove x86 NaCl target vectors. * bfd-in2.h: Regenerated. * configure: Likewise. binutils/ * NEWS: Mention x86 NaCl target support removal. * dwarf.c (init_dwarf_regnames_by_bfd_arch_and_mach): Remove x86 NaCl target support. * testsuite/binutils-all/elfedit-1.d: Likewise. * testsuite/binutils-all/i386/i386.exp: Likewise. * testsuite/binutils-all/x86-64/objects.exp: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/x86-64.exp: Likewise. gas/ * NEWS: Mention x86 NaCl target support removal. * config/tc-i386.c: Remove x86 NaCl target support. * config/tc-i386.h: Likewise. * configure.tgt: Likewise. * testsuite/gas/i386/i386.exp: Likewise. * testsuite/gas/i386/iamcu-1.d: Likewise. * testsuite/gas/i386/iamcu-2.d: Likewise. * testsuite/gas/i386/iamcu-3.d: Likewise. * testsuite/gas/i386/iamcu-4.d: Likewise. * testsuite/gas/i386/iamcu-5.d: Likewise. * testsuite/gas/i386/k1om.d: Likewise. * testsuite/gas/i386/l1om.d: Likewise. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_nacl.c, eelf32_x86_64_nacl.c, eelf_x86_64_nacl.c. Remove x86 NaCl dep files. * NEWS: Mention x86 NaCl target support removal. * configure.tgt: Remove x86 NaCl target support. * testsuite/ld-elf/binutils.exp: Likewise. * testsuite/ld-elf/elf.exp: Likewise. * testsuite/ld-elfvers/vers.exp: Likewise. * testsuite/ld-i386/align-branch-1.d: Likewise. * testsuite/ld-i386/export-class.exp: Likewise. * testsuite/ld-i386/i386.exp: Likewise. * testsuite/ld-i386/load1.d: Likewise. * testsuite/ld-i386/pie1.d: Likewise. * testsuite/ld-i386/pr12570a.d: Likewise. * testsuite/ld-i386/pr12570b.d: Likewise. * testsuite/ld-i386/pr19636-1d.d: Likewise. * testsuite/ld-i386/pr19636-1l.d: Likewise. * testsuite/ld-i386/pr19636-2c.d: Likewise. * testsuite/ld-i386/pr19636-2d.d: Likewise. * testsuite/ld-i386/pr19636-2e.d: Likewise. * testsuite/ld-i386/pr20244-1a.d: Likewise. * testsuite/ld-i386/pr20244-1b.d: Likewise. * testsuite/ld-i386/pr20244-2a.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Likewise. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-i386/pr20244-4a.d: Likewise. * testsuite/ld-i386/pr20244-4b.d: Likewise. * testsuite/ld-i386/pr21884.d: Likewise. * testsuite/ld-ifunc/binutils.exp: Likewise. * testsuite/ld-ifunc/ifunc-10-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-10-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-11-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-11-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-12-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-12-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-13-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-13-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14c-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14c-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14d-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14d-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14e-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14e-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14f-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14f-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-15-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-15-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-16-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-16-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-16-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-16-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-17a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-17a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-17b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-17b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-19a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-19a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-19b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-19b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-20-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-20-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-21-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-6a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-6a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-6b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-6b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-7a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-7a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-7b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-7b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-8-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-8-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-9-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-9-x86-64.d: Likewise. * testsuite/ld-ifunc/pr17154-i386-now.d: Likewise. * testsuite/ld-ifunc/pr17154-i386.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64-now.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64.d: Likewise. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/ld-x86-64/align-branch-1.d: Likewise. * testsuite/ld-x86-64/dwarfreloc.exp: Likewise. * testsuite/ld-x86-64/line.exp: Likewise. * testsuite/ld-x86-64/load1a.d: Likewise. * testsuite/ld-x86-64/load1b.d: Likewise. * testsuite/ld-x86-64/load1c.d: Likewise. * testsuite/ld-x86-64/load1d.d: Likewise. * testsuite/ld-x86-64/pie3.d: Likewise. * testsuite/ld-x86-64/pr18160.d: Likewise. * testsuite/ld-x86-64/pr19013-x32.d: Likewise. * testsuite/ld-x86-64/pr19013.d: Likewise. * testsuite/ld-x86-64/pr19636-2d.d: Likewise. * testsuite/ld-x86-64/pr19636-2l.d: Likewise. * testsuite/ld-x86-64/pr20253-1b.d: Likewise. * testsuite/ld-x86-64/pr20253-1d.d: Likewise. * testsuite/ld-x86-64/pr20253-1f.d: Likewise. * testsuite/ld-x86-64/pr20253-1h.d: Likewise. * testsuite/ld-x86-64/pr20253-1j.d: Likewise. * testsuite/ld-x86-64/pr20253-1l.d: Likewise. * testsuite/ld-x86-64/pr21884.d: Likewise. * testsuite/ld-x86-64/pr22393-3a.rd: Likewise. * testsuite/ld-x86-64/pr22393-3b.rd: Likewise. * testsuite/ld-x86-64/tlsgd10.dd: Likewise. * testsuite/ld-x86-64/tlsgd5.dd: Likewise. * testsuite/ld-x86-64/tlsgd8.dd: Likewise. * testsuite/ld-x86-64/x86-64.exp: Likewise. * emulparams/elf32_x86_64_nacl.sh: Removed. * emulparams/elf_i386_nacl.sh: Likewise. * emulparams/elf_x86_64_nacl.sh: Likewise. * testsuite/ld-i386/emit-relocs-nacl.rd: Likewise. * testsuite/ld-i386/load1-nacl.d: Likewise. * testsuite/ld-i386/pie1-nacl.d: Likewise. * testsuite/ld-i386/plt-nacl.pd: Likewise. * testsuite/ld-i386/plt-pic-nacl.pd: Likewise. * testsuite/ld-i386/pr17709-nacl.rd: Likewise. * testsuite/ld-i386/pr19636-1d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2c-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2e-nacl.d: Likewise. * testsuite/ld-i386/pr19827-nacl.rd: Likewise. * testsuite/ld-i386/pr21884-nacl.d: Likewise. * testsuite/ld-i386/pr21884-nacl.t: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic2-nacl.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/load1a-nacl.d: Likewise. * testsuite/ld-x86-64/load1b-nacl.d: Likewise. * testsuite/ld-x86-64/load1c-nacl.d: Likewise. * testsuite/ld-x86-64/load1d-nacl.d: Likewise. * testsuite/ld-x86-64/pie3-nacl.d: Likewise. * testsuite/ld-x86-64/plt-nacl.pd: Likewise. * testsuite/ld-x86-64/pr17709-nacl.rd: Likewise. * testsuite/ld-x86-64/pr19013-nacl.d: Likewise. * testsuite/ld-x86-64/pr19636-2d-nacl.d: Likewise. * testsuite/ld-x86-64/pr19827-nacl.rd: Likewise. * testsuite/ld-x86-64/pr21884-nacl.d: Likewise. * testsuite/ld-x86-64/pr21884-nacl.t: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.pd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise. * Makefile.in: Regenerated. * po/BLD-POTFILES.in: Likewise.
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu1-29/+24
The unprivileged CSR should be controlled by other specific specs rather than the privileged spec. For example, the debug CSR should be controlled by the debug spec, and the float CSR should be controlled by the float spec. User may use assembler options to choose what the debug and other specs they want, or may encode the versions of specs into the architecture string directly. Since we haven't decided which one is better, we set the defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec versions for them. However, these PRIV_SPEC_CLASS_NONE will be changed to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future. gas/ * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the checking into riscv_csr_address. (riscv_csr_version_check): Likewise. (riscv_csr_address): New function. Return the suitable CSR address after checking the ISA dependency and versions. Issue warnings if we find any conflict and -mcsr-check is set. CSR_CLASS_F and CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the priv spec versions for them. (reg_csr_lookup_internal): Call riscv_csr_address to find the suitable CSR address. * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the priv spec warnings here. These warnings are added by accident. Remove them and only focus on the ISA dependency warnings. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since dscratch0 and dscratch1 are regarded as the unprivileged CSR rather than the privileged ones. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. include/ * opcode/riscv-opc.h: Support the unprivileged CSR. The versions of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now. * opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG. opcodes/ * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the unprivileged CSR can also be initialized.
2020-06-29x86: Support VEX base opcode length > 1H.J. Lu1-6/+2
Intel AMX instructions with 8-bit immediate opcode extension without operands: tilerelease, 0, 0x49c0, None, 2, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } Update build_vex_prefix to support VEX base opcode length > 1. * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1. (md_assemble): Don't process ImmExt without operands.
2020-06-29gas: Fix mmix fixups and TC_FX_SIZE_SLACK, PR25331Hans-Peter Nilsson2-6/+16
Finally; sorry for the delay. There were a few false starts, where I misinterpreted the error-messages and the comment that Alan added: it's not the fix size that's too large (and the frag too small), it's stating the wrong size of what will be "fixed up" - that of the actual target value, not the size of the field that needs to be adjusted. Comments added for clarity. Test-suite committed separately. gas: PR gas/25331 * config/tc-mmix.c (md_assemble) <fixup for BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8. Also, set its fx_no_overflow. (md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>: Similarly this fixup affects 4 bytes, not 8 and needs its fx_no_overflow set. * config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
2020-06-29C++ commentsAlan Modra3-20/+11
binutils isn't c99 (yet). This replaces or removes some C++ style comments. bfd/ * arc-got.h: Use C style comments. * coff-z80.c: Likewise. * elf32-csky.c: Likewise. * peXXigen.c: Likewise. * elf32-m32c.c (m32c_elf_relax_delete_bytes): Remove commented out code. binutils/ * dwarf.c: Use C style comments. * resrc.c: Likewise. gas/ * config/tc-s12z.c: Use C style comments. * config/tc-z80.c: Likewise. * config/tc-xtensa.c (emit_ld_r_n): Remove commented out code. include/ * coff/internal.h: Use C style comments. * coff/pe.h: Likewise. * elf/ppc64.h: Likewise. opcodes/ * arm-dis.c: Use C style comments. * cr16-opc.c: Likewise. * ft32-dis.c: Likewise. * moxie-opc.c: Likewise. * tic54x-dis.c: Likewise. * s12z-opc.c: Remove useless comment. * xgate-dis.c: Likewise.
2020-06-26x86: Process ImmExt without operandsH.J. Lu1-1/+5
To support Intel AMX instructions with 8-bit immediate opcode extension, but without operands: tilerelease, 0, 0x49, 0xc0, 1, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } process ImmExt without operands. * config/tc-i386.c (md_assemble): Process ImmExt without operands.
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-14/+14
Rename VecSIB to SIB to support Intel Advanced Matrix Extensions which introduces instructions with a mandatory SIB byte which isn't a vector SIB (VSIB). gas/ * config/tc-i386.c (check_VecOperands): Replace vecsib with sib. Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128, VECSIB256 and VECSIB512, respectively. (build_modrm_byte): Replace vecsib with sib. opcodes/ * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB. (VecSIB128): Renamed to ... (VECSIB128): This. (VecSIB256): Renamed to ... (VECSIB256): This. (VecSIB512): Renamed to ... (VECSIB512): This. (VecSIB): Renamed to ... (SIB): This. (i386_opcode_modifier): Replace vecsib with sib. * i386-opc.tbl (VexSIB128): New. (VecSIB256): Likewise. (VecSIB512): Likewise. Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256 and VecSIB512, respectively.
2020-06-26m68k: tag floating-point ABI usedPat Bernardi1-0/+20
This patch adds GNU attribute support to m68k and utilises it to tag the floating-point calling convention used (hard-float or soft-float). It enables the linker to ensure linked objects use a consistent floating-point ABI and allows tools like GDB to infer the ABI used from the ELF file. It is based on similar work done for PowerPC. bfd/ * elf32-m68k.c (m68k_elf_merge_obj_attributes): New function. (elf32_m68k_merge_private_bfd_data): Merge GNU attributes. binutils/ * readelf.c (display_m68k_gnu_attribute): New function. (process_arch_specific): Call display_m68k_gnu_attribute for EM_68K. gas/ * config/tc-m68k.c (m68k_elf_gnu_attribute): New function. (md_pseudo_table): Handle "gnu_attribute". * doc/as.texi: Document GNU attribute for M68K. include/ * elf/m68k.h: Add enum for GNU object attribute with floating point tag name and values. ld/ * testsuite/ld-m68k/attr-gnu-4-0.s: New file. * testsuite/ld-m68k/attr-gnu-4-1.s: Likewise. * testsuite/ld-m68k/attr-gnu-4-2.s: Likewise. * testsuite/ld-m68k/attr-gnu-4-00.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-01.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-02.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-10.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-11.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-12.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-20.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-21.d: Likewise. * testsuite/ld-m68k/attr-gnu-4-22.d: Likewise. * testsuite/ld-m68k/m68k.exp: Run the new tests.
2020-06-25Stop the assembler from generating R_ARM_THM_JMP11 relocations as these are ↵Nick Clifton1-0/+1
not supported by the kernel. PR 26141 * config/tc-arm.c (arm_force_relocation): Force resolution of BFD_RELOC_THUMB_PCREL_BRANCH12 relocations. * testsuite/gas/arm/plt-1.d: Adjust expected disassembly.
2020-06-25x86: move ImmExt processingJan Beulich1-5/+3
With abuses of ImmExt gone, all templates using it have operands. Move its main invocation into process_operands(), matching its secondary one for the SSE2AVX case.
2020-06-25x86: operand sizing prefixes can disambiguate insnsJan Beulich1-0/+24
Use of an explicit data size or REX.W prefix is sufficient indication of the intended operation when operand size can't be derived from suffix or register operands. Avoid the ambiguity warning and make in particular immediate handling (sizing) cope with explicitly specified prefixes. Extending/reusing the noreg16 test made me notice a few cases of unintentional 32-bit addressing, which gets corrected at the same time.
2020-06-25x86-64: REX prefix is invalid with VEX etcJan Beulich1-3/+10
Just like for the data size prefix (see commit 7a8655d2bbdc ["x86: don't abort() upon DATA16 prefix on (E)VEX encoded insn"]), any form of REX prefix is invalid with VEX/XOP/EVEX.
2020-06-25x86-64: honor REX prefixes for SSE2AVXJan Beulich1-28/+37
Legacy encoded insns do so, and their automatic conversion to AVX ones ought to produce functionally identical code. Therefore explicit REX prefixes cannot simply be ignored. This is in particular relevant because at least PCMPESTR{I,M}'s 64-bit forms couldn't be expressed in older gas by other than using a REX64 prefix.
2020-06-25x86: also refuse data size prefix on SIMD insnsJan Beulich1-3/+7
The data size prefix alters the meaning of legacy encoded SIMD insns, and hence shouldn't be accepted there. Use of it also leads to inconsistencies in SSE2AVX mode. Don't match insns with data size prefix against SSE2AVX templates.
2020-06-25x86: drop stray assignment from build_evex_prefix()Jan Beulich1-1/+0
Unlike in build_vex_prefix() this is not needed here.
2020-06-23RISC-V: Generate ELF priv attributes if priv instruction are explicited used.Nelson Chu1-6/+42
We should generate the ELF priv attributes only if, 1. The priv attributes are already set in the assembly file. 2. The CSR are explicited used. 3. The privileged instruction are explicited used. * There are four privileged instruction defined in the v1.11 priv spec: `mret`, `sret`, `wfi` and `sfence.vma`. * `sfence.vm` is dropped in the v1.10 priv spec. * `uret` is actually a N-ext instruction. So it is better to regard it as an user instruction rather than the priv instruction. * `hret` is used to return from traps in H-mode. H-mode is removed since the v1.10 priv spec, but probably be added in the new hypervisor spec. Therefore, `hret` should be controlled by the hypervisor spec rather than priv spec in the future. * `dret` is a debug instruction. We should record the debug spec versions once it is explicited used in the future. gas/ * config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to explicit_priv_attr. It used to indicate CSR or priv instructions are explictly used. (riscv_is_priv_insn): Return True if it is a privileged instruction. (riscv_ip): Call riscv_is_priv_insn to check whether the instruction is privileged or not. If it is, then set explicit_priv_attr to TRUE. (riscv_write_out_attrs): Clarification of when to generate the elf priv spec attributes. * testsuite/gas/riscv/attribute-11.s: Add comments. * testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol `priv_insn_<n>` to decide which priv instruction is expected to used. (<n> is a to g.) * testsuite/gas/riscv/attribute-14a.d: Likewise. * testsuite/gas/riscv/attribute-14b.d: Likewise. * testsuite/gas/riscv/attribute-14c.d: Likewise. * testsuite/gas/riscv/attribute-14d.d: Likewise. * testsuite/gas/riscv/attribute-14e.d: Likewise.
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-27/+9
We do know some conflicts among different privileged specs. For linker, the safest approach is that don't allow the object linked with others which may cause conflicts. But this may cause inconvenience since not all objects with conflicting priv specs are linked will cause problems. But it is hard to know the detailed conflict cases for linker, so we probably need a option to tell linker that we do know there are no conflicts, or we are willing to take risks to link the objects with conflicted priv specs. But the option is still under discussion. Therefore, we can report warnings rather than errors when linking the objects with conflicted priv specs. This not only makes the linker more flexible, but also warns people that the conflicts may happen. We also need to update the output priv spec version once the input priv spec is newer. bfd/ * elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker. (riscv_get_priv_spec_class): Likewise. (riscv_get_priv_spec_name): Likewise. (riscv_get_priv_spec_class_from_numbers): New function, convert the version numbers into string, then call riscv_get_priv_spec_class to get the priv spec class. * elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration from include/opcode/riscv.h to bfd/elfxx-riscv.h. (riscv_get_priv_spec_name): Likewise. (riscv_get_priv_spec_class_from_numbers): New forward declaration. (opcode/riscv.h): Include it in the header rather than elfxx-riscv.c. * elfnn-riscv.c (riscv_merge_attributes): Get the priv spec classes of input and output objects form their priv spec attributes by riscv_get_priv_spec_class_from_numbers. Report warning rather than errors when linking objects with differnet priv spec versions. We do know v1.9.1 may have conflicts to other versions, so report the warning, too. After that, update the output priv spec version to the newest one so far. gas/ * config/tc-riscv.c (buf_size, buf): Remove the unused variables. (riscv_set_default_priv_spec): Get the priv spec version from the priv spec attributes by riscv_get_priv_spec_class_from_numbers. include/ * opcode/riscv.h (riscv_get_priv_spec_class): Move the function forward declarations to bfd/elfxx-riscv.h. (riscv_get_priv_spec_name): Likewise. opcodes/ * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c. * riscv-dis.c: Include elfxx-riscv.h. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
2020-06-16x86: Correct noavx512_vp2intersectCui,Lili1-1/+2
* config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS. * doc/c-i386.texi: Add avx512_vp2intersect.
2020-06-16x86: drop SSE4a from SSE check againJan Beulich1-1/+0
Upon re-consideration in commit 569d50f1c611 ("x86: further refine SSE check (SSE4a, SHA, GFNI)") I went too far: Mixing of SSE and AVX insns doesn't suffer as bad a penalty on AMD CPUs as on Intel ones. SSE4a being an AMD-only extension, it shouldn't be part of the ISA extensions set for which the diagnostic may get issued. Undo that part.
2020-06-16Really remove tic30-aout supportAlan Modra1-4/+0
bfd/ * aout-tic30.c: Delete file. * Makefile.am (BFD32_BACKENDS): Remove aout-tic30.lo. (BFD32_BACKENDS_CFILES): Remove aout-tic30.c. * config.bfd (c30-*-*aout*, tic30-*-*aout*): Remove entry. (xc16x-*-elf): Sort properly. * configure.ac: Remove tic30_aout_vec. * targets.c: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. gas/ * config/tc-tic30.h: Remove OBJ_AOUT support. * configure.tgt: Delete tic30-*-*aout* entry. ld/ * emulparams/tic30aout.sh: Delete file. * scripttempl/tic30aout.sc: Delete file. * Makefile.am: Remove etic30aout.c from ALL_EMULATION_SOURCES and delete dependency. * configure.tgt: Delete tic30-*-*aout* entry. * testsuite/ld-scripts/sane1.d: Delete tic30-*-aout mention. * testsuite/ld-scripts/segment-start.d: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2020-06-15xtensa: allow runtime ABI selectionMax Filippov1-4/+25
2020-06-15 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED) (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New global variable. (xtensa_abi_choice): New function. (elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of XSHAL_ABI to select PLT code. gas/ * config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (option_abi_windowed, option_abi_call0): New enum constants. (md_longopts): Add entries for --abi-windowed and --abi-call0. (md_parse_option): Add handlers for --abi-windowed and --abi-call0. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. * doc/as.texi (Target Xtensa options): Add --abi-windowed and --abi-call0 to the list of options. * doc/c-xtensa.texi: Add description for options --abi-windowed and --abi-call0. * testsuite/gas/xtensa/abi-call0.d: New test definition. * testsuite/gas/xtensa/abi-windowed.d: New test definition. * testsuite/gas/xtensa/abi.s: New test source. include/ * elf/xtensa.h (xtensa_abi_choice): New declaration. ld/ * emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition. (XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test ABI tag consistency. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. (PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED, OPTION_ABI_CALL0 and declare elf32xtensa_abi. (PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and --abi-call0. (PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and --abi-call0. (PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and --abi-call0. * ld.texi: Add description for options --abi-windowed and --abi-call0.
2020-06-09x86-64: adjust far indirect branch handlingJan Beulich1-1/+3
An unwanted side effect of 5990e377e5a3 ("x86-64: Intel64 adjustments for insns dealing with far pointers") was that with -mintel64 LCALL and LJMP would now default to 64-bit operand size. Since 64-bit far branches aren't portable, the default operand size should still be 32-bit. However, since the 64-bit variant is permitted, an ambiguous operand warning should be issued. As to the actual code change, please note that the conditional surrounding the switch() that gets adjusted covers several cases which are of no interest to or benign in 64-bit mode, hence the new conditional added can be quite a bit less involved.
2020-06-09x86: don't ignore mandatory pseudo prefixesJan Beulich1-23/+47
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not be randomly ignored. Fix this for insns without operands as well as for insns referencing the high 16 [XYZ]MM registers. To achieve the former, re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and moving its only operand check to check_VecOperands(). This involves fixing a testcase relying on {vex2} to get ignored.
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan1-0/+7
gas/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (insns): Add dfb. * testsuite/gas/arm/dfb.d: New test. * testsuite/gas/arm/dfb.s: Input for test. opcodes/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * arm-dis.c (arm_opcodes): Add dfb. (thumb32_opcodes): Add dfb.
2020-06-08x86: also handle %k<N> and %bnd<N> in debugging helpersJan Beulich1-1/+3
Adjustment of this function was missed when support for the respective registers was added.
2020-06-08x86: simplify check_byte_reg()Jan Beulich1-15/+4
With the introduction of what right now is the very first conditional in the function's loop (commit dc821c5f9ae5 ["x86: replace Reg8, Reg16, Reg32, and Reg64"]), the last if() in the same loop has become pointless - retain just its body.
2020-06-08x86: restrict %tr<N> visibilityJan Beulich1-2/+8
First of all, these registers have never been available on any 64-bit CPU, and hence should not be recognized in 64-bit mode. But even before that they had already disappeared - also don't recognize them when 586 or 686 architectures were explicitly set.
2020-06-08x86: also allow %st(N) in CFI directivesJan Beulich1-1/+2
In 0e0eea782025 ("x86: x87-related adjustments") I screwed up CFI directives with FPU support disabled, by moving the conditional there across a check of "allow_pseudo_reg". Add the missing check.
2020-06-08x86: restrict use of register aliasesJan Beulich1-65/+95
Register aliases (created e.g. via .set) check their target register at the time of creation of the alias. While this makes sense, it's not enough: The underlying register must also be "visible" at the time of use. Wrong use of such aliases would lead to internal errors in e.g. add_prefix() or build_modrm_byte(). Split the checking part of parse_real_register() into a new helper function and use it also from the latter part of parse_register() (at the same time replacing a minor open coded part of it). Since parse_register() returning NULL already has a meaning, a fake new "bad register" indicator gets added, which all callers need to check for.
2020-06-06Power10 tidiesAlan Modra1-0/+2
binutils/ * doc/binutils.texi (PowerPC -M option): Mention power10 and pwr10. gas/ * config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2020-06-06Rename PowerPC64 pcrel GOT TLS relocationsAlan Modra1-16/+16
These relocations should have had REL in their names, to reflect the fact that they are pc-relative. Fix that now by adding _PCREL. I've added some back-compatibility code to support anyone using .reloc with the old relocations. include/ * elf/ppc64.h (elf_ppc64_reloc_type): Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. bfd/ * reloc.c: Rename BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34, BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34, BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34, BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34. * elf64-ppc.c: Update throughout for reloc renaming. (ppc64_elf_reloc_name_lookup): Handle old reloc names. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c: Update throughout for reloc renaming. elfcpp/ * powerpc.h: Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. gold/ * powerpc.cc: Update throughout for reloc renaming.
2020-06-05gas: avoid GCC 10 warning stringop-overflow in tc-bpf.cJose E. Marchesi1-2/+2
The GAS struct frag ends with a field `fr_literal' whose purpose is to mark the begining of the frag's data: struct frag { ... /* Data begins here. */ char fr_literal[1]; }; The code in gas/config/tc-bpf.c recently committed: where = fixP->fx_frag->fr_literal + fixP->fx_where; where[1] = target_big_endian ? 0x01 : 0x10; triggers the stringop-overflow warning in GCC 10+, since the compiler assumes the size of the modified buffer is 1 byte. This patch slightly modifies the code to make tc-bpf.c buildable with GCC 10+. 2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning stringop-overflow.
2020-06-05RISC-V: Don't generate the ELF privilege attributes when no CSR are used.Nelson Chu1-0/+9
gas/ * config/tc-riscv.c (explicit_csr): New static boolean. Used to indicate CSR are explictly used. (riscv_ip): Set explicit_csr to TRUE if any CSR is used. (riscv_write_out_attrs): If we already have set elf priv attributes, then generate them. Otherwise, don't generate them when no CSR are used. * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-11.s: New testcase. * testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is used, so we should output the ELF priv attributes. * testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is used, so output the priv attributes according to the -mpriv-spec. * testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't used, so ignore the -mpriv-spec setting. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
2020-06-04gas: Fix ip2k-elf and xstormy16-elf buildH.J. Lu2-3/+6
Fix ip2k-elf and xstormy16-elf build due to commit e9bffec9afc45cf7c49308f0b4b8cc6bf68f58f2 Author: Jose E. Marchesi <jose.marchesi@oracle.com> Date: Thu Jun 4 16:15:53 2020 +0200 opcodes: discriminate endianness and insn-endianness in CGEN ports * config/tc-ip2k. (ip2k_apply_fix): Pass endianness to cgen_get_insn_value. * config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass endianness to cgen_get_insn_value and cgen_put_insn_value.
2020-06-04gas: simplify code in tc-bpf.c:md_apply_fixJose E. Marchesi1-3/+1
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_apply_fix): Simplify and avoid using cgen_put_insn_value.
2020-06-04cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi1-4/+2
cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi2-2/+3
The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-05-28Fix all unexpected failures in gas testsuite for pdp11-aout.Stephen Casner1-0/+10
These failures were caused by the PDP11's mix of little-endian octets in shorts but shorts in big endian order for long or quad so regexps did not match. Also tests used addresses as values in .long which required BRD_RELOC_32 that was not implemented. * gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad * gas/testsuite/gas/all/gas.exp: Select alternate test scripts for pdp11, skip octa test completely. * gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s * gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order. * gas/testsuite/gas/all/cond-pdp11.l: Match different octet order. * bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of addreses in .long (used in testsuites) and .stab values.
2020-05-27Fix PR gas/26001 (pdp11-*-*)Stephen Casner1-1/+10
PR gas/26001 * gas/config/tc-pdp11.c (parse_reg): Distinguish register names from symbols that begin with a register name. * gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols. * gas/testsuite/gas/pdp11/pr26001.s: Likewise. * gas/testsuite/gas/pdp11/pr26001.d: Likewise.
2020-05-27RISC-V: Fix missing initialization of riscv_csr_extra structsSimon Cook1-0/+1
The next pointer of struct riscv_csr_extra was not always initilized to NULL or a valid pointer, causing the assembler to attempt to read through an uninitialized pointer on startup. gas/ChangeLog: * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next pointer when creating struct riscv_csr_extra.
2020-05-26tc-xgate.c: Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_XH.J. Lu1-4/+4
Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X to silence GCC 10 warning: gas/config/tc-xgate.c:1339:5: error: implicit conversion from ‘enum elf_xgate_reloc_type’ to ‘bfd_reloc_code_real_type’ {aka ‘enum bfd_reloc_code_real’} [-Werror=enum-conversion] 1339 | R_XGATE_PCREL_9); | ^~~~~~~~~~~~~~~ PR gas/26044 * config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X instead of R_XGATE_PCREL_X. (xgate_parse_operand): Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X.
2020-05-26gas: Silence GCC 10 warning on tc-visium.cH.J. Lu1-1/+1
PR gas/26044 * config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26gas: Silence GCC 10 warning tc-vax.cH.J. Lu1-2/+2
PR gas/26044 * config/tc-vax.c (md_estimate_size_before_relax): Replace fragP->fr_literal with &fragP->fr_literal[0]. (md_convert_frag): Likewise.
2020-05-26gas: Silence GCC 10 warning on tc-v850.cH.J. Lu1-2/+2
PR gas/26044 * config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
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