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2019-10-16qsort: tc-xtensa.c tidyAlan Modra1-22/+26
Not much to see here, just reduce the number of calls to S_GET_VALUE and symbol_symbolS in the comparison functions. * config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't call S_GET_VALUE multiple times for a symbol. Rearrange code so it is obvious what is the primary sort key. (xg_order_trampoline_chain): Similarly.
2019-10-15remove more xmalloc in bfdAlan Modra1-6/+6
Also fixes m68hc1x printf arguments which would have bombed when compiling on a 32-bit host with --enable-64-bit-bfd. bfd/ PR 24955 * elf32-arm.c (set_cmse_veneer_addr_from_implib): Use bfd_malloc rather than xmalloc. * elf32-m68hc1x.c (reloc_warning): New function. (elf32_m68hc11_relocate_section): Use it here. Cast bfd_vma values corresponding to %lx in format strings. * elf32-nds32.c (nds32_insertion_sort): Use a stack temporary. gas/ * config/tc-nds32.c (nds32_set_section_relocs): Use relocs and n parameters rather than equivalent sec->orelocation and sec->reloc_count. Don't sort for n <= 1. Tidy.
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel1-1/+1
So far z15 was identified as arch13. After the machine has been announced we can now add the real name. gas/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): Add z15 as alternate CPU name. * doc/as.texi: Add z15 to CPU string list. * doc/c-s390.texi: Likewise. opcodes/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Enable z15 as CPU string in the opcode table.
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz1-4/+142
This functionality will generate a new GNU object attribute for the "data region" has been added. This object attribute is used mark whether the compiler has generated code assuming that data could be in the upper or lower memory regions. Code which assumes data is always in the lower memory region is incompatible with code which uses the full memory range for data. The patch also adds a new assembler directive ".mspabi_attribute" to handle the existing MSPABI object attributes. GCC will now emit both .gnu_attribute and .mspabi_attribute directives to indicate what options the source file was compiled with. The assembler will now check the values set in these directives against the options that the it has been invoked with. If there is a discrepancy, the assembler will exit with an error. bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to.. (elf32_msp430_merge_msp430_attributes): Add support for merging the GNU object attribute for data region. binutils* readelf.c (display_msp430_gnu_attribute): New. (process_arch_specific): Use msp430 specific handler for GNU attributes. gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to FALSE if the data region is set to "upper", "either" or "none". (msp430_object_attribute): New. (md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute. (msp430_md_end): Replace hard-coded attribute values with enums. Handle data region object attribute. * doc/as.texi: Document MSP430 Data Region object attribute. * doc/c-msp430.texi: Document the .mspabi_attribute directive. * testsuite/gas/msp430/attr-430-small-bad.d: New test. * testsuite/gas/msp430/attr-430-small-bad.l: New test. * testsuite/gas/msp430/attr-430-small-good.d: New test. * testsuite/gas/msp430/attr-430-small.s: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-any-good.d: New test. * testsuite/gas/msp430/attr-430x-large-any.s: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-lower-good.d: New test. * testsuite/gas/msp430/attr-430x-large-lower.s: New test. * testsuite/gas/msp430/msp430.exp: Run new tests. include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names and values. ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test. * testsuite/ld-msp430-elf/attr-gnu-obj.s: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test. * testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich1-2/+2
First and foremost the EsSeg attribute was misplaced for CMPSD. Then both it and MOVSD were lacking Dword on both of their operands. Finally string insns with multiple operands and requiring use of ES: had the wrong operand number reported in the diagnostic.
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina1-7/+16
The fix for PR12848 introduced an off by one error in the mask, this corrected the negative overflows but not the positive overflows. As a result the conditional branch instructions accepted a too wide positive immediate which resulted in it corrupting the instruction during encoding. The relocation I believe has been incorrectly named, to be consistent with the other relocations it should have been named BRANCH21 which is why the masks for it are confusing. I've replaced the masks with a function out_of_range_p which should make it harder to make such mistakes. The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits and so the mask should be checking for 24-bits for positive overflow. gas/ChangeLog: PR gas/24991 * config/tc-arm.c (out_of_range_p): New. (md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9, BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20, BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25 * testsuite/gas/arm/pr24991.d: New test. * testsuite/gas/arm/pr24991.l: New test. * testsuite/gas/arm/pr24991.s: New test.
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ↵Srinath Parvathaneni1-5/+5
instruction VLDR. This patch modifies assembler to accept the equivalent sized floating and signless datatypes for VLDR instruction but as alias for the unsigned version. gas/ChangeLog: 2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float * and signless datatypes for few cases of VLDR instruction. * testsuite/gas/arm/mve-vldr-bad-3.l: Modify. * testsuite/gas/arm/mve-vldr-bad-3.s: Likewise. * testsuite/gas/arm/mve-vstrldr-1.d: Likewise. * testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
2019-09-23ecoff bfd.h tidyAlan Modra2-0/+2
bfd/ * bfd-in.h: Move ecoff function declarations.. * ecoff-bfd.h: ..to here, new file. * ecoff.c: Include ecoff-bfd.h. * ecofflink.c: Likewise. * elf64-alpha.c: Likewise. * elfxx-mips.c: Likewise. * bfd-in2.h: Regenerate. gas/ * config/obj-ecoff.c: Include ecoff-bfd.h. * config/obj-elf.c: Likewise.
2019-09-23arm bfd.h tidyAlan Modra1-0/+1
bfd/ * bfd-in.h: Move arm declaraions.. * cpu-arm.h: ..to here, new file.. * coff-arm.h: ..and here, new file.. * elf32-arm.h: ..and here, new file. * cpu-arm.c: Include cpu-arm.h. * coff-arm.c: Include cpu-arm.h and coff-arm.h. * elf32-arm.c: Include cpu-arm.h and elf32-arm.h. * pe-arm.c: Move function rename defines later. * pe-arm-wince.c: Likewise and include sysdep.h and bfd.h early. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c: Include cpu-arm.h. ld/ * emultempl/armelf.em: Include elf32-arm.h. * emultempl/pe.em: Move func defines later and include coff-arm.h.
2019-09-21tc-i386.c gcc10 warning fixAlan Modra1-2/+2
.../gas/config/tc-i386.c: In function ‘md_parse_option’: .../gas/config/tc-i386.c:11441:9: error: implicit conversion from ‘enum <anonymous>’ to ‘enum <anonymous>’ [-Werror=enum-conversion] 11441 | vexwig = evexw0; | ^ .../gas/config/tc-i386.c:11443:9: error: implicit conversion from ‘enum <anonymous>’ to ‘enum <anonymous>’ [-Werror=enum-conversion] 11443 | vexwig = evexw1; | ^ * config/tc-i386.c (md_parse_option): Fix warning on vexwig assignment.
2019-09-20bfd macro conversion to inline functions, sectionAlan Modra1-1/+1
This one exposed a bug in tic6x gas, found with inline function parameter type checking. struct bfd_section and struct bfd_symbol both have a flags field, so bfd_is_com_section (symbol) compiled OK when bfd_is_com_section was a macro but didn't special case common symbols. bfd/ * bfd-in.h (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, discarded_section), (bfd_get_section_limit_octets, bfd_get_section_limit): Delete macros. * bfd.c (bfd_get_section_limit_octets, bfd_get_section_limit), (bfd_section_list_remove, bfd_section_list_append), (bfd_section_list_prepend, bfd_section_list_insert_after), (bfd_section_list_insert_before, bfd_section_removed_from_list): New inline functions. * section.c (bfd_is_und_section, bfd_is_abs_section), (bfd_is_ind_section, bfd_is_const_section, bfd_section_list_remove), (bfd_section_list_append, bfd_section_list_prepend), (bfd_section_list_insert_after, bfd_section_list_insert_before), (bfd_section_removed_from_list): Delete macros. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, bfd_is_und_section), (bfd_is_abs_section, bfd_is_ind_section, bfd_is_const_section), (discarded_section): New inline functions. * bfd-in2.h: Regenerate. gas/ * config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check. ld/ * emultempl/xtensaelf.em (xtensa_get_section_deps): Comment. Use bfd_section_userdata. (xtensa_set_section_deps): Use bfd_set_section_userdata. * ldlang.c (lang_output_section_get): Use bfd_section_userdata. (sort_def_symbol): Likewise, and bfd_set_section_userdata. (init_os): Use bfd_set_section_userdata. (print_all_symbols): Use bfd_section_userdata. * ldlang.h (get_userdata): Delete.
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich1-2/+2
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit PUSH/POP templates into non-64-bit ones isn't correct, due to the different operand widths, and hence suffixes permitted. Restore the separate templates. Add tests of PUSH/POP with q suffix and %fs/%gs operands to the testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
2019-09-19bfd_section_* macrosAlan Modra62-300/+270
This large patch removes the unnecessary bfd parameter from various bfd section macros and functions. The bfd is hardly ever used and if needed for the bfd_set_section_* or bfd_rename_section functions can be found via section->owner except for the com, und, abs, and ind std_section special sections. Those sections shouldn't be modified anyway. The patch also removes various bfd_get_section_<field> macros, replacing their use with bfd_section_<field>, and adds bfd_set_section_lma. I've also fixed a minor bug in gas where compressed section renaming was done directly rather than calling bfd_rename_section. This would have broken bfd_get_section_by_name and similar functions, but that hardly mattered at such a late stage in gas processing. bfd/ * bfd-in.h (bfd_get_section_name, bfd_get_section_vma), (bfd_get_section_lma, bfd_get_section_alignment), (bfd_get_section_size, bfd_get_section_flags), (bfd_get_section_userdata): Delete. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment): Lose bfd parameter. (bfd_section_flags, bfd_section_userdata): New. (bfd_is_com_section): Rename parameter. * section.c (bfd_set_section_userdata, bfd_set_section_vma), (bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section), (bfd_set_section_size): Delete bfd parameter, rename section parameter. (bfd_set_section_lma): New. * bfd-in2.h: Regenerate. * mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param, update callers. * aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c, * elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c, * elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c, * mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c, * peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c, * xcofflink.c: Update throughout for bfd section macro and function changes. binutils/ * addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c, * objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c, * od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c, * resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update throughout for bfd section macro and function changes. gas/ * as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c, * read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c, * config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c, * config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c, * config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c, * config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c, * config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c, * config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c, * config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for bfd section macro and function changes. * write.c (compress_debug): Use bfd_rename_section. gdb/ * aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c, * coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c, * dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c, * exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h, * hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c, * i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c, * maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c, * mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c, * objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c, * ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c, * rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c, * s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c, * solib-spu.c, * solib-svr4.c, * solib-target.c, * spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c, * symmisc.c, * symtab.c, * target.c, * windows-nat.c, * xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c, * mi/mi-interp.c: Update throughout for bfd section macro and function changes. * gcore (gcore_create_callback): Use bfd_set_section_lma. * spu-tdep.c (spu_overlay_new_objfile): Likewise. gprof/ * corefile.c, * symtab.c: Update throughout for bfd section macro and function changes. ld/ * ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c, * emultempl/aarch64elf.em, * emultempl/aix.em, * emultempl/armcoff.em, * emultempl/armelf.em, * emultempl/cr16elf.em, * emultempl/cskyelf.em, * emultempl/m68hc1xelf.em, * emultempl/m68kelf.em, * emultempl/mipself.em, * emultempl/mmix-elfnmmo.em, * emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em, * emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update throughout for bfd section macro and function changes. libctf/ * ctf-open-bfd.c: Update throughout for bfd section macro changes. opcodes/ * arc-ext.c: Update throughout for bfd section macro changes. sim/ * common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c, * erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c, * m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c, * rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c, * rx/trace.c: Update throughout for bfd section macro changes.
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-7/+20
Generalize opcode arch dependencies so that we can support the overlapping B extension Zb* subsets. 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle insn_class enum rather than subset char string. (riscv_ip): Update call to riscv_multi_subset_supports. include/ * opcode/riscv.h (riscv_insn_class): New enum. * opcode/riscv.h (struct riscv_opcode): Change subset field to insn_class field. opcodes/ * riscv-opc.c (riscv_opcodes): Change subset field to insn_class field for all instructions. (riscv_insn_types): Likewise.
2019-09-10[PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni1-0/+41
This patch adds support for MVE VCTP instruction in assembler. gas ChangeLog: 2019-09-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (M_MNEM_vctp): Add new Mnemonic. (do_mve_vctp): Add function to encode VCTP instruction. * testsuite/gas/arm/mve-vctp-bad.d: New test. * testsuite/gas/arm/mve-vctp-bad.l: Likewise. * testsuite/gas/arm/mve-vctp-bad.s: Likewise. * testsuite/gas/arm/mve-vctp.d: Likewise. * testsuite/gas/arm/mve-vctp.s: Likewise.
2019-09-05PowerPC warning on symbol+offset@gotAlan Modra1-3/+3
* config/tc-ppc.c (ppc_elf_suffix): Display the relocation operator on GOT reloc warnings/errors.
2019-08-30[PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction ↵Srinath Parvathaneni1-1/+7
correctly. This patch make changes to the assembler to encode MVE VMOV instruction "a" same as "b". a: VMOV<c><q> <Dd>, <Dm> b: VMOV<c><q>.F64 <Dd>, <Dm> gas/ChangeLog: 2019-08-30 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_neon_mov): Modify "if" statement. * testsuite/gas/arm/mve-vmov-bad-3.d: New test. * testsuite/gas/arm/mve-vmov-bad-3.l: Likewise. * testsuite/gas/arm/mve-vmov-bad-3.s: Likewise.
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This ↵Srinath Parvathaneni1-2/+4
instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction. gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector register to both the arguments in VMOV instruction. * testsuite/gas/arm/mve-vmov-1.d: Modify. * testsuite/gas/arm/mve-vmov-1.s: Likewise. * testsuite/gas/arm/mve-vorr.d: Likewise. opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
2019-08-25RISC-V: Improve li expansion for better code density.Kito Cheng1-5/+33
li is a pseudo instruction in RISC-V, it might expand to more than one instructions if the immediate value can't fit addi or lui, but the assembler will always using 4-byte instructions during expansion. For example: li a0, 0x12345001 will expand into 12345537 lui a0,0x12345 00150513 addi a0,a0,1 but addi could be compress into 0505 addi a0,a0,1 It because load_const use macro_build to emit instructions, and macro_build call append_insn, and expect it will compress it if possible, but the fact is append_insn never compress anything, So this patch redirect the li expansion flow to normal instruction emission flow via md_assemble, added md_assemblef as an wrapper for that for easier emit instruction with printf-style argument to build instruction. gas/ChangeLog: * tc-riscv.c (md_assemblef): New. (load_const) Use md_assemblef instead of macro_build to emit instructions. * testsuite/gas/riscv/li32.d: New. * testsuite/gas/riscv/li32.s: Ditto. * testsuite/gas/riscv/li64.d: Ditto. * testsuite/gas/riscv/li64.s: Ditto.
2019-08-22Arm: Add support for missing CPUsDennis Zhang1-0/+9
This patch adds support for following CPUs: Cortex-M35P, Cortex-A77, Cortex-A76AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas/ChangeLog: * config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77, and Cortex-A76AE. * doc/c-arm.texi: Document new processors. * testsuite/gas/arm/cpu-cortex-a76ae.d: New test. * testsuite/gas/arm/cpu-cortex-a77.d: New test. * testsuite/gas/arm/cpu-cortex-m35p.d: New test. bfd/ChangeLog: * cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point ↵Barnaby Wilks1-1/+2
numbers for the AArch64 assembler. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 0.5 .float16 10.2, NaN, 452.09 The floats will always be encoded using the binary16 format as described in the IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision format since AArch64 only supports the IEEE format. gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to acceptable float characters. * doc/c-aarch64.texi: Documentation for float16 directive. * testsuite/gas/aarch64/float16-be.d: New test. * testsuite/gas/aarch64/float16-le.d: New test. * testsuite/gas/aarch64/float16.s: New test. * NEWS: Add NEWS entry.
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: ↵Dennis Zhang1-0/+22
Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas * NEWS: Mention the Arm and AArch64 new processors. * config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE. * doc/c-aarch64.texi: Document new CPUs. * testsuite/gas/aarch64/cpu-cortex-a34.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a77.d: New test. * testsuite/gas/aarch64/nop-asm.s: New test. bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-19MIPS/gas: Fix misaligned address errors to disregard ISA mode bitFaraz Shahbazker1-5/+23
gas/ * config/tc-mips.c (fix_bad_misaligned_address): New function. (fix_validate_branch): Call fix_bad_misaligned address_to calculate the target address. (md_apply_fix): Likewise. (md_convert_frag): Update misaligned address calculation to disregard ISA mode bit.
2019-08-19MIPS/gas: Retain ISA mode bit for labels with .insn annotationFaraz Shahbazker1-3/+4
gas/ * config/tc-mips.c (mips_move_labels): Retain ISA mode bit when moving labels in text segments. (mips_align): Indicate text mode when aligning labels in text segments. * gas/testsuite/gas/mips/insn-isa-mode.d: New test. * gas/testsuite/gas/mips/insn-isa-mode.s: New test source. * gas/testsuite/gas/mips/mips.exp: Run the new test.
2019-08-19Float16: Fix test failures for non ELF targetsBarnaby Wilks1-27/+22
The tests were failing due to md_atof trying to do word-wise endian switching on the float16 (for little-endian targets sometimes multi word values have their word order changed). However since a float16 is only 1 word wide, it would end up writing incorrect data, as you cannot switch the word order of just one word. * config/tc-arm.c (md_atof): Add precision check. Formatting.
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni1-2/+41
This is a change to the first published specifications [1][a] but since there is no hardware out there that uses the old instructions we do not want to support the old variant. This changes are done based on the latest published specifications [1][b]. [1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual [a] version bf [b] version bh gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64. (po_imm1_or_imm2_or_fail): Marco to check the immediate is either of 48 or 64. (parse_operands): Add case OP_I48_I64. (do_mve_scalar_shift1): Add function to encode the MVE shift instructions with 4 arguments. * testsuite/gas/arm/mve-shift-bad.l: Modify. * testsuite/gas/arm/mve-shift-bad.s: Likewise. * testsuite/gas/arm/mve-shift.d: Likewise. * testsuite/gas/arm/mve-shift.s: Likewise. opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for cases MVE_SQRSHRL and MVE_UQRSHLL. (print_insn_mve): Add case for specifier 'k' to check specific bit of the instruction.
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating ↵Barnaby Wilks3-8/+129
point numbers to the assembler. Half precision floating point numbers will be encoded using the IEEE 754 half precision floating point format - 16 bits in total, 1 for sign, 5 for exponent and 10 bits of mantissa. This patch implements the float16 directive for both the IEEE 754 format and the Arm alternative format for the Arm backend. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 12.0 .float16 0.23, 433.1, 0.06 The Arm alternative format is almost identical to the IEEE 754 format, except that it doesn't encode for NaNs or Infinity (instead an exponent of 0x1F represents a normalized number in the range 65536 to 131008). The alternative format is documented in the reference manual: https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439 Which format is used is controlled by the .float16_format <format> directive, where if <format> = ieee, then use the IEEE 754 half-precision format else if <format> = alternative, then use the Arm alternative format Or the format can be set on the command line via the -mfp16-format option that has a similar syntax. -mfp16-format=<ieee|alternative>. This also fixes the format and it cannot be changed by any directives. Once the format has been set (either by the command line option or a directive) it cannot be changed, and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the line being ignored. For ELF targets the appropriate EABI attribute will be written out at the end of assembling if the format has been explicitly specified. If no format has been explicitly specified then no EABI attributes will be written. If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008 format by default until the format is fixed or changed with the float16_format directive. gas * config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings. (md_atof): Set precision for float16 type. (arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative format. (set_fp16_format): Parse a float16_format directive. (arm_parse_fp16_opt): Parse the fp16-format command line option. (aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute. * config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to arm_is_largest_exponent_ok. (arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function. * doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format= * testsuite/gas/arm/float16-bad.d: New test. * testsuite/gas/arm/float16-bad.l: New test. * testsuite/gas/arm/float16-bad.s: New test. * testsuite/gas/arm/float16-be.d: New test. * testsuite/gas/arm/float16-format-bad.d: New test. * testsuite/gas/arm/float16-format-bad.l: New test. * testsuite/gas/arm/float16-format-bad.s: New test. * testsuite/gas/arm/float16-format-opt-bad.d: New test. * testsuite/gas/arm/float16-format-opt-bad.l: New test. * testsuite/gas/arm/float16-le.d: New test. * testsuite/gas/arm/float16.s: New test. * testsuite/gas/arm/float16-eabi-alternative-format.d: New test. * testsuite/gas/arm/float16-eabi-ieee-format.d: New test. * testsuite/gas/arm/float16-eabi-no-format.d: New test. * testsuite/gas/arm/float16-eabi.s: New test. * config/atof-ieee.c (H_PRECISION): Macro for precision of float16 type. (atof_ieee): Set precision and exponent bits for encoding float16 types. (gen_to_words): NaN and Infinity encoding for float16. (ieee_md_atof): Set precision for encoding float16 type.
2019-08-12PR24851, gas/testsuite/gas/epiphany/badrelax.s failure with MALLOC_PERTURB_=1Alan Modra1-17/+22
PR 24851 * config/tc-epiphany.c (md_estimate_size_before_relax): Clear extra opcode bytes when changing from a 2-byte to a 4-byte insn.
2019-08-05Removes support in the ARM assembler for the unsigned variants of the ↵Barnaby Wilks1-2/+2
VQ(R)DMLAH and VQ(R)DMLASH MVE instructions. Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH instructions, however the Armv8.1-M Mainline specification states that these functions only have signed variations (.s32, .s16 and .s8 suffixes). This is documented here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183 gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro. (do_neon_qrdmlah): Use N_S_32 macro. * testsuite/gas/arm/mve-vqdmlah-bad.d: New test. * testsuite/gas/arm/mve-vqdmlah-bad.l: New test. * testsuite/gas/arm/mve-vqdmlah-bad.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash-bad.d: New test. * testsuite/gas/arm/mve-vqdmlash-bad.l: New test. * testsuite/gas/arm/mve-vqdmlash-bad.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests. opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH instructions.
2019-07-24Complain about mbind, ifunc, and unique in final_writeAlan Modra1-0/+3
It's not as good as complaining in gas/config/obj-elf.c since you lose any reference to the source file. bfd/ * elf-bfd.h (struct elf_backend_data): Return bfd_boolean from elf_backend_final_write_processing, don't pass linker arg. (_bfd_elf_final_write_processing): Update prototype. * elf.c (_bfd_elf_write_object_contents): Adjust call. (_bfd_elf_final_write_processing): Return error on incompatible OSABI and has_gnu_osabi. Remove linker arg. * elf-nacl.h (nacl_final_write_processing): Update prototype. * elf-vxworks.h (elf_vxworks_final_write_processing): Likewise. * elfxx-mips.h (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_write_processing): Likewise. * elf-hppa.h (elf_hppa_final_write_processing): Return status and remove linker arg. * elf-m10300.c (_bfd_mn10300_elf_final_write_processing): Likewise. * elf-nacl.c (nacl_final_write_processing): Likewise. * elf-vxworks.c (elf_vxworks_final_write_processing): Likewise. * elf32-arc.c (arc_elf_final_write_processing): Likewise. * elf32-arm.c (arm_final_write_processing): Likewise. (elf32_arm_final_write_processing): Likewise. (elf32_arm_nacl_final_write_processing): Likewise. (elf32_arm_vxworks_final_write_processing): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. * elf32-bfin.c (elf32_bfin_final_write_processing): Likewise. * elf32-cr16.c (_bfd_cr16_elf_final_write_processing): Likewise. * elf32-cris.c (cris_elf_final_write_processing): Likewise. * elf32-h8300.c (elf32_h8_final_write_processing): Likewise. * elf32-lm32.c (lm32_elf_final_write_processing): Likewise. * elf32-m32r.c (m32r_elf_final_write_processing): Likewise. * elf32-m68k.c (elf_m68k_final_write_processing): Likewise. * elf32-mips.c (mips_vxworks_final_write_processing): Likewise. * elf32-msp430.c (bfd_elf_msp430_final_write_processing): Likewise. * elf32-nds32.c (nds32_elf_final_write_processing): Likewise. * elf32-or1k.c (or1k_elf_final_write_processing): Likewise. * elf32-pj.c (pj_elf_final_write_processing): Likewise. * elf32-ppc.c (ppc_final_write_processing): Likewise. (ppc_elf_final_write_processing): Likewise. (ppc_elf_vxworks_final_write_processing): Likewise. * elf32-sparc.c (sparc_final_write_processing): Likewise. (elf32_sparc_final_write_processing): Likewise. (elf32_sparc_vxworks_final_write_processing): Likewise. * elf32-v850.c (v850_elf_final_write_processing): Likewise. * elf32-xc16x.c (elf32_xc16x_final_write_processing): Likewise. * elf32-xtensa.c (elf_xtensa_final_write_processing): Likewise. * elf64-ia64-vms.c (elf64_vms_final_write_processing): Likewise. * elfnn-ia64.c (elfNN_ia64_final_write_processing): Likewise. * elfxx-mips.c (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_write_processing): Likewise. gas/ * config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi. * testsuite/gas/elf/section12a.d: Update xfails. * testsuite/gas/elf/section12b.d: Likewise.
2019-07-23SHF_GNU_MBIND requires ELFOSABI_GNUAlan Modra1-26/+43
When SHF_GNU_MBIND was added in the SHF_LOOS to SHF_HIOS range, it should have required ELFOSABI_GNU since these flags are already in use by other OSes. HPUX SHF_HP_TLS in fact has the same value. That means no place in binutils should test SHF_GNU_MBIND without first checking OSABI, and SHF_GNU_MBIND should not be set without also setting OSABI. At least, that's the ideal, but the patch accepts SHF_GNU_MBIND on ELFOSABI_NONE object files since gas didn't always set OSABI. However, to reinforce the fact that SHF_GNU_MBIND isn't proper without a non-zero OSABI, readelf will display the flag as LOOS+0 if OSABI isn't set. The clash with SHF_HP_TLS means that hppa64-linux either has that flag on .tbss sections or supports GNU_MBIND, not both. (hppa64-linux users, if there are any, may have noticed that GNU ld since 2017 mysteriously aligned their .tbss sections to a 4k boundary. That was one consequence of SHF_HP_TLS being blindly interpreted as SHF_GNU_MBIND.) Since it seems that binutils, gdb, gcc, glibc, and the linux kernel don't care about SHF_HP_TLS I took that flag out of .tbss for hppa64-linux. bfd/ * elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_mbind. * elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_mbind. (get_program_header_size): Formatting. Only test SH_GNU_MBIND when elf_gnu_osabi_mbind is set. (_bfd_elf_map_sections_to_segments): Likewise. (_bfd_elf_init_private_section_data): Likewise. (_bfd_elf_final_write_processing): Update comment. * elf64-hppa.c (elf64_hppa_special_sections): Move .tbss entry. (elf_backend_special_sections): Define without .tbss for linux. binutils/ * readelf.c (get_parisc_segment_type): Split off hpux entries.. (get_ia64_segment_type): ..and these.. (get_hpux_segment_type): ..to here. (get_segment_type): Condition GNU_MBIND on osabi. Use get_hpux_segment_type. (get_symbol_binding): Do not print UNIQUE for ELFOSABI_NONE. (get_symbol_type): Do not print IFUNC for ELFOSABI_NONE. gas/ * config/obj-elf.c (obj_elf_change_section): Don't emit a fatal error for non-SHF_ALLOC SHF_GNU_MBIND here. (obj_elf_parse_section_letters): Return SHF_GNU_MBIND in new gnu_attr param. (obj_elf_section): Adjust obj_elf_parse_section_letters call. Formatting. Set SHF_GNU_MBIND and elf_osabi from gnu_attr. Emit normal error for non-SHF_ALLOC SHF_GNU_MBIND and wrong osabi. (obj_elf_type): Set elf_osabi for ifunc. * testsuite/gas/elf/section12a.d: xfail msp430 and hpux. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.d: Likewise. * testsuite/gas/elf/section13.l: Adjust expected error. ld/ * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Condition SHF_GNU_MBIND on osabi. Set output elf_gnu_osabi_mbind.
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline ↵Barnaby Wilks1-5/+0
specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size. The instructions that this change apply to are: VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf Fixed this by removing the check for this warning from GAS as well as opcodes. Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size and the same source and destination operand. Also fixed tests that would previously check for this warning. gas * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE. * testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmladh.d: New tests. * testsuite/gas/arm/mve-vqdmladh.s: New tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh.d: New tests. * testsuite/gas/arm/mve-vqdmlsdh.s: New tests. opcodes * arm-dis.c (is_mve_unpredictable): Stop marking some MVE instructions as UNPREDICTABLE.
2019-07-19gas: make .lcomm to accept an optional aligmnet in eBPF targetsJose E. Marchesi1-1/+43
Tested in a x86_64 host. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c. (pe_lcomm): Likewise. (md_pseudo_table): Use pe_lcomm to implement .lcomm.
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford1-1/+1
After some discussion, we've decided to rename the +bitperm feature flag to +sve2-bitperm, so that it's consistent with the other SVE2 feature flags. The associated internal macros already used "SVE2_BITPERM", so only the feature flag itself needs to change. 2019-07-19 Richard Sandiford <richard.sandiford@arm.com> gas/ * doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm. * config/tc-aarch64.c (aarch64_features): Likewise. * testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise. * testsuite/gas/aarch64/illegal-sve2.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-07-19[PowerPC64] pc-relative TLS relocationsAlan Modra1-5/+39
This patch supports using pcrel instructions in TLS code sequences. A number of new relocations are needed, gas operand modifiers to generate those relocations, and new TLS optimisation. For optimisation it turns out that the new pcrel GD and LD sequences can be distinguished from the non-pcrel GD and LD sequences by there being different relocations on the new sequence. The final "add ra,rb,13" on IE sequences similarly needs a new relocation, or as I chose, a modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points one byte into the "add" instruction rather than being on the instruction boundary. GD: pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC edited to IE pld 3,z@got@tprel@pcrel add 3,3,13 edited to LE paddi 3,13,z@tprel nop LD: pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC .. paddi 9,3,z2@dtprel pld 10,z3@got@dtprel@pcrel add 10,10,3 edited to LE paddi 3,13,0x1000 nop IE: pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34 add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1 ldx 4,9,z@tls@pcrel lwax 5,9,z@tls@pcrel stdx 5,9,z@tls@pcrel edited to LE paddi 9,13,z@tprel nop ld 4,0(9) lwa 5,0(9) std 5,0(9) LE: paddi 10,13,z@tprel include/ * elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34), (R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34), (R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define. (IS_PPC64_TLS_RELOC): Include new tls relocs. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34), (BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34), (BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34), (BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs. * elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs. (ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs. (must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64. (ppc64_elf_check_relocs): Support pcrel tls relocs. (ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel", "got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel". (fixup_size, md_assemble): Handle pcrel tls relocs. (ppc_force_relocation, ppc_fix_adjustable): Likewise. (md_apply_fix, tc_gen_reloc): Likewise. ld/ * testsuite/ld-powerpc/tlsgd.d, * testsuite/ld-powerpc/tlsgd.s, * testsuite/ld-powerpc/tlsie.d, * testsuite/ld-powerpc/tlsie.s, * testsuite/ld-powerpc/tlsld.d, * testsuite/ld-powerpc/tlsld.s: New tests. * testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-18gas: .lcomm gets an alignment argument in eBPFJose E. Marchesi1-1/+2
gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c: Make .lcomm to get a third argument with the alignment.
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi1-0/+3
This little patch adds support to the eBPF port of GAS for a few data directives. The names for the directives have been chosen to be coherent with the suffixes used in eBPF instructions: b, h, w and dw for 8, 16, 32 and 64-bit values respectively. Documentation and tests included. Tested in a x86_64 host. gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_pseudo_table): .half, .word and .dword. * testsuite/gas/bpf/data.s: New file. * testsuite/gas/bpf/data.d: Likewise. * testsuite/gas/bpf/data-be.d: Likewise. * testsuite/gas/bpf/bpf.exp: Run data and data-be. * doc/c-bpf.texi (BPF Directives): New section.
2019-07-17x86: replace "anymem" checks where possibleJan Beulich1-8/+14
Once operand parsing has completed, the simpler check of Operand_Mem can be used in places where i.types[] got passed to operand_type_check(). Note that this has shown a couple of omissions of adjusting i.flags[] when playing with i.op[] / i.types[] / i.tm.operand_types[]. Not all of them get added here, just all of the ones needed in process_operands().
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-12/+18
... instead of an operand type bit: It's an insn property, not an operand one. There's just one actual change to be made to the templates: Most are now required to have the (unswapped) destination go into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly and its operands swapped. {,V}MOVS{S,D}, otoh, are left alone in this regard, as otherwise generated code would differ from what we've been producing so far (which I don't think is wanted). Take the opportunity and add a missing IgnoreSize to pextrb (leading to an error in 16-bit mode), and take the liberty to once again drop stray IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16x86: fold SReg{2,3}Jan Beulich2-23/+22
They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
2019-07-09Re: gas/ELF: don't accumulate .type settingsAlan Modra3-29/+23
git commit f2d4ba38f5 caused many failures for mips-sgi-irix targets, and added a new test that failed for aarch64, nds32, and rl78. The mips failures are due to BSF_OBJECT being set in many cases for symbols by the mips .global/.globl directive. This patch removes that code and instead sets BSF_OBJECT in a target frob_symbol function, also moving the mips hacks in elf_frob_symbol to the new function. Note that common symbols are handled fine in elf.c:swap_out_syms without needing to set BSF_OBJECT, so that old code can disappear. * config/obj-elf.c (elf_frob_symbol): Remove mips hacks. * config/tc-mips.h (tc_frob_symbol): Define. (mips_frob_symbol): Declare. * config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix. (mips_frob_symbol): Fudge symbols for irix here. * testsuite/gas/elf/type-2.e: Allow random target symbols.
2019-07-04x86: correct "-Q" option handlingJan Beulich1-1/+3
For another patch I wanted to use a sufficiently benign option (simply to be able to specify one, which certain test case invocations require), and I stumbled across -Q in the --help output. Before realizing that this is x86-specific anyway, I've tried and and ran into a mysterious testsuite failure, until I further realized that other than the help text suggests the option requires an argument. Correct the help text, and make the implementation actually match what the comment there has been describing (and what the help text now says).
2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich2-1/+40
Recently a patch was submitted for a Xen Project test harness binary to override the compiler specified @object to @func (see [1]). In a reply I suggested we shouldn't make ourselves dependent on currently unspecified behavior of gas here: It accumulates all requests, and then bfd/elf.c:swap_out_syms(), in an apparently ad hoc manner, prioritizes certain flags over others. Make the behavior predictable: Generally the last .type is what counts. Exceptions are directives which set multiple bits (TLS, IFUNC, and UNIQUE): Subsequent directives requesting just the more generic bit (i.e. FUNC following IFUNC) won't clear the more specific one. Warn about incompatible changes, except from/to STT_NOTYPE. Also add a new target hook, which hppa wants to use right away afaict. In the course of adding the warning I ran into two ld testsuite failures. I can only assume that it was a copy-and-paste mistake that lead to the same symbol having its type set twice. [1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01980.html
2019-07-02This patch fixes a bug in the AArch64 assembler where an incorrect ↵Barnaby Wilks1-0/+9
structural load/store by element instruction would generate the wrong error message. For example, when provided with the (incorrect) instruction st4 {v0.16b-v3.16b}[4],[x0] currently assembler provides the following error message "Error: comma expected between operands at operand 2 -- `st4 {v0.16b-v3.16b}[4],[x0]'". This was due to the assembler consuming the {v0.16b-v3.16b} as the first operand leaving [4],[x0] as what it believed to be the second operand. The actual error is that the first operand should be of element type and not vector type (as provided). The new diagnostic for this error is "Error: expected element type rather than vector type at operand 1 -- `st4 {v0.16b-v3.16b}[4],[x0]'. Added testcases to check for the correct diagnostic message as well as checking that variations of the structural load/store by element instruction also generate the error when they have the same problem. * config/tc-aarch64.c (parse_operands): Add error check. * testsuite/gas/aarch64/diagnostic.l: New test. * testsuite/gas/aarch64/diagnostic.s: New test. * testsuite/gas/aarch64/illegal.l: New tests. * testsuite/gas/aarch64/illegal.s: New tests.
2019-07-01x86: drop Vec_Imm4Jan Beulich1-25/+11
It is pretty wasteful to have a per-operand flag which is used in exactly 4 cases. It can be relatively easily replaced, and by doing so I've actually found some dead code to remove at the same time (there's no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01x86: limit ImmExt abuseJan Beulich1-13/+10
In quite a few cases ImmExt gets used when there's not really any immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this case is supposed to be dealt with. Eliminate most abuses, leaving in place (for now) only ones where process_immext() is involved.
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-0/+23
It seems to be not uncommon for people to use AND or OR in this form for just setting the status flags. TEST, which doesn't write to any register other than EFLAGS, ought to be preferred. Make the change only for -O2 and above though, at least for now.
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-0/+43
When they're in the 0F opcode space, swapping their source operands may allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN behavior precludes us doing so for many packed and scalar floating point insns; such an optimization would need to be done by the compiler instead in this case, when it knows that NaN-s have undefined behavior anyway. While for explicitly specified AVX/AVX2 insns the optimization (for now at least) gets done only for -O2 and -Os, it is utilized by default in SSE2AVX mode, as there we're re-writing the programmer's specified insns anyway. Rather than introducing a new attribute flag, the change re-uses one which so far was meaningful only for EVEX-encoded insns.
2019-07-01x86: StaticRounding implies SAEJan Beulich1-6/+3
This implication allows to simplify some conditionals, thus slightly improving performance. This change also paves the way for re-using StaticRounding for non-EVEX insns.
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-11/+19
As long as there's no write mask as well as no broadcast, and as long as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the lower 16 XMM/YMM registers using their VEX equivalents with -O1. Also take the opportunity and avoid looping twice over all operands when dealing with memory-with-displacement ones.
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