| Age | Commit message (Collapse) | Author | Files | Lines |
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For jumps requiring multiple trampolines trampoline placement code may
place multiple sequential trampolines into the same frag. Don't do that.
gas/
2018-02-13 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xg_find_best_trampoline): Skip trampoline
frag that contains source address.
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ORR instruction.
PR 22773
* config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR
instruction before assuming that it is a MOV instruction.
* testsuite/gas/arm/pr22773.s: New test.
* testsuite/gas/arm/pr22773.d: New test driver.
* testsuite/gas/arm/pr22773.l: New expected output.
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Since there is no need to prepare for PLT branch on x86-64, generate
R_X86_64_PLT32, instead of R_X86_64_PC32, if possible, which can be
used as a marker for 32-bit PC-relative branches.
To compile Linux kernel, this patch:
From: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH] x86: Treat R_X86_64_PLT32 as R_X86_64_PC32
On i386, there are 2 types of PLTs, PIC and non-PIC. PIE and shared
objects must use PIC PLT. To use PIC PLT, you need to load
_GLOBAL_OFFSET_TABLE_ into EBX first. There is no need for that on
x86-64 since x86-64 uses PC-relative PLT.
On x86-64, for 32-bit PC-relative branches, we can generate PLT32
relocation, instead of PC32 relocation, which can also be used as
a marker for 32-bit PC-relative branches. Linker can always reduce
PLT32 relocation to PC32 if function is defined locally. Local
functions should use PC32 relocation. As far as Linux kernel is
concerned, R_X86_64_PLT32 can be treated the same as R_X86_64_PC32
since Linux kernel doesn't use PLT.
is needed. It is available on hjl/plt32/master branch at
https://github.com/hjl-tools/linux
bfd/
PR gas/22791
* elf64-x86-64.c (is_32bit_relative_branch): Removed.
(elf_x86_64_relocate_section): Check PIC relocations in PIE.
Remove is_32bit_relative_branch usage. Disallow PC32 reloc
against protected function in shared object.
gas/
PR gas/22791
* config/tc-i386.c (need_plt32_p): New function.
(output_jump): Generate BFD_RELOC_X86_64_PLT32 if possible.
(md_estimate_size_before_relax): Likewise.
* testsuite/gas/i386/reloc64.d: Updated.
* testsuite/gas/i386/x86-64-jump.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-1.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-3.d: Likewise.
* testsuite/gas/i386/ilp32/reloc64.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
ld/
PR gas/22791
* testsuite/ld-x86-64/mpx1c.rd: Updated.
* testsuite/ld-x86-64/pr22791-1.err: New file.
* testsuite/ld-x86-64/pr22791-1a.c: Likewise.
* testsuite/ld-x86-64/pr22791-1b.s: Likewise.
* testsuite/ld-x86-64/pr22791-2.rd: Likewise.
* testsuite/ld-x86-64/pr22791-2a.s: Likewise.
* testsuite/ld-x86-64/pr22791-2b.c: Likewise.
* testsuite/ld-x86-64/pr22791-2c.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run PR ld/22791 tests.
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incompatible function types.
PR 22823
bfd Fix compile time warnings generated by gcc version 8.
* libbfd-in.h: Remove extraneous text from prototypes.
Add prototypes for bfd_false_any, bfd_true_any,
bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any,
bfd_n1_any, bfd_void_any.
(_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy
function.
(_bfd_generic_bfd_merge_private_bfd_data): Likewise.
(_bfd_generic_bfd_set_private_flags): Likewise.
(_bfd_generic_bfd_copy_private_section_data): Likewise.
(_bfd_generic_bfd_copy_private_symbol_data): Likewise.
(_bfd_generic_bfd_copy_private_header_data): Likewise.
(_bfd_generic_bfd_print_private_bfd_data): Likewise.
(_bfd_noarchive_construct_extended_name_table): Likewise.
(_bfd_noarchive_truncate_arname): Likewise.
(_bfd_noarchive_write_ar_hdr): Likewise.
(_bfd_noarchive_get_elt_at_index): Likewise.
(_bfd_nosymbols_canonicalize_symtab): Likewise.
(_bfd_nosymbols_print_symbol): Likewise.
(_bfd_nosymbols_get_symbol_info): Likewise.
(_bfd_nosymbols_get_symbol_version_string): Likewise.
(_bfd_nosymbols_bfd_is_local_label_name): Likewise.
(_bfd_nosymbols_bfd_is_target_special_symbol): Likewise.
(_bfd_nosymbols_get_lineno): Likewise.
(_bfd_nosymbols_find_nearest_line): Likewise.
(_bfd_nosymbols_find_line): Likewise.
(_bfd_nosymbols_find_inliner_info): Likewise.
(_bfd_nosymbols_bfd_make_debug_symbol): Likewise.
(_bfd_nosymbols_read_minisymbols): Likewise.
(_bfd_nosymbols_minisymbol_to_symbol): Likewise.
(_bfd_norelocs_bfd_reloc_type_lookup): Likewise.
(_bfd_norelocs_bfd_reloc_name_lookup): Likewise.
(_bfd_nowrite_set_arch_mach): Likewise.
(_bfd_nowrite_set_section_contents): Likewise.
(_bfd_nolink_sizeof_headers): Likewise.
(_bfd_nolink_bfd_get_relocated_section_contents): Likewise.
(_bfd_nolink_bfd_relax_section): Likewise.
(_bfd_nolink_bfd_gc_sections): Likewise.
(_bfd_nolink_bfd_lookup_section_flags): Likewise.
(_bfd_nolink_bfd_merge_sections): Likewise.
(_bfd_nolink_bfd_is_group_section): Likewise.
(_bfd_nolink_bfd_discard_group): Likewise.
(_bfd_nolink_bfd_link_hash_table_create): Likewise.
(_bfd_nolink_bfd_link_add_symbols): Likewise.
(_bfd_nolink_bfd_link_just_syms): Likewise.
(_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise.
(_bfd_nolink_bfd_final_link): Likewise.
(_bfd_nolink_bfd_link_split_section): Likewise.
(_bfd_nolink_section_already_linked): Likewise.
(_bfd_nolink_bfd_define_common_symbol): Likewise.
(_bfd_nolink_bfd_define_start_stop): Likewise.
(_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise.
(_bfd_nodynamic_get_synthetic_symtab): Likewise.
(_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise.
(_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise.
* libbfd.c (bfd_false_any): New function. Like bfd_false but
accepts one or more arguments.
(bfd_true_any): Likewise.
(bfd_nullvoidptr_any): Likewise.
(bfd_0_any): Likewise.
(bfd_0u_any): Likewise.
(bfd_0l_any): Likewise.
(_bfd_n1_any): Likewise.
(bfd_void_any): Likewise.
* libbfd.h (extern): Regenerate
* aout-target.h (MY_bfd_is_target_special_symbol): Use vararg
based dummy function.
* aout-tic30.c (tic30_aout_set_arch_mach): Likewise.
* binary.c (binary_get_symbol_info): Likewise.
* coff-alpha.c (alpha_ecoff_backend_data): Likewise.
* coff-mips.c (mips_ecoff_backend_data): Likewise.
* coffcode.h (coff_set_alignment_hook): Likewise.
(symname_in_debug_hook): Likewise.
(bfd_coff_backend_data bigobj_swap_table): Likewise.
* elf-m10300.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-metag.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-score.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-score7.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise.
* elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise.
* elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise.
(bfd_elfNN_bfd_make_debug_symbol): Likewise.
(bfd_elfNN_bfd_merge_private_bfd_data): Likewise.
(bfd_elfNN_bfd_set_private_flags): Likewise.
(bfd_elfNN_bfd_is_target_special_symbol): Likewise.
(elf_backend_init_index_section): Likewise.
(elf_backend_allow_non_load_phdr): Likewise.
* elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise.
* i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise.
* ieee.c (ieee_construct_extended_name_table): Likewise.
(ieee_write_armap): Likewise.
(ieee_write_ar_hdr): Likewise.
(ieee_bfd_is_target_special_symbol): Likewise.
* ihex.c (ihex_canonicalize_symtab): Likewise.
(ihex_bfd_is_target_special_symbol): Likewise.
* libaout.h (aout_32_bfd_is_target_special_symbol): Likewise.
* libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise.
(_bfd_ecoff_set_alignment_hook): Likewise.
* mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise.
* mmo.c (mmo_bfd_is_target_special_symbol): Likewise.
* nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise.
* oasys.c (oasys_construct_extended_name_table): Likewise.
(oasys_write_armap): Likewise.
(oasys_write_ar_hdr): Likewise.
(oasys_bfd_is_target_special_symbol): Likewise.
* pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise.
* plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise.
* ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise.
* som.c (som_bfd_is_target_special_symbol): Likewise.
* srec.c (srec_bfd_is_target_special_symbol): Likewise.
* tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise.
* verilog.c (verilog_bfd_is_target_special_symbol): Likewise.
* versados.c (versados_bfd_is_target_special_symbol): Likewise.
(versados_bfd_reloc_name_lookup): Likewise.
* vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise.
(vms_bfd_define_start_stop): Likewise.
(alpha_vms_bfd_is_target_special_symbol): Likewise.
* wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise.
* xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise.
* elf32-arc.c (get_replace_function): Assign replacement function
to func pointer.
* elf32-i370.c (i370_noop): Update prototype.
gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant
casts.
(obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit.
(obj_elf_vtable_inherit): New stub function that calls
obj_elf_get_vtable_inherit.
(obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry.
(obj_elf_vtable_entry): New stub function that calls
obj_elf_get_vtable_entry.
* config/obj-elf.h (obj_elf_vtable_inherit): Update prototype.
(obj_elf_vtable_entry) Likewise.
(obj_elf_get_vtable_inherit) Likewise.
(obj_elf_get_vtable_entry) Likewise.
* config/tc-arm.c (md_pseudo_table): Remove now redundant cast.
* config/tc-i386c (md_pseudo_table): Likewise.
* config/tc-hppa.c (pa_vtable_entry): Call
obj_elf_get_vtable_entry.
(pa_vtable_inherit): Call obj_elf_get_vtable_inherit.
* config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file
with call to dwarf2_get_filename.
* dwarf2dbg.c (dwarf2_directive_file): Rename to
dwarf2_directive_filename.
(dwarf2_directive_file): New stub function that calls
dwarf2_directive_filename.
* dwarf2dbg.h: Prototype dwarf2_directive_filename.
opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning
about truncation of printing.
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Checks for insn alignment were hopelessly confused when misaligned
data starts a new frag. The real-world testcase happened to run out
of frag space in the middle of emitting a trace-back table via
something like:
.byte 0 /* VERSION=0 */
.byte 9 /* LANG=C++ */
.byte 34 /* Bits on: has_tboff, fp_present */
.byte 64 /* Bits on: name_present */
.byte 128 /* Bits on: stores_bc, FP_SAVED=0 */
.byte 0 /* Bits on: GP_SAVED=0 */
.byte 2 /* FIXEDPARMS=2 */
.byte 1 /* FLOATPARMS=0, parmsonstk */
.long 0
.long 768 /* tb_offset: 0x300 */
.hword 45 /* Function name length: 45 */
.long 0x334e5a5f
.long 0x31766f70
.long 0x65744932
.long 0x69746172
.long 0x7a5f6e6f
.long 0x64504533
.long 0x5f534e50
.long 0x72463431
.long 0x61746361
.long 0x74535f6c
.long 0x74637572
.byte 0x45
.byte 0
The trigger being those misaligned .long's output for the function
name. A most horrible way to output a string, especially considering
endian issues..
PR 22819
* config/tc-ppc.c (md_assemble): Rewrite insn alignment checking.
(ppc_frag_check): Likewise.
* testsuite/gas/ppc/misalign.d,
* testsuite/gas/ppc/misalign.l,
* testsuite/gas/ppc/misalign.s: New test.
* testsuite/gas/ppc/misalign2.d,
* testsuite/gas/ppc/misalign2.s: New test.
* testsuite/gas/ppc/ppc.exp: Run them.
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Correct a commit f0531ed6a429 ("Compress loads/stores with implicit 0
offset.") regression and remove a `-Wshadow' compilation error:
cc1: warnings being treated as errors
.../gas/config/tc-riscv.c: In function 'riscv_handle_implicit_zero_offset':
.../gas/config/tc-riscv.c:1194: error: declaration of 'expr' shadows a global declaration
.../gas/expr.h:180: error: shadowed declaration is here
make[4]: *** [tc-riscv.o] Error 1
which for versions of GCC before 4.8 prevents GAS for RISC-V targets
from being built. See also GCC PR c/53066.
gas/
* config/tc-riscv.c (riscv_handle_implicit_zero_offset): Rename
`expr' parameter to `ep'.
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The .dc.a directive has wrong size (32 bits) on SPARC 64-bit because
the assembler sets the correct BFD architecture only at the very end
of the processing and it's too late for the directive. It's fixed by
defining TARGET_MACH and making it return a sensible default value.
gas/
* config/tc-sparc.h (sparc_mach): Declare.
(TARGET_MACH): Define to above.
* config/tc-sparc.c (sparc_mach): New function.
(sparc_md_end): Minor tweak.
ld/
* testsuite/ld-elf/pr22450.d: Remove reference to SPARC64.
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This is a patch to add the gas support for group relocations to create a
16, 32, 48, or 64 bit PC-relative offset inline.
The following relocations are added along with the test cases:
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
bfd/
2018-01-24 Renlin Li <renlin.li@arm.com>
* reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
gas/
2018-01-24 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reloc_table): add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
(md_apply_fix): Likewise
* testsuite/gas/aarch64/prel_g0.s: New.
* testsuite/gas/aarch64/prel_g0.d: New.
* testsuite/gas/aarch64/prel_g0_nc.s: New.
* testsuite/gas/aarch64/prel_g0_nc.d: New.
* testsuite/gas/aarch64/prel_g1.s: New.
* testsuite/gas/aarch64/prel_g1.d: New.
* testsuite/gas/aarch64/prel_g1_nc.s: New.
* testsuite/gas/aarch64/prel_g1_nc.d: New.
* testsuite/gas/aarch64/prel_g2.s: New.
* testsuite/gas/aarch64/prel_g2.d: New.
* testsuite/gas/aarch64/prel_g2_nc.s: New.
* testsuite/gas/aarch64/prel_g2_nc.d: New.
* testsuite/gas/aarch64/prel_g3.s: New.
* testsuite/gas/aarch64/prel_g3.d: New.
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Complement commit 23fce1e31156 ("MIPS16 intermix test failure"),
<https://sourceware.org/ml/binutils/2009-01/msg00335.html>, and
remove a stale option marker entry.
gas/
* config/tc-mips.c (options): Remove OPTION_COMPAT_ARCH_BASE
enum value.
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Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel PCONFIG instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .pconfig.
* doc/c-i386.texi: Document .pconfig.
* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
* testsuite/gas/i386/pconfig-intel.d: New test.
* testsuite/gas/i386/pconfig.d: Likewise.
* testsuite/gas/i386/pconfig.s: Likewise.
* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
* i386-dis.c (enum): Add pconfig.
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
(cpu_flags): Add CpuPCONFIG.
* i386-opc.h (enum): Add CpuPCONFIG.
(i386_cpu_flags): Add cpupconfig.
* i386-opc.tbl: Add PCONFIG instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel WBNOINVD instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
* doc/c-i386.texi: Document .wbnoinvd.
* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
* testsuite/gas/i386/wbnoinvd-intel.d: New test.
* testsuite/gas/i386/wbnoinvd.d: Likewise.
* testsuite/gas/i386/wbnoinvd.s: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F09.
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
(cpu_flags): Add CpuWBNOINVD.
* i386-opc.h (enum): Add CpuWBNOINVD.
(i386_cpu_flags): Add cpuwbnoinvd.
* i386-opc.tbl: Add WBNOINVD instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Remove an issue with `as --help' always reporting `o32' as the default
ABI regardless of what the default actually is, originally caused by
commit cac012d6d394 ("check mips abi x linker emulation compatibility"),
<https://sourceware.org/ml/binutils/2003-05/msg00187.html> missing an
update here.
gas/
* config/tc-mips.c (md_show_usage): Correctly indicate the
configuration-specific default ABI.
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Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") GAS
bug and add missing help text for the `-mmips16e2' and `-mno-mips16e2'
options added with said commit.
gas/
* config/tc-mips.c (md_show_usage): Report `-mmips16e2' and
`-mno-mips16e2' options.
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ie: \"
PR 22737
* config/tc-rx.c (rx_start_line): Handle escaped double-quote character.
* testsuite/gas/rx/pr22737.s: New test.
* testsuite/gas/rx/pr22737.d: Likewise.
* testsuite/gas/rx/rx.exp: Run the new test.
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Remove spurious comments after the definition of ToC and ToU.
2018-01-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (ToC macro): Remove spurious comment.
(ToU macro): Likewise.
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gas/
* config/tc-riscv.c (validate_riscv_insn) <'z'>: New.
(riscv_ip) <'z'>: New.
opcodes/
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
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The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Armv8-M Security Extensions introduced some Thumb-only opcodes
(eg. sg). These are defined using the TUE and TCE macros, setting the
Arm execution state related fields to 0/NULL.
This patch adds 2 new macros to avoid filling this field and clearly
identify Thumb-only instructions.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (ToC): Define macro.
(ToU): Likewise.
(insns): Make use of above macros for new instructions introduced in
Armv8-M.
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|
Newly introduced instructions common to ARMv8-M Baseline and Mainline
are currently all marked as unconditional. However, all instructions but
sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually
support conditional execution. This patch fixes the definition of these
instructions accordingly.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
and vlstm conditionally executable and reindent parameters.
* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
aforementionned instructions.
|
|
Deprecations related to the use of the IT instruction introduced in
Armv8-A do not apply to Armv8-M Baseline and mainline. However the
warning logic do not distinguish between the various profiles and warn
whenever the architecture version is 8.
This patch adds a check to exclude M profile architectures from this
warning. This works as expected when -march is specified on the
command-line or a .arch/.cpu directive exist. However, in autodetection
mode the CPU/architecture targeted is only known once the instructions
have been all processed but this code is run when IT instruction is
processed. It is therefore not possible to distinguish between Armv8-M
and Armv8-A in that mode.
The approach chosen here is not to warn in autodetection mode. The udf.d
testcase that relied on that behavior to test deprecation warning for
Armv8-A is therefore updated to explicitely pass -march=armv8-a.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M
profile architecture or if in autodetection mode. Clarify that
deprecation is for performance reason and concerns Armv8-A and Armv8-R.
* testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning
message.
* testsuite/gas/arm/armv8-ar-it-bad.l: Likewise.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise.
* testsuite/gas/arm/udf.l: Likewise.
* testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
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|
Occasionally I build an out-of-tree a.out target (m68k-amigaos). After
a system upgrade which included a newer compiler (clang 4) the build
produces warnings like this:
warning: macro expansion producing 'defined' has undefined behavior
[-Wexpansion-to-defined]
This is caused by the macro gas/config/aout_gnu.h:USE_EXTENDED_RELOC.
Since it is in a header file, the warning triggers for several files.
I am unsure what solution is preferable, thus I am suggesting two
patches:
a) keep the offending macro but define it explicitly to 0 and 1
b) replace the macro usage with its value where it is used.
Either patch removes the warning for clang. I did not check with a
recent GCC.
* gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly
define to 0 and 1. Remove a dangling reference to "AMD 29000"
in a comment.
|
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* config/tc-arm.c (aeabi_set_public_attributes): Avoid false
positive "‘profile’ may be used uninitialized".
|
|
CSDB is a new instruction which Arm has defined. As it shares the
encoding space with NOP instructions, it is available from Armv3 in
Arm mode, and Armv6T2 in Thumb mode.
OK? If so, please commit on my behalf as I don't have commit rights
over here.
Thanks, James
---
opcodes/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
gas/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
in Arm execution state, and Armv6T2 and above in Thumb execution
state.
* testsuite/gas/arm/csdb.s: New.
* testsuite/gas/arm/csdb.d: New.
* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
|
|
|
|
PR 18119
* config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked
version of ARM MRS instruction.
|
|
gas/
* config/tc-riscv.c (risc_ip) <o>: Add comment.
* testsuite/gas/riscv/c-nonzero-imm.d,
* testsuite/gas/riscv/c-nonzero-imm.l,
* testsuite/gas/riscv/c-nonzero-imm.s,
* testsuite/gas/riscv/c-nonzero-reg.d,
* testsuite/gas/riscv/c-nonzero-reg.l,
* testsuite/gas/riscv/c-nonzero-reg.s,
* testsuite/gas/riscv/c-zero-imm-64.d,
* testsuite/gas/riscv/c-zero-imm-64.s,
* testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s,
* testsuite/gas/riscv/c-zero-reg.d,
* testsuite/gas/riscv/c-zero-reg.s: New.
opcodes/
* riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New.
(riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co.
<andi, and, add, addiw, addw, c.addi>: Change Cj to Co.
<add>: Add explanatory comment for 4-operand add instruction.
<c.nop>: Add support for immediate operand.
<c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add.
<c.lui>: Use match_c_lui_with_hint instead of match_c_lui.
<c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.
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|
Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:
v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.
Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.
gas/
PR gas/22559
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.
include/
PR gas/22559
* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.
opcodes/
PR gas/22559
* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
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|
Previously parse_vector_type_for_operand was changed to allow the use of 4b
register size for indexed lane instructions. However this had the unintended
side effect of also allowing 4b for normal vector registers.
Because this support was only partial the rest of the tool silently treated
4b as 8b and continued. This patch adds full support for 4b so it can be
properly distinguished from 8b and the correct errors are generated.
With this patch you still can't encode any instruction which actually requires
v<num>.4b but such instructions don't exist so to prevent needing a workaround
in get_vreg_qualifier_from_value this was just omitted.
gas/
PR gas/22529
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
* gas/testsuite/gas/aarch64/pr22529.s: New.
* gas/testsuite/gas/aarch64/pr22529.d: New.
* gas/testsuite/gas/aarch64/pr22529.l: New.
include/
PR gas/22529
* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.
opcodes/
PR gas/22529
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
|
|
onto the stack.
PR 22493
* config/tc-arm.c (encode_ldmstm): Do not use A2 encoding of the
PUSH insn when pushing the stack pointer.
|
|
Just like for instructions in GPRs, there's no need to have separate
templates for otherwise identical insns acting on XMM or YMM registers
(or memory of the same size).
|
|
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
|
|
Express them as Reg|Tbyte and Acc|Tbyte respectively.
|
|
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.
Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
|
|
Pseudo prefixes must be used on an instruction. Issue an error when
pseudo prefix is used without instruction.
PR gas/22623
* gas/config/tc-i386.c (output_insn): Check pseudo prefix
without instruction.
* testsuite/gas/i386/i386.exp: Run inval-pseudo.
* testsuite/gas/i386/inval-pseudo.l: New file.
* testsuite/gas/i386/inval-pseudo.s: Likewise.
|
|
Again these look to be typos: No template currently allows for any two
(or all three) of RegXMM, RegYMM, and RegZMM in a single operand. Quite
clearly ! are missing, after the addition of which the checks for the
first and (if present) second operands also fully match up.
|
|
I'm rather certain the missing ! was just a typo, the more with the
similar check in mind that's in the same function a few hundred lines
down (in the body of "if (vex_reg != (unsigned int) ~0)"). Of course
this can't be demonstrated by a test case - internal data structure
consistency is being checked here, and neither form of the check
triggers with any current template.
It is also not really clear to me why operand_type_equal() is being used
in the {X,Y,Z}MM register check here, rather than just testing the
respective bits: Just like Reg32|Reg64 is legal in an operand template,
I don't see why e.g. RegXMM|RegYMM wouldn't be. For example it ought to
be possible to combine
vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
into a single template (with setting of VEX.L suitably handled elsewhere
if that's not already happening anyway).
Additionally I don't understand why this uses abort() instead of
gas_assert().
Both of these latter considerations then also apply to the
aforementioned other check in the same function.
|
|
using the old address.
top * COPYING.LIBGLOSS: Update address of FSF in copyright notice.
bfd * cpu-mt.c: Update address of FSF in copyright notice.
* elf32-m32c.c: Likewise.
* elf32-mt.c: Likewise.
* elf32-rl78.c: Likewise.
* elf32-rx.c: Likewise.
* elf32-rx.h: Likewise.
* elf32-spu.h: Likewise.
* hosts/x86-64linux.h: Likewise.
etc * add-log.el: Update address of FSF in copyright notice.
gas * config/tc-m32c.c: Update address of FSF in copyright notice.
* config/tc-m32c.h: Likewise.
* config/tc-mt.c: Likewise.
* config/tc-mt.h: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-visium.h: Likewise.
* testsuite/gas/rx/explode: Likewise.
ld * testsuite/ld-mn10300/mn10300.exp: Update address of FSF in
copyright notice.
|
|
It's obviously wrong to mask SPRs to 8 bits.
PR 21118
* config/tc-ppc.c (md_assemble): Don't mask register number.
|
|
Don't use address where symbol gets resolved, as during section
relaxation symbols will slide, instead canonicalize symbols and check
that they are are the same.
This fixes a bug when a relaxed jump goes into the wrong trampoline.
gas/
2017-12-07 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xg_order_trampoline_chain): Replace
xg_order_trampoline_chain_entry call with check for
canonicalized symbol equality and offset equality.
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|
include/
* opcode/ppc.h (PPC_INT_FMT): Define.
(struct powerpc_opcode) <opcode>: Update type.
(struct powerpc_opcode) <mask>: Likewise.
(struct powerpc_opcode) <bitm>: Likewise.
(struct powerpc_opcode) <insert>: Likewise.
(struct powerpc_opcode) <extract>: Likewise.
(ppc_optional_operand_value): Likewise.
gas/
* config/tc-ppc.c (last_insn): Update type.
(insn_validate) <omask, mask>: Likewise.
(ppc_setup_opcodes) <mask, right_bit>: Likewise.
<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
(ppc_insert_operand): Update return and argument types and remove
unneeded type casts.
<min, max, right, tmp>: Update type.
(md_assemble): Remove unneeded type casts.
<insn, val, tmp_insn>: Update type.
opcodes/
* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
(operand_value_powerpc): Update return and argument type.
<value, top>: Update type.
(skip_optional_operands): Update argument type.
(lookup_powerpc): Likewise.
(lookup_vle): Likewise.
<table_opcd, table_mask, insn2>: Update type.
(lookup_spe2): Update argument type.
<table_opcd, table_mask, insn2>: Update type.
(print_insn_powerpc) <insn, value>: Update type.
Use PPC_INT_FMT for printing instructions and operands.
* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
|
|
This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
|
|
While we shouldn't outright reject such (as was wrongly done by commit
4d36230d59 ("x86: Update segment register check in Intel syntax"), as
MASM accepts them even silently, issue (by default) a warning for such
questionable constructs.
|
|
This reverts commit 4d36230d59903b92fbe2b53b31ed64a884860f0e.
I was committed without maintainer ack and regresses intended
functionality. A replacement will be committed shortly.
|
|
gas/
* config/tc-riscv.c (riscv_frag_align_code): New local insn_alignment.
Early return if bytes less than or equal to insn_alignment.
* testsuite/gas/riscv/align-1.l: New.
* testsuite/gas/riscv/align-1.s: New.
* testsuite/gas/riscv/riscv.exp: Use run_dump_tests. Use run_list_test
for align-1.
|
|
This should be an obvious fix.
It corrects the register number for IP1 to 17.
gas/
2017-11-29 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reg_names): Fix IP1 register alias error.
* testsuite/gas/aarch64/register_aliases.s: Add IP0 and IP1 tests.
* testsuite/gas/aarch64/register_aliases.d: Update.
|
|
user has already created the section.
PR 22492
* config/obj-elf.c (obj_elf_version): Use record_alignment rather
than bfd_set_section_alignment.
|
|
gas/
* config/tc-riscv.c (riscv_handle_implicit_zero_offset): New.
(riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to
riscv_handle_implicit_zero_offset. At label load_store, replace
existing code with call to riscv_handle_implicit_zero_offset.
* testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New.
* testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New.
* testsuite/gas/riscv/riscv.exp: Run new tests.
|
|
find_trampoline_seg takes noticeable time when assembling source with
many sections. Cache the result of the most recent search and check it
first. No functional changes.
gas/
2017-11-27 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (find_trampoline_seg): Add static variable
that caches the result of the most recent search.
|
|
There is a recurring pattern in assembly files generated by a compiler
where a lot of jumps in a function are going to the same place. When
these jumps are relaxed with trampolines the assembler generates a
separate jump thread from each source.
Create an index of trampoline jump targets for each segment and see if a
jump being relaxed goes to a location from that index, in which case
replace its target with a location of existing trampoline jump that
results in the shortest path to the original target.
gas/
2017-11-27 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (trampoline_chain_entry, trampoline_chain)
(trampoline_chain_index): New structures.
(trampoline_index): Add chain_index field.
(xg_order_trampoline_chain_entry, xg_sort_trampoline_chain)
(xg_find_chain_entry, xg_get_best_chain_entry)
(xg_order_trampoline_chain, xg_get_trampoline_chain)
(xg_find_best_eq_target, xg_add_location_to_chain)
(xg_create_trampoline_chain, xg_get_single_symbol_slot): New
functions.
(xg_relax_fixups): Call xg_find_best_eq_target to adjust jump
target to point to an existing jump. Call
xg_create_trampoline_chain to create new jump target. Call
xg_add_location_to_chain to add newly created trampoline jump
to the corresponding chain.
(add_jump_to_trampoline): Extract loop searching for a single
slot with a symbol into a separate function, replace that code
with a call to that function.
(relax_frag_immed): Call xg_find_best_eq_target to adjust jump
target to point to an existing jump.
* testsuite/gas/xtensa/all.exp: Add trampoline-2 test.
* testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses
as many duplicate trampoline chains are now coalesced.
* testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump
stays in sync with instruction stream.
* testsuite/gas/xtensa/trampoline-2.l: New test result file.
* testsuite/gas/xtensa/trampoline-2.s: New test source file.
|
|
There's almost exact copy of the trampoline placement code in the
search_trampolines function that is used for jumps generated for relaxed
branch instructions. Get rid of the duplication and reuse
xg_find_best_trampoline function for that.
gas/
2017-11-27 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (search_trampolines, get_best_trampoline):
Remove definitions.
(xg_find_best_trampoline_for_tinsn): New function.
(relax_frag_immed): Replace call to get_best_trampoline with a
call to xg_find_best_trampoline_for_tinsn.
* testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses
as the placement of trampolines for relaxed branches has been
changed.
|
