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2024-06-18Support APX CCMP and CTESTCui, Lili1-1/+145
CCMP and CTEST are two new sets of instructions for conditional CMP and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST in the instruction mnemonic, e.g.: ccmp<cc> { dfv=sf , cf , of } %eax, %ecx also add {evex} cmp/test %eax, %ecx as an alias for ccmpt. For the encoder part, add function check_Scc_OszcOperation to parse '{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode, and adjust base_opcode to its normal meaning in install_template. For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags suffixes. gas/ChangeLog: * config/tc-i386.c (OSZC_CF): New. (OSZC_ZF): Ditto. (OSZC_SF): Ditto. (OSZC_OF): Ditto. (set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice. (check_Scc_OszcOperations): Handle SCC OSZC flags. (install_template): Add scc and oszc_flags. (build_apx_evex_prefix): Encode SCC and oszc flags bits. (parse_insn): Handle check_Scc_OszcOperations. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add ccmp and ctest. * i386-dis-evex.h: Ditto. * i386-dis.c (struct instr_info): add scc. (struct dis386): Add new micro 'NE','SC' and'DF'. (get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn. (putop): Handle %NE, %SC and %DF. * i386-opc.h (SCC): New. * i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2024-06-18LoongArch: add .option directiveLulu Cai1-0/+59
In some cases we may want to use different options only for certain assembly, so the .option directive is added to control the assembler options. .option can accept 4 parameters: push pop Pushes or pops the current option stack. They limit the scope of option changes so that they do not affect other parts of the assembly file. relax norelax Enables or disables relaxation.
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas1-0/+8
The FEAT_BRBE extension provides two aliases of sys: - brb iall (Invalidates all Branch records in the Branch Record Buffer) - brb inj (Injects the Branch Record held in BRBINFINJ_EL1, BRBSRCINJ_EL1, and BRBTGTINJ_EL1 into the Branch Record Buffer) This patch adds: - the feature option "brbe" that must be added for the aliases to be available - a new operand flag AARCH64_OPND_Rt_IN_SYS_ALIASES that warns in a comment when Rt is set to the non default value 0b11111 (it is constrained unpredictable whether the instruction is undefined or behaves as if the Rt field is set to 0b11111). - a new operand flag AARCH64_OPND_BRBOP that encodes and decodes Op2 values from bit 5 - support for the two brb aliases above See: - https://developer.arm.com/documentation/ddi0602/2024-03/Base-Instructions/BRB--Branch-Record-Buffer--an-alias-of-SYS-?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-INJ--Branch-Record-Injection-into-the-Branch-Record-Buffer?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-IALL--Invalidate-the-Branch-Record-Buffer?lang=en
2024-06-12RISC-V: Support S[sm]csrind extension csrs.Jiawei1-0/+22
This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs. Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs in Smaia/Ssaia extension. bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (enum riscv_csr_class): New extensions. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extensions. include/ChangeLog: * opcode/riscv-opc.h (CSR_MIREG2): New csr. (CSR_MIREG3): Ditto. (CSR_MIREG4): Ditto. (CSR_MIREG5): Ditto. (CSR_MIREG6): Ditto. (CSR_SIREG2): Ditto. (CSR_SIREG3): Ditto. (CSR_SIREG4): Ditto. (CSR_SIREG5): Ditto. (CSR_SIREG6): Ditto. (CSR_VSIREG2): Ditto. (CSR_VSIREG3): Ditto. (CSR_VSIREG4): Ditto. (CSR_VSIREG5): Ditto. (CSR_VSIREG6): Ditto. (DECLARE_CSR): Ditto.
2024-06-10aarch64: warn on unpredictable results for new rcpc3 instructionsMatthieu Longo1-1/+39
The previous patch for the feature rcpc3 introduced 4 new operations (ldiapp, stilp, ldapr, stlr). The specification mentions some cases of inputs causing unpredictable results. gas currently fails to diagnose them, and does not emit warnings. Even if the instruction encoding is valid, the developer probably wants to know for those cases that the instruction won't have the expected effect. - ldiapp & stilp: * unpredictable load pair transfer with register overlap * unpredictable transfer with writeback - ldapr & stlr: * unpredictable transfer with writeback This patch also completes the existing relevant tests.
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-1/+5
Extremely rarely used attributes are inefficient when represented by a separate attribute. Convert it to an operand constraint, as already suggested during review. The collision with RegKludge is pretty simple to resolve.
2024-06-05arm: remove FPA instructions from assemblerRichard Earnshaw1-699/+0
These can no-longer be generated as the options to reach them have now gone. So remove the parsing support for FPA instructions.
2024-06-05arm: remove options to select the FPARichard Earnshaw1-15/+1
Remove the command-line options to choose the FPA (or FPE - an emulated FPA). From this point on it should be impossible to assemble the old FPA instructions.
2024-06-05arm: change default FPUs from FPA to noneRichard Earnshaw1-62/+63
Change the cases where the default FPU was FPA to none. This should ensure that any code that used settings to pick the floating-point order will not silently produce a different output. The options that explicitly set the FPA remain for the moment.
2024-06-05arm: redirect fp constant data directives through a wrapperRichard Earnshaw1-5/+20
Assembler directives such as .float, or .double are handled by generic code, but on Arm, their output can vary depeding on the type of FPU begin targetted. When we remove FPA support we don't want to silently generate different code for processors that previously defaulted to the FPA, so redirect these directives through a wrapper function that checks the FPU is enabled; we use the legacy -mno-fpu in the test to catch this. Also fix a few tests so that they won't start to fail on targets (eg arm-wince-pe) where there is no default format for the FPU and we pick this from the default processor type.
2024-06-05arm: adjust FPU selection logicRichard Earnshaw1-9/+2
The logic here seems to be overly complex, so simplify it a bit. One particular problem was that using the legacy -mno-fpu option was not working properly, as this has all the feature bits set to zero causing the code to then pick a different FPU as the default. Fix this by only selecting an FPU as a fallback if the code has not otherwise selected one: there was only one route by which this could happen. This patch is really a pre-cursor to the following one where we want to make no-fpu internally a fall-back position for some legacy processors where previously we would have dropped back to the FPA.
2024-06-05arm: default to softvfp on armv6 or later coresRichard Earnshaw1-17/+17
From armv6 onwards a lot of cores started to come with a physical VFP implementation; but many still did not and in some cases there are both variants. For the cores that lacked a physical VFP we would fall back to FPU_NONE if the platform/ABI did not mandate something else. To make matters worse, FPU_NONE is internal state used to imply soft-fpa (ie a mixed-endian double format), so any use of .double in hand-written assembly is almost certainly generating incorrect output. That's undesirable, all these cores should really default to a softvfp model.
2024-06-05arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFPRichard Earnshaw5-58/+96
FPU_ARCH_VFP has always meant VFP floating-point format (natural FP word order) but without any VFP instructions. But the name FPU_ARCH_VFP is potentially confusing. This patch just changes the name to make the meaning clearer.
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-1/+11
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> Nazareno Bruschi <nazareno.bruschi@embecosm.com> Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions.
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang2-1/+65
R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only created at the first time to handle alignment directive. This means that all other sections may use this symbol. If the section of this symbol is discarded, there may be problems. Search it in its own section. Remove elf_backend_data.is_rela_normal() function added at commit daeda14191c. Co-authored-by: Jinyang He <hejinyang@loongson.cn> Reported-by: WANG Xuerui <git@xen0n.name> Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t
2024-05-31x86: reduce check_{byte,word,long,qword}_reg() overheadJan Beulich1-4/+15
These run after template matching. Therefore it is quite pointless for them to check all operands, when operand sizes matching across operands is already known. Exit the loops early in such cases. In check_byte_reg() also drop a long-stale part of a comment.
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-0/+13
Except for very few insns mnemonic suffixes aren't permitted in Intel syntax. Warn about such for now, indicating that they will be outright refused down the road. While fiddling with testcases to address fallout, drop a few things which should never have been tested as valid Intel syntax. Also add a previously missing line to simd-suffix.d.
2024-05-29x86/Intel: SHLD/SHRD have dual meaningJan Beulich1-2/+5
Since we uniformly permit D suffixes in Intel mode whenever in AT&T mode an L suffix may be used, we need to be consistent with this. Take the easy route, despite that still leading to an anomaly which is also visible from the new testcase: shld eax, ecx, 1 shld eax, ecx, cl can mean two things with APX: SHL with a D suffix in NDD EVEX encoding, or the traditional SHLD in legacy encoding.
2024-05-29PR31796, Internal error in write_function_pdata at obj-coff-sehAlan Modra1-2/+22
PR31796 is the result of lack of aarch64 support in obj-coff-seh.c. Nick fixed this with commit 73c8603c3f. Make the seh support consistently warn in future if some archictecture is missing, rather than giving internal errors. PR 31796 * config/obj-coff-seh.c (verify_target): New function. (obj_coff_seh_handler, obj_coff_seh_endproc, obj_coff_seh_proc), (obj_coff_seh_endprologue): Use it.
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com1-0/+3
Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions use new SVE2 vector operands. They are called SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have 1 bit, 2 bit, and 3 bit indices respectively. The lsb and width of these new operands are the same as many existing operands but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h. We made a design choice for the second operand of the halfword variant of luti4 with two register tables. We could have either defined a new operand, like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With the new operand, we would need to implement constraints on register lists based on either operand or opcode flag. With existing operand, we could just existing constraint checks using opcode flag. We chose the second approach and went with SVE_ZnxN and added opcode flag to enforce lengths of vector register list operands. This way, we can reuse the existing constraint check logic.
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com1-0/+67
Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions needed definition of some new operands. We will first discuss operands for the third operand of the instructions and then discuss a vector register list operand needed for the second operand. The third operands are vectors with bit indices and without type qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 and they have 1 bit, 2 bit, and 3 bit indices respectively. For these new operands, we defined new parsing case branch. The lsb and width of these operands are the same as many existing but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h for these new operands. For the second operand of these instructions, we introduced a new operand called LVn_LUT. This represents a vector register list with stride 1. We defined new inserter and extractor for this new operand and it is encoded in FLD_Rn. We are enforcing the number of registers in the reglist using opcode flag rather than operand flag as this is what other SIMD vector register list operands are doing. The disassembly also uses opcode flag to print the correct number of registers.
2024-05-28Fix: internal error in write_function_pdata at obj-coff-sehNick Clifton1-0/+5
PR 31796
2024-05-24x86: simplify VexVVVV_SRC2 handling for the XOP caseJan Beulich1-9/+5
As already suggested during review, rather than having an extra conditional in build_modrm_byte() (a code path used for quite a few more insns, including even certain GPR ones), adjust the attribute in the installed template to properly describe things with operands swapped.
2024-05-24x86: simplify / consolidate check_{word,long,qword}_reg()Jan Beulich1-16/+4
These run after template matching. Therefore operands are already known to match the template in use. With the loop bodies skipping anything not a GPR in the actual operands, there's therefore no need to check the template's operand type for permitting Reg or Accum. At the same time bring the three functions in sync for the "byte" part of the logic, as far as checking the template for other sizes (qword specifically) goes. Plus drop a stale comment from check_qword_reg(), when all three are now behaving the same in this regard.
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich1-5/+47
Properly reject inappropriate suffixes (No_lSuf / No_qSuf mistakenly omitted by cf665fee1d6c ["x86: re-work AVX512 embedded rounding / SAE"]), to avoid emitting bad or arbitrarily guessed instructions. Interestingly check_{long,qword}_suffix() don't help here, which perhaps is another indication that the way they work right now isn't quite appropriate. Sadly correcting just the templates breaks operand ambiguity detection, since so far that worked from a single template permitting more than one suffix. Here we have ambiguity though which can now be noticed only when taking all (matching) templates together. Therefore we need to determine further matching templates (see code comments for constraints), to then accumulate permitted suffixes across all of them.
2024-05-22Support APX zero-upperCui, Lili1-2/+3
This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-22X86: Remove "i.rex" to eliminate extra conditional branchCui, Lili1-1/+1
Resulting code will do better without the extra conditional branch. Remove "i.rex" to eliminate extra conditional branch. gas/ChangeLog: * config/tc-i386.c (establish_rex): Remove i.rex.
2024-05-22Add check for 8-bit old registers in EVEX formatCui, Lili1-3/+4
Since APX supports EVEX from legacy instructions, we need to check the 8-bit old registers in EVEX format. And add test cases for it. gas/ChangeLog: * config/tc-i386.c (md_assemble): Add invalid check for old byte registers in EVEX format. * testsuite/gas/i386/x86-64-apx-inval.l: Add new test. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
2024-05-22x86: Split REX/REX2 old registers judgment.Cui, Lili1-16/+14
Split "REX/REX2 old register checking" and "add empty rex prefix" into two separate branches. gas/ChangeLog: * config/tc-i386.c (establish_rex): Split the judgments.
2024-05-21gas: drop remnants of ia64-*-aix*Jan Beulich1-23/+0
With BFD not supporting that target anymore, GAS can't possibly support it either.
2024-05-20RISC-V: PR31733, Change initial CFI operation from DW_CFA_def_cfa_register ↵Sung-hun Kim1-1/+1
to DW_CFA_def_cfa The DWARF specification (especially, DWARF4 and 5 [1,2]) states that DW_CFA_def_cfa_register cannot be used as the first CFI operation. It said DW_CFA_def_cfa_register as follows: ... This operation is valid only if the current CFA rule is defined to use a register and offset. So, DW_CFA_def_cfa_register can be used after that other definition operation such as DW_CFA_def_cfa is called. However, the current gas code emits DW_CFA_def_cfa_register as an initial CFI operation for RISCV. In the libgcc, the unwinding function does not care about it, so it can unwind the call stack. However, on the third party library such as libunwindstack in Android, it causes a fatal error. This patch changes the initial CFI operation to DW_CFA_def_cfa with offset 0. It works as same as the previous one, but it does not have any limitation so it satisfies the DWARF spec. This change resolves the compatibility issue while preserving the original behaviour. [1] DWARF4 specification, https://dwarfstd.org/doc/DWARF4.pdf [2] DWARF5 specification, https://dwarfstd.org/doc/DWARF5.pdf Signed-off-by: Sung-hun Kim <sfoon.kim@samsung.com> Reviewed-By: Andrew Burgess <aburgess@redhat.com> Approved-By: Nelson Chu <nelson@rivosinc.com> gas/ PR 31733 config/tc-riscv.c (riscv_cfi_frame_initial_instructions): Use DW_CFA_def_cfa rather than DW_CFA_def_cfa_register.
2024-05-17LoongArch: gas: Adjust DWARF CIE alignment factorsmengqinggang1-5/+9
Set DWARF2_CIE_DATA_ALIGNMENT (data alignment factors) to -8. It helps to save space. Data Alignment Factor A signed LEB128 encoded value that is factored out of all offset instructions that are associated with this CIE or its FDEs. This value shall be multiplied by the register offset argument of an offset instruction to obtain the new offset value.
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+1
2024-05-16arm: remove incorrect handling of FP bignums in move_or_literal_poolRichard Earnshaw1-6/+24
This hunk of code in move_or_literal_pool just looks wrong, but I can't find a testcase that will tickle it to prove it. It looks a bit like it was intended to catch cases where a bignum contained a floating-point value, but there were a number of problems with it. - It tested X_add_number == -1, but an FP bignum is indicated by any value <= 0. - It converted the floating-point value to extended precision, but that's not used on Arm beyond the legacy FPA code. No attempt was made to match the FP value to the intended memory/mov operation. Since I can't construct a viable testcase, I've just removed the existing code and made the function error out in this case: this seems more sensible than generating wrong code or trying to write something more complex that can't be tested anyway.
2024-05-15aarch64: Add sysreg features to +d128 dependenciesAndrew Carlotti1-2/+5
We should revisit sysreg feature enablement and dependencies in future, but this change should help until then. OK for master?
2024-05-15aarch64: Add simd dependency to +sha2Andrew Carlotti1-1/+1
This matches the existing behaviour in GCC and LLVM, and also the current documentation. OK for master?
2024-05-14arm: remove Maverick support from the assembler.Richard Earnshaw1-179/+4
Delete all the Maverick instructions and register handling from the assembler. We continue to recognize -mcpu=ep9312, but treat it as an alias for arm920t. We no-longer recognize -mfpu=maverick.
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili1-6/+3
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of extension_opcode to encode the vvvv register. * testsuite/gas/i386/x86-64-sse2avx.d: Added new testcases. * testsuite/gas/i386/x86-64-sse2avx.s: Diito. opcodes/ChangeLog: * i386-opc.tbl: Added DstVVVV to some extension_opcode instructions. * i386-tbl.h: Regenerated.
2024-05-06x86: Drop SwapSourcesCui, Lili1-8/+11
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of SWAP_SOURCES to encode the vvvv register. opcodes/ChangeLog: * i386-opc.h (SWAP_SOURCES): Dropped. (NO_DEFAULT_MASK): Adjusted the value. (ADDR_PREFIX_OP_REG): Ditto. (DISTINCT_DEST): Ditto. (IMPLICIT_STACK_OP): Ditto. (VexVVVV_SRC2): New. * i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-15/+17
Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV. Src1VVVV means using VEX.vvvv encodes the first source register operand. The old logic did not check vexvvvv first, which made the logic here very complicated. gas/ChangeLog: * config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV. (build_modrm_byte): Used vexvvvv to encode the vvvv register. (s_insn): Replaced 1 with Src1VVVV. opcodes/ChangeLog: * i386-opc.h (VexVVVV_DST): Adjusted the value. (Src1VVVV): New. * i386-opc.tbl: Replaced part VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich1-2/+7
Legacy encoded SIMD insns are converted to AVX ones in that mode. When eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where available; there are quite a few which can't be converted). Note that LDDQU is represented as VMOVDQU32 (and the prior use of the sse3 template there needs dropping, to get the order right). Note further that in a few cases, due to the use of templates, AVX512VL is used when AVX512F would suffice. Since AVX10 is the main reference, this shouldn't be too much of a problem.
2024-04-25bpf: fix calculation when deciding to relax branchDavid Faust1-4/+33
In certain cases we were calculating the jump displacement incorrectly when deciding whether to relax a branch. This meant for some branches, such as a very long backwards conditional branch, relaxation was not done when it should have been. The result was to error later, because the actual jump displacement was too large to fit in the original instruction. This patch fixes up the displacement calculation so that those branches are correctly relaxed and no longer result in an error. In addition, it changes md_convert_frag to install fixups for the JAL instructions in the resulting relaxations rather than encoding the displacement value directly. gas/ * config/tc-bpf.c (relaxed_branch_length): Correct displacement calculation when relaxing. (md_convert_frag): Likewise. Install fixups for JAL instructions resulting from relaxation. * testsuite/gas/bpf/jump-relax-ja-be.d: Correct and expand test. * testsuite/gas/bpf/jump-relax-ja.d: Likewise. * testsuite/gas/bpf/jump-relax-ja.s: Likewise. * testsuite/gas/bpf/jump-relax-jump-be.d: Likewise. * testsuite/gas/bpf/jump-relax-jump.d: Likewise. * testsuite/gas/bpf/jump-relax-jump.s: Likewise.
2024-04-25LoongArch: gas: Simplify relocations in sections without code flagJinyang He1-3/+1
Gas should not emit ADD/SUB relocation pairs for label differences if they are in the same section without code flag even relax enabled. Because the real value is not be affected by relaxation and it can be compute out in assembly stage. Thus, correct the `TC_FORCE_RELOCATION _SUB_SAME` and the label differences in same section without code flag can be resolved in fixup_segment().
2024-04-23arm: Fix MVE vmla encodingClaudio Bantaloukas1-2/+2
2024-04-22x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili1-1/+4
gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Added invalid check for APX X4. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added invalid testcase. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get_valid_dis386): Added invalid check for APX X4.
2024-04-20LoongArch: Add -mignore-start-align optionmengqinggang1-20/+50
Ignore .align at the start of a section may result in misalignment when partial linking. Manually add -mignore-start-align option without partial linking. Gcc -falign-functions add .align 5 to the start of a section, it causes some error message mismatch. Set these testcases to xfail on LoongArch target.
2024-04-16x86: Fix a memory leak in md_assembleH.J. Lu1-5/+8
Fix a memory leak in md_assemble where copy may be cleared and may be the same as copy: if (copy && !mnem_suffix) { line = copy; copy = NULL; no_match: * config/tc-i386.c (md_assemble): Properly free the xstrdup memory.
2024-04-10x86-64: Use long NOPs for Intel Core processorsH.J. Lu1-5/+35
Use long NOPs for Intel Core processors since they are faster than multiple NOPs. Don't use them for 64-bit processors by default since Intel Atom processors can only decode 4 prefixes in 1 cycle. * config/tc-i386.c (alt64_9): New. (alt64_10): Likewise. (alt64_11): Likewise. (alt64_12): Likewise. (alt64_13): Likewise. (alt64_14): Likewise. (alt64_15): Likewise. (alt64_patt): Likewise. (i386_generate_nops): Use alt64_patt for Intel Core processors in 64-bit mode. * testsuite/gas/i386/x86-64-nops-1-core2.d: Expect long NOPs. * testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Replace ../x86-64-nops-1.d with ../x86-64-nops-1-core2.d. * testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Replace ../x86-64-nops-4.d with ../x86-64-nops-4-core2.d.
2024-04-09arm: Fix encoding of MVE vqshr[u]nAlex Coplan1-4/+4
As it stands, these insns are incorrectly encoded as vqrshr[u]n. Concretely, the problem can be seen as follows: $ cat t.s vqrshrnb.s16 q0,q0,#8 vqshrnb.s16 q0,q0,#8 $ gas/as-new t.s -march=armv8.1-m.main+mve -o t.o $ binutils/objdump -d t.o -m armv8.1-m.main t.o: file format elf32-littlearm Disassembly of section .text: 00000000 <.text>: 0: ee88 0f41 vqrshrnb.s16 q0, q0, #0 4: ee88 0f41 vqrshrnb.s16 q0, q0, #0 Here we assemble these two instructions to the same opcode. The encoding of the first is the correct, while the encoding of the second is incorrect, and the bottom bit should be clear, see the Armv8-M ARM: https://developer.arm.com/documentation/ddi0553/latest/ There is an additional problem here in that the disassembly of the immediate is incorrect. llvm-objdump shows the correct disassembly here: t.o: file format elf32-littlearm Disassembly of section .text: 00000000 <$t>: 0: ee88 0f41 vqrshrnb.s16 q0, q0, #8 4: ee88 0f41 vqrshrnb.s16 q0, q0, #8 Note that we defer adding a test for the correct encoding of these insns until the next patch which fixes the disassembly issue.
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei1-0/+181
Support zcmp extension push/pop/popret and popret zero instructions. The `reg_list' is a list containing 1 to 13 registers, we can use: "{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}" to present this feature. Passed gcc/binutils regressions of riscv-gnu-toolchain. Most of work was finished by Sinan Lin. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp. (riscv_supported_std_z_ext): Added zcmp with version 1.0. (riscv_parse_check_conflicts): Zcmp conflicts with d/zcd. (riscv_multi_subset_supports): Handle zcmp. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (regno_to_reg_list): New function, used to map register to reg_list number. (reglist_lookup): Called reglist_lookup_internal. Return false if reg_list number is zero, which is an invalid value. (reglist_lookup_internal): Parse register list, and return the last register by regno_to_reg_list. (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test. * testsuite/gas/riscv/zcmp-push-pop.d: New test. * testsuite/gas/riscv/zcmp-push-pop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp. (MATCH/MASK_CM_POP): Ditto. (MATCH/MASK_CM_POPRET): Ditto. (MATCH/MASK_CM_POPRETZ): Ditto. (DECLARE_INSN): New declarations for zcmp. * opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm operand for zcmp. (OP_MASK_REG_LIST): Handle operand for zcmp register list. (OP_SH_REG_LIST): Ditto. (ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base. (X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers. (enum riscv_insn_class): Added INSN_CLASS_ZCMP. (extern riscv_get_sp_base): Added. opcodes/ChangeLog: * riscv-dis.c (print_reg_list): New function, used to get zcmp reg_list field. (riscv_get_spimm): New function, used to get zcmp sp adjustment immediate. (print_insn_args): Handle new operands for zcmp. * riscv-opc.c (riscv_get_sp_base): New function, used by gas and objdump. Get sp base adjustment. (riscv_opcodes): Added zcmp instructions.
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