Age | Commit message (Collapse) | Author | Files | Lines |
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* config/tc-m68k.c (md_begin): Support 64bit host.
(get_num): Support 64bit BFD on 32bit host.
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* config/tc-mips.c (md_apply_fix3): Fix typos in BFD_RELOC_64.
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SEC_MERGE sections.
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2005-04-06 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (tc_gen_reloc): Don't turn
BFD_RELOC_X86_64_32S into BFD_RELOC_32.
gas/testsuite/
2005-04-06 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-pcrel.s: Test R_X86_64_32S.
* gas/i386/x86-64-pcrel.d: Updated.
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(xtensa_find_unaligned_branch_targets, get_aligned_diff,
future_alignment_required): Use branch_align_power to check section
alignment as well as xtensa_fetch_width when aligning branch targets.
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(xtensa_fetch_width): Change to unsigned.
(assemble_nop, xtensa_find_unaligned_branch_targets,
xtensa_find_unaligned_loops, xg_assemble_vliw_tokens,
is_narrow_branch_guaranteed_in_range, xtensa_fix_close_loop_end_frags,
min_bytes_to_other_loop_end, unrelaxed_frag_min_size,
unrelaxed_frag_max_size, xtensa_fix_short_loop_frags,
count_insns_to_loop_end, unrelaxed_frag_min_insn_count,
get_text_align_max_fill_size, get_text_align_nop_count,
get_text_align_nth_nop_size, get_noop_aligned_address,
get_aligned_diff, convert_frag_align_next_opcode,
convert_frag_immed_finish_loop, xtensa_create_property_segments,
xtensa_create_xproperty_segments, xt_block_aligned_size): Clean up
types, avoiding size_t and using offsetT and addressT appropriately.
(get_text_align_power): Clean up types. Avoid incorrect bound.
(get_text_align_fill_size): Clean up types. Restructure for clarity.
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2005-04-04 H.J. Lu <hongjiu.lu@intel.com>
* elf.c (bfd_elf_set_group_contents): Ignore linker created
group section.
(assign_section_numbers): Accept link_info. Check SHT_GROUP
sections for relocatable files only. Remove the linker created
group sections.
(_bfd_elf_compute_section_file_positions): Pass link_info to
assign_section_numbers.
* elfxx-ia64.c (elfNN_ia64_object_p): New.
(elf_backend_object_p): Defined.
gas/
2005-04-04 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ia64.c (start_unwind_section): Undo the change
of 2004-08-18.
(generate_unwind_image, dot_endp): Likewise.
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* config/tc-ia64.c (ia64_handle_align): Move le_nop and
le_nop_stop arrays and initializers to file scope.
(md_begin): When generating code for anything other than
Itanium 1, use MMI instead of MFI NOP bundles as a filler.
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2005-04-01 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (output_imm): Also set sign flag for 64-bit push
immediates.
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for the VAX target in order to be more compatible with the VAX MACRO assembler.
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2005-04-01 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (s_bss): Call obj_elf_section_change_hook.
gas/testsuite/
2005-04-01 Jan Beulich <jbeulich@novell.com>
* gas/i386/bss.[sd]: New.
* gas/i386/i386.exp: Run new test.
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2005-04-01 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (md_apply_fix3): Also handle BFD_RELOC_X86_64_32S.
(tc_gen_reloc): Handle BFD_RELOC_X86_64_32S in the default case.
gas/testsuite/
2005-04-01 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-pcrel.[sd]: New.
* gas/i386/i386.exp: Run new test.
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bfd_elf32_is_arm_mapping_symbol_name.
* bfd/bfd-in2.h: Regenerate.
* bfd/cpu-arm.c (bfd_is_arm_mapping_symbol_name): Rename from
bfd_elf32_is_arm_mapping_symbol_name.
* bfd/elf32-arm.c (elf32_arm_is_target_special_symbol): Rename
bfd_elf32_is_arm_mapping_symbol_name to bfd_is_arm_mapping_symbol_name.
(arm_elf_find_function): Likewise.
(elf32_arm_output_symbol_hook): Likewise.
* gas/config/tc-arm.c (arm_adjust_symtab): Likewise.
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* bfd/bfd-in2.h: Regenerate.
* bfd/elf32-arm.c (elf32_arm_is_target_special_symbol): Rename call to
bfd_elf32_is_arm_mapping_symbol_name.
(elf32_arm_output_symbol_hook): Likewise.
(arm_elf_find_function): Likewise, and include STT_NOTYPE in test for
mapping symbols.
(is_arm_mapping_symbol_name): Function moved from here...
* bfd/cpu-arm.c (bfd_elf32_is_arm_mapping_symbol_name): ...to here,
renamed and made global.
* gas/config/tc-arm.c (mapping_state): Change documentation in function
comment to cross-reference spec instead. Change type of mapping symbols
to BSF_NO_TYPE.
(arm_adjust_symtab): Don't change type of mapping symbols here.
* gas/testsuite/gas/arm/mapping.d: Update expected output.
* ld/testsuite/ld-arm/arm-app-abs32.d: Likewise.
* ld/testsuite/ld-arm/arm-app.d: Likewise.
* ld/testsuite/ld-arm/mixed-app.d: Likewise.
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* bfd-in2.h, libbfd.h: Regenerated.
* reloc.c: Add ARM TLS relocations.
* elf32-arm.c (elf32_arm_howto_table): Add dynamic TLS
relocations.
(elf32_arm_tls_gd32_howto, elf32_arm_tls_ldo32_howto)
(elf32_arm_tls_ldm32_howto, elf32_arm_tls_le32_howto)
(elf32_arm_tls_ie32_howto): New.
(elf32_arm_howto_from_type): Support TLS relocations.
(elf32_arm_reloc_map): Likewise.
(elf32_arm_reloc_type_lookup): Likewise.
(TCB_SIZE): Define.
(struct elf32_arm_obj_tdata): New.
(elf32_arm_tdata, elf32_arm_local_got_tls_type): Define.
(elf32_arm_mkobject): New function.
(struct elf32_arm_relocs_copied): Add pc_count.
(elf32_arm_hash_entry, GOT_UNKNOWN, GOT_NORMAL, GOT_TLS_GD)
(GOT_TLS_IE): Define.
(struct elf32_arm_link_hash_table): Add tls_ldm_got.
(elf32_arm_link_hash_newfunc): Initialize tls_type.
(elf32_arm_copy_indirect_symbol): Copy pc_count and tls_type.
(elf32_arm_link_hash_table_create): Initialize tls_ldm_got.
(dtpoff_base, tpoff): New functions.
(elf32_arm_final_link_relocate): Handle TLS relocations.
(IS_ARM_TLS_RELOC): Define.
(elf32_arm_relocate_section): Warn about TLS mismatches.
(elf32_arm_gc_sweep_hook): Handle TLS relocations and pc_count.
(elf32_arm_check_relocs): Detect invalid symbol indexes. Handle
TLS relocations and pc_count.
(elf32_arm_adjust_dynamic_symbol): Check non_got_ref.
(allocate_dynrelocs): Handle TLS. Bind REL32 relocs to local
calls.
(elf32_arm_size_dynamic_sections): Handle TLS.
(elf32_arm_finish_dynamic_symbol): Likewise.
(bfd_elf32_mkobject): Define.
gas/
* config/tc-arm.c (arm_parse_reloc): Add TLS relocations.
(md_apply_fix3): Mark TLS symbols.
(tc_gen_reloc): Handle TLS relocations.
(arm_fix_adjustable): Ignore TLS relocations.
(s_arm_elf_cons): Support expressions after decorated symbols.
gas/testuite/
* gas/arm/tls.s, gas/arm/tls.d: New files.
* gas/arm/arm.exp: Run TLS test.
include/elf/
* arm.h: Add TLS relocations.
ld/testsuite/
* ld-arm/tls-lib.s, ld-arm/tls-lib.d, ld-arm/tls-lib.r,
ld-arm/tls-app.s, ld-arm/tls-app.d, ld-arm/tls-app.r: New files.
* ld-arm/arm-lib.ld, ld-arm/arm-dyn.ld: Increase data segment
alignment.
* ld-arm/arm-elf.exp: Run TLS tests.
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indicates whether personality routine index N has been output for this
section.
(mapping_state): tc_segment_info_data now struct not enum.
(arm_elf_change_section): Likewise, and marked_pr_dependency is now
handled on section change.
(create_unwind_entry): Previous code to output dependency removed.
(s_arm_unwind_fnend): Output dependency if it hasn't been done already
for this section.
* gas/config/tc-arm.h (TC_SEGMENT_INFO_TYPE): Redefined as struct
arm_segment_info_type.
(arm_segment_info_type): New struct.
* gas/testsuite/gas/arm/unwind.d: Update expected output.
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(xtensa_frob_label): Compute "freq" before possibly switching frags.
Insert a LOOP_END frag before every loop target, and do not overload
DESIRE_ALIGN_IF_TARGET frags with loop end information.
(xg_assemble_vliw_tokens): Use do_align_targets.
(xtensa_fix_target_frags): Remove code to convert a
DESIRE_ALIGN_IF_TARGET frag to a LOOP_END frag when there is a
negatable branch at the end of a loop.
(frag_can_negate_branch): Delete.
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2005-03-28 David Mosberger <davidm@hpl.hp.com>
H.J. Lu <hongjiu.lu@intel.com>
PR 803
NEWS: Mention "-mtune=[itanium1|itanium2]".
* config/tc-ia64.c (md): Add tune.
(md_parse_option): Accepted "-mtune=[itanium1|itanium2]".
(md_show_usage): Add "-mtune=[itanium1|itanium2]".
(extra_goodness): Prefer M- and I-unit NOPs for itanium2. F and
B unit NOPs are discouraged for McKinley-derived cores.
(md_begin): Don't hardcode the "extra_goodness()" function in
the comment...
(ia64_init): Set md.tune to itanium2.
* doc/as.texinfo: Add -mtune=[itanium1|itanium2]".
* doc/c-ia64.texi: Likewise.
gas/testsuite/
2005-03-28 H.J. Lu <hongjiu.lu@intel.com>
PR 803
* gas/ia64/dv-imply.d: Pass -mtune=itanium1 to as.
* gas/ia64/dv-mutex.d : Likewise.
* gas/ia64/dv-safe.d: Likewise.
* gas/ia64/dv-srlz.d.nop: Likewise.
* gas/ia64/ldxmov-1.d: Likewise.
* gas/ia64/opc-b.d: Likewise.
* gas/ia64/opc-f.d: Likewise.
* gas/ia64/opc-i.d: Likewise.
* gas/ia64/opc-m.d: Likewise.
* gas/ia64/operand-or.d: Likewise.
* gas/ia64/pcrel.d: Likewise.
* gas/ia64/pseudo.d: Likewise.
* gas/ia64/tls.d: Likewise.
ld/testsuite/
2005-03-28 H.J. Lu <hongjiu.lu@intel.com>
PR 803
* ld-ia64/ia64.exp: Pass -mtune=itanium1 to as.
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bad C_EFCN symbol, print its name.
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(xg_symbolic_immeds_fit): Check for direct calls and return TRUE if
the use_longcalls flag is set. Do this before checking the segment.
(xg_expand_assembly_insn): Rearrange to use new do_expand flag. Never
expand direct calls at this point.
(xtensa_set_frag_assembly_state): Set use_longcalls flag.
(xtensa_find_unmarked_state_frags): Likewise.
(md_assemble): Do not disable longcalls by setting is_specific_opcode.
(xg_assemble_vliw_tokens): Switch frags when use_longcalls changes.
(convert_frag_immed): Remove unnecessary check of is_specific_opcode.
* config/tc-xtensa.h (xtensa_frag_type): Add use_longcalls flag.
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* config/tc-cris.c: Ditto.
(md_estimate_size_before_relax): Remove obsolete comment for
parameter "segment_type".
(md_begin): Document reason for cast of hash_insert argument.
(md_atof): Correct type of parameter "type".
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attributes properly.
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relocations correctly as well.
(mips_fix_adjustable): Don't make BFD_RELOC_MIPS16_LO16
relocations in mergeable sections section-relative either.
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for sh_symbian_find_elf_flags.
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* config/tc-m68k.c (TRUNC, SEXT): Define.
(issbyte, isubyte, issword, isuword, isbyte, isword): Use the above.
(m68k_ip): Truncate or sign extend expressions as appropriate.
(get_num): Likewise.
(md_apply_fix3): Use SEXT.
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xg_apply_fix_value and return a value to indicate success.
(md_pcrel_from): Skip check of fx_done. Return 0 if not PC-relative.
(xtensa_force_relocation): Remove checks for VTABLE relocs.
(xtensa_validate_fix_sub): New.
(xtensa_fix_adjustable): Remove check for external or weak symbols.
(tc_gen_reloc): Move code to handle difference of symbols and code to
apply tentative fix values to ...
(md_apply_fix3): ...here. Enable standard overflow checks for simple
8, 16, and 32 bit relocations. Apply fixes for slot-specific
relocations when linkrelax flag is not set.
* config/tc-xtensa.h (xtensa_validate_fix_sub): Add prototype.
(TC_FORCE_RELOCATION_SUB_SAME, TC_VALIDATE_FIX_SUB): Define.
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2005-03-17 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (i386_scale): Beautify error message.
(Intel syntax comments): Update.
(struct intel_parser_s): Add fields in_offset, in_bracket, and
next_operand.
(intel_e04_1, intel_e05_1, intel_e05_1, intel_e09_1, intel_e10_1):
Remove declarations.
(intel_bracket_expr): Declare.
(i386_intel_operand): Initialize new intel_parser fields. Wrap most
of the function body in a loop allowing to split an operand into two.
Replace calls to malloc and checks of it returning non-NULL with
calls to xmalloc/xstrdup.
(intel_expr): SHORT no longer handled here. Add comment indicating
comparison ops need implementation.
(intel_e04, intel_e04_1): Combine, replace recursion with loop.
Check right operand of - does not specify a register when parsing
the address of a memory reference.
(intel_e05, intel_e05_1): Combine, replace recursion with loop.
Check operands do not specify a register when parsing the address of
a memory reference.
(intel_e06, intel_e06_1): Likewise.
(intel_e09, intel_e09_1): Combine, replace recursion with loop. Also
handle SHORT as well as unary + and -. Don't accept : except for
segment overrides or in direct far jump/call insns.
(intel_brack_expr): New.
(intel_e10, intel_e10_1): Combine, replace recursion with loop. Use
intel_brack_expr.
(intel_e11): Replace chain of if/else-if by switch, alloing fall-
through in certain cases. Use intel_brack_expr. Add new diagnostics.
Allow symbolic constants as register scale value.
(intel_get_token): Replace call to malloc and check of return value
with call to xmalloc. Change handling for FLAT to match MASM's.
(intel_putback_token): Don't try to back up/free current token if
that is T_NIL.
gas/testsuite/
2005-03-17 Jan Beulich <jbeulich@novell.com>
* gas/i386/intel.d: Add stderr directive.
* gas/i386/intel.e: New.
* gas/i386/intel16.d: Add stderr directive. Adjust for changed
source.
* gas/i386/intel16.e: New.
* gas/i386/intel16.s: Add instances of addressing forms with base
and index specified in reverse order.
* gas/i386/intelbad.l: Adjust for changed source.
* gas/i386/intelbad.s: Add more operand forms to check.
* gas/i386/intelok.d: Remove -r from objdump options. Add stderr
directive. Adjust for changed source.
* gas/i386/intelok.e: New.
* gas/i386/intelok.s: Define MASM constants byte, word, etc. Add
more operand forms to check.
* gas/i386/x86_64.d: Add stderr directive.
* gas/i386/x86_64.e: New.
* gas/i386/x86_64.s: Adjust for parser changes.
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* config/tc-arm.c (meabi_flags): Check EABI_DEFAULT.
* config/te-armeabi.h: New file.
* config/te-armlinuxeabi.h (EABI_DEFAULT): Define.
* config/te-symbian.h: Include "te-armeabi.h".
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is_mls parameter; do not diagnose Rm==Rd when is_mls.
(do_mla, do_mls, five_bit_unsigned_immediate, bfci_lsb_and_width)
(do_bfc, do_bfi, do_bfx, do_rbit, do_mov16, do_ldsttv4): New functions.
(insns): Add ARMv6T2 instructions:
bfc bfi mls movw movt rbit sbfx ubfx ldrht ldrsht ldrsbt strht.
(arm_archs): Add V6T2 variants.
testsuite:
* gas/arm/archv6t2.d, gas/arm/archv6t2.s: New dump test.
* gas/arm/archv6t2-bad.l, gas/arm/archv6t2-bad.l: New errors test.
* gas/arm/arm.exp: Run them.
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2005-03-14 Eric Christopher <echristo@redhat.com>
* config/tc-mips.c: Include dw2gencfi.h.
(mips_cfi_frame_initial_instructions): New.
* config/tc-mips.h (TARGET_USE_CFIPOP): Define.
(tc_cfi_frame_initial_instructions): Ditto.
(DWARF2_DEFAULT_RETURN_COLUMN): Ditto.
(DWARF2_CIE_DATA_ALIGNMENT): Ditto.
* Makefile.am: Update dependencies.
* Makefile.in: Regenerate.
==> testsuite/ChangeLog <==
2005-03-14 Eric Christopher <echristo@redhat.com>
* gas/cfi/cfi-mips-1.d, gas/cfi/cfi-mips-1.s: New dump test.
* gas/cfi/cfi.exp: Run it.
* gas/cfi/cfi-common-1.d: Update.
* gas/cfi/cfi-common-2.d: Ditto.
* gas/cfi/cfi-common-3.d: Ditto.
* gas/cfi/cfi-common-4.d: Ditto.
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* config/tc-arm.c (tinsns): Add ARMv6K instructions sev, wfe,
wfi, yield.
opcodes:
* arm-dis.c (thumb_opcodes): Add ARMv6K instructions nop, sev,
wfe, wfi, yield.
gas/testsuite:
* gas/arm/thumbv6k.d, gas/arm/thumbv6k.s: New dump test.
* gas/arm/arm.exp: Run it.
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* configure.in: Remove fmt=vms support.
* config.in: Regenerate.
* configure: Regenerate.
* config/obj-vms.h, config/obj-vms.c, config/vms-conf.h: Remove.
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when checking if xg_resolve_literals needs to be called.
* config/tc-xtensa.h: Fix spelling typo in a comment.
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2005-03-10 Jan Beulich <jbeulich@novell.com>
* config/tc-tic54x.h (tic54x_macro_info): Change parameter type.
* config/tc-tic54x.c (tic54x_macro_info): Likewise. Replace hand-
crafted structure declarations with the types from macro.h.
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for -mno-shared optimization.
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(MAX_NOPS): Bump to 4.
(mips_fix_vr4130): New variable.
(nops_for_vr4130): New function.
(nops_for_insn): Use MAX_DELAY_NOPS rather than MAX_NOPS. Use
nops_for_vr4130 if working around VR4130 errata.
(OPTION_FIX_VR4130, OPTION_NO_FIX_VR4130): New macros.
(md_longopts): Add -mfix-vr4130 and -mno-fix-vr4130.
(md_parse_option): Handle them.
(md_show_usage): Print them.
* doc/c-mips.texi: Document -mfix-vr4130 and -mno-fix-vr4130.
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branch delay code.
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(mips_emit_delays): Declare.
(md_flush_pending_output): Use mips_emit_delays.
* config/tc-mips.c (mips_no_prev_insn): Remove parameter; always forget
the previous instructions.
(md_begin, append_insn, md_parse_option): Update callers.
(mips_emit_delay): Remove parameter. Move INSNS != 0 code to
start_noreorder.
(mips_align, s_change_sec, s_cons, s_float_cons, s_gpword)
(s_gpdword): Update callers.
(start_noreorder, end_noreorder): New functions.
(macro, macro2, mips16_macro, s_mipsset): Use them instead of
manipulating mips_opts or prev_nop_frag directly.
(mips_flush_pending_output): Delete.
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(append_insn, mips_emit_delays): ...here.
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(history): Resize to 1 + MAX_NOPS.
(fix_vr4120_class): New enumeration.
(vr4120_conflicts): New variable.
(init_vr4120_conflicts): New function.
(md_begin): Call it.
(insn_uses_reg): Constify first argument.
(classify_vr4120_insn, insns_between, nops_for_insn, nops_for_sequence)
(nops_for_insn_or_target): New functions.
(append_insn): Use the new nops_for_* functions instead of inline
delay checks. Generalize prev_nop_frag handling to handle an
arbitrary history length. Insert nops into the history buffer
once the number of nops in prev_nop_frag is fixed.
(emit_delays): Use nops_for_insn instead of inline delay checks.
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check from branch delay code. Remove unnecessary check for branches.
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(nop_insn, mips16_nop_insn): New variables.
(NOP_INSN): New macro.
(insn_length, create_insn, install_insn, move_insn, add_fixed_insn)
(add_relaxed_insn, insert_into_history, emit_nop): New functions.
(md_begin): Initialize nop_insn and mips16_nop_insn.
(append_insn): Use the new emit_nop function to add nops, recording
them in the history buffer. Use add_fixed_insn or add_relaxed_insn
to reserve room for the instruction and install_insn to install the
final form. Use insert_into_history to record the instruction in
the history buffer. Use move_insn to do delay slot filling.
(mips_emit_delays): Use add_fixed_insn instead of the emit_nop macro.
(macro_build, mips16_macro_build, macro_build_lui, mips_ip)
(mips16_ip): Use create_insn to initialize mips_cl_insns.
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(EXTRACT_OPERAND, MIPS16_INSERT_OPERAND, MIPS16_EXTRACT_OPERAND): New.
(insn_uses_reg, reg_needs_delay, append_insn, macro_build)
(mips16_macro_build, macro_build_lui, mips16_macro, mips_ip)
(mips16_ip): Use the new macros instead of explicit masks and shifts.
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