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AgeCommit message (Expand)AuthorFilesLines
2018-03-30Make power8 the default cpu when assembling for 64-bit little endian targets.Peter Bergner1-1/+5
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li1-6/+46
2018-03-28x86: drop VecESizeJan Beulich1-14/+12
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-25/+45
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich1-2/+6
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+20
2018-03-22x86: use local variable in check_VecOperands()Jan Beulich1-7/+8
2018-03-22ix86: allow HLE store of accumulator to absolute addressJan Beulich1-0/+8
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-2/+5
2018-03-22x86: fold a few XOP templatesJan Beulich1-4/+8
2018-03-16RISC-V: Emit better warning for unknown CSR.Jim Wilson1-6/+11
2018-03-14RISC-V: Add .insn support.Jim Wilson1-27/+413
2018-03-09x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu1-1/+2
2018-03-09x86: Strip whitespace in check_VecOperationsH.J. Lu1-0/+6
2018-03-08x86: Optimize with EVEX128 encoding for AVX512VLH.J. Lu1-8/+11
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-7/+12
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-21/+1
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-6/+39
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich1-3/+4
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich2-43/+24
2018-03-08x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich1-7/+9
2018-03-08x86: fold redundant expressions in process_suffix()Jan Beulich1-20/+13
2018-03-08x86: simplify result processing of cpu_flags_match()Jan Beulich1-24/+16
2018-03-08x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich1-1/+11
2018-03-08x86: change AVX512VL handling in cpu_flags_match()Jan Beulich1-11/+5
2018-03-08x86: drop CPU_FLAGS_32BIT_MATCHJan Beulich1-5/+4
2018-03-08x86: simplify AVX checks in cpu_flags_match()Jan Beulich1-22/+6
2018-03-08x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCHJan Beulich1-6/+0
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich1-1/+5
2018-03-08x86: drop FloatDJan Beulich1-7/+7
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich1-12/+13
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-10/+37
2018-03-08Really remove unnecessary power9 group terminating nopAlan Modra1-4/+2
2018-03-08Remove unnecessary power9 group terminating nopAlan Modra1-10/+8
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu2-154/+147
2018-03-02[ARM] Fix NULL dereference of march_ext_optThomas Preud'homme1-1/+1
2018-03-01[ARM] Clean up selection of feature bitsThomas Preud'homme1-111/+127
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-2/+7
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-2/+234
2018-02-23nds32: Support target directive .ict_model.Kuan-Lin Chen1-1/+52
2018-02-22Diagnose when trying to assemble conditional FP16 vmovx and vinsAndre Simoes Dias Vieira1-0/+14
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu1-0/+27
2018-02-22Fix memory access violation when attempting to shorten a suffixed micromips i...A. Wilcox1-1/+1
2018-02-20gas: xtensa: limit size of auto litpoolsMax Filippov1-42/+77
2018-02-17Add .nop assembler directiveH.J. Lu2-106/+171
2018-02-15Fix AArch32 build attributes for Armv8.4-A.Tamar Christina1-1/+1
2018-02-13gas: xtensa: fix trampoline placementMax Filippov1-0/+6
2018-02-13Fix ARm assembler so that it rejects invalid immediate values for the Thumb O...Nick Clifton1-3/+5
2018-02-13x86-64: Generate branch with PLT32 relocationH.J. Lu1-1/+48
2018-02-13Fix compile time warning messages from gcc version 8 about cast between incom...Nick Clifton6-12/+32
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