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2019-12-12i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu1-3/+2
Similar to SP, BP, SI and DI registers, R12-R15 registers must use REX prefix for the low byte register when optimizing test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 PR gas/25274 * config/tc-i386.c (optimize_encoding): Also check R12-R15 registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8" optimization. * testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test with r12. * testsuite/gas/i386/x86-64-optimize-3.d: Updated. * testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
2019-12-12i386: Add -mbranches-within-32B-boundariesH.J. Lu1-0/+13
Add -mbranches-within-32B-boundaries to enable -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5 * config/tc-i386.c (OPTION_MBRANCHES_WITH_32B_BOUNDARIES): New. (md_longopts): Add -mbranches-within-32B-boundaries. (md_parse_option): Handle -mbranches-within-32B-boundaries. (md_show_usage): Add -mbranches-within-32B-boundaries.
2019-12-12i386: Align branches within a fixed boundaryH.J. Lu2-3/+1074
Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
2019-12-12gas signed overflow fixesAlan Modra10-52/+51
* config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow. * config/tc-metag.c (parse_dalu): Likewise. * config/tc-tic4x.c (md_pcrel_from): Likewise. * config/tc-tic6x.c (tic6x_output_unwinding): Likewise. * config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer. Don't use register keyword. Avoid signed overflow and remove now unneccesary char masks. Formatting. * config/tc-ia64.c (operand_match): Don't use shifts to sign extend. * config/tc-mep.c (mep_apply_fix): Likewise. * config/tc-pru.c (md_apply_fix): Likewise. * config/tc-riscv.c (load_const): Likewise. * config/tc-nios2.c (md_apply_fix): Likewise. Don't potentially truncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16 calculation.
2019-12-12obj-evax.c tidyAlan Modra1-29/+22
This started out as fixing decode_16, which used a char to index a 256 byte decodings array. When char is signed that could result in an out of bounds array access. The rest of the patch is for consistency and just general cleanup. * config/obj-evax.c (crc32, encode_32, encode_16, decode_16): Remove unnecessary prototypes. (number_of_codings): Delete, use ARRAY_SIZE instead throughout. (codings, decodings): Make arrays of unsigned char. (crc32): Use unsigned variables. Delete unnecessary mask. (encode_32, encode_16): Return unsigned char*, and make static buffer an unsigned char array. (decode_16): Make arg an unsigned char*. Remove useless casts. (shorten_identifier): Use unsigned char crc_chars. (is_truncated_identifier): Make ptr an unsigned char*.
2019-12-11[gas][arm] Add -mwarn-restrict-itAndre Vieira1-0/+7
Add a -m{no-}warn-restrict-it option to control IT related warnings in ARMv8-A and ARMv8-R. This is disabled by default. Committed on behalf of Wilco Dijkstra. gas/ChangeLog: 2019-12-11 Wilco Dijkstra <wdijkstr@arm.com> * config/tc-arm.c (warn_on_restrict_it): Add new variable. (it_fsm_post_encode): Check warn_on_restrict_it. (arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise. * testsuite/gas/arm/armv8-a-bad.d: Likewise. * testsuite/gas/arm/armv8-a-it-bad.d: Likewise. * testsuite/gas/arm/armv8-r-bad.d: Likewise. * testsuite/gas/arm/armv8-r-it-bad.d: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise. * testsuite/gas/arm/udf.d: Likewise.
2019-12-11x86: further refine SSE check (SSE4a, SHA, GFNI)Jan Beulich1-0/+3
In ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went both a little too far and not quite far enough: - GFNI insns also have AVX512 variants, which also shouldn't get diagnosed, - SSE4a insns should get diagnosed just like SSE4.x ones, - SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
2019-12-10[gas][arm] Set context table for '.arch_extension'Andre Vieira1-0/+1
This patch fixes .arch_extension behaviour. Currently, context table for '.arch_extension' is only set while "-march" processing, but it is not set while .arch processing, so following code is rejected .syntax unified .thumb .arch armv8.1-m.main .arch_extension mve.fp unless -march=armv8.1-m.main is given. Committing on behalf of Vladimir Murzin gas/ChangeLog: 2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com> * config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table. * testsuite/gas/arm/mve-arch-ext.s: New. * testsuite/gas/arm/mve-arch-ext.d: New.
2019-12-09x86/Intel: fold "xmmword" with "oword"Jan Beulich1-11/+9
These are full aliases of one another, so there's no real need to use distinct O_md* values for them.
2019-12-09x86/Intel: support "mmword ptr"Jan Beulich1-2/+5
This is an alias of "qword ptr", commonly used with MMX insns. At this occasion also test (alongside the newly supported "mmword") - "zmmword" used as expression, - PADDB with "oword ptr" (aliasing "xmmword ptr").
2019-12-09x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich1-3/+6
Commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic") broke rejecting of these for floating point insns. Fix this by setting the "byte" operand attribute, which will now (again) cause an error. Furthermore the diagnostic for the "far ptr" case in general and for the "near ptr" case in the non-float cases became "invalid instruction suffix" instead of the intended "operand size mismatch". Fix this by also setting the "tbyte" operand attribute (no insn template accepts both byte and tbyte operands).
2019-12-09x86/Intel: drop pointless suffix setting for "tbyte ptr"Jan Beulich1-10/+5
There are extremely few insns accepting "tbyte ptr" operand, so the "tbyte" operand flag checking done by match_operand_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Fold the code with that setting the "byte" operand flag to force an error (no insn at all accepts both "byte ptr" and tbyte ptr" operands, except for AnySize ones where the two (conflicting) recorded types don't matter (operand_size_match() doesn't call match_operand_size() in this case).
2019-12-09x86/Intel: drop pointless suffix setting for "fword ptr"Jan Beulich1-2/+0
No floating point insn accepts an "fword ptr" operand, so the "fword" operand flag checking done by match_mem_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-09x86/Intel: drop pointless special casing of LxSJan Beulich1-6/+1
LDS et al don't accept "word ptr" operands anyway, as per their insn templates. Hence there's no need to special case this here; the check has become dysfunctional anyway by dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich1-3/+1
This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich1-3/+2
SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the latter should not also disable the former. In the course of adding respective tests also do away with the duplication of crypto.d's contents in crypto-directive.d.
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich1-0/+9
Since we accept these without suffix / operand size specifier, we should also do so with one. (The fact that we unilaterally accept these, other than far branches, rather than limiting them to Intel64 mode, will be taken care of later on.) Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>" et al get rejected outside of 64-bit mode. This became broken by dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Furthermore cover lgdt et al in the Intel syntax handling as well, which continued to work after said commit just by coincidence.
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich1-2/+3
While dc2be329b950 ("i386: Only check suffix in instruction mnemonic") has made the assembler accept these in the first place (they were wrongly rejected before), the generated code was still wrong in that it lacked an operand size override. (In 64-bit code, other than in 16- and 32-bit ones, CALL and JMP with memory operands are all entirely unambiguous: No operand size can have two meanings.)
2019-12-04x86: consolidate tracking of MMX register useJan Beulich1-9/+3
Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead include the two special insns (not having register operands) explicitly.
2019-12-04x86: make sure all PUSH/POP honor DefaultSizeJan Beulich1-8/+14
While segment registers are registers, their use doesn't allow sizing of insns without suffix / explicit operand size specifier. Prevent PUSH and POP of segment registers from entering that path, instead allowing them to observe the stackop_size setting just like other PUSH/POP and alike do.
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich1-1/+3
Insns permitting only GPR operands (and hence implicit sizing when there's no suffix) don't ever have their DefaultSize attribute inspected, so it shouldn't be there in the first place. Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be converted to 32-bit operand size in .code16gcc mode. While the same is true for SYSRET, it permitting more than one suffix makes it FLDENV- like, and hence rather than dropping the attribute, for now add it to the exclusion list to avoid it getting an operand size prefix emitted in .code16gcc mode. (This will be dealt with later, perhaps together with FLDENV and friends.)
2019-11-28gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess1-0/+6
The flag controlling the default DWARF CIE version to produce now starts with the value -1. This can be modified with the command line flag as before, but after command line flag processing, in md_after_parse_args targets can, if the global still has the value -1, override this value. This gives a target specific default. If a CIE version is not select either by command line flag, or a target specific default, then some new code in dwarf2_init now select a global default. This remains as version 1 to match previous behaviour. This RISC-V has a target specific default of version provided, this make the return column uleb128, which means we can use all DWARF registers include CSRs. I chose to switch to version 3 rather than version 4 as this is most similar to the global default (version 1). Switching to version 4 adds additional columns to the CIE header. gas/ChangeLog: * as.c (flag_dwarf_cie_version): Change initial value to -1, and update comment. * config/tc-riscv.c (riscv_after_parse_args): Set flag_dwarf_cie_version if it has not already been set. * dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version if needed. * testsuite/gas/riscv/default-cie-version.d: New file. * testsuite/gas/riscv/default-cie-version.s: New file. ld/ChangeLog: * testsuite/ld-elf/eh5.d: Accept version 3 DWARF CIE. Change-Id: Ibbfe8f0979fba480bf0a359978b09d2b3055555e
2019-11-28binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess1-0/+4
This commit gives DWARF register numbers to the RISC-V CSRs inline with the RISC-V ELF specification here: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md The CSRs are defined being numbered from 4096 to 8191. This adds support to the assembler, required in order to reference CSRs in, for example .cfi directives. I have then extended dwarf.c in order to support printing CSR names in the dumped DWARF output. As the CSR name space is quite large and only sparsely populated, I have provided a new function to perform RISC-V DWARF register name lookup which uses a switch statement rather than the table base approach that other architectures use. Any CSR that does not have a known name will return a name based on 'csr%d' with the %d being replaced by the offset of the CSR from 4096. gas/ChangeLog: * config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSR names too. * testsuite/gas/riscv/csr-dw-regnums.d: New file. * testsuite/gas/riscv/csr-dw-regnums.s: New file. binutils/ChangeLog: * dwarf.c (regname_internal_riscv): New function. (init_dwarf_regnames_riscv): Use new function. Change-Id: I3f70bc24fa8b3c75744e6775eeeb87db70c7ecfb
2019-11-28gas/riscv: Remove unneeded structureAndrew Burgess1-7/+1
We build a hash table of all register classes and numbers. The hash key is the register name and the hash value is the class and number encoded into a single value, which is of type 'void *'. When we pull the values out of the hash we cast them to be a pointer to a structure, however, we never access the fields of that structure, we just decode the register class and number from the pointer value itself. This commit removes the structure and treats the encoded class and number as a 'void *' during hash lookup. gas/ChangeLog: * config/tc-riscv.c (struct regname): Delete. (hash_reg_names): Handle value as 'void *'. Change-Id: Ie7d8f46ca3798f56f4af94395279de684f87f9cc
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski1-3/+6
psb CYSNC was not finding that CSYNC was a correct spelling. The problem was upper case version was being put in the wrong hashtable. This fixes the problem by using the correct hashtable. Also adds testcases for the upper case versions. * config/tc-aarch64.c (md_begin): Use correct hash table for uppercase version of hint. * testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase. * testsuite/gas/aarch64/system-2.d: Update. Change-Id: If43f8b85cacd24840d596c3092b0345e5f212766
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu1-16/+17
This patch changes the CRC extension to use the core feature bits instead of the coproc/fpu feature bits. CRC is not an fpu feature and it causes issues with the new fpu reset patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using the '.arch_extension' directive, which sets bits in the coproc bitfield. When a '.fpu' directive is encountered, the CRC feature bit gets removed and there is no way to set it back using '.fpu'. With this patch, CRC will be marked in the feature core bits, which prevents it from getting removed when setting/changing the fpu options. gas/ChangeLog: * config/tc-arm.c (arm_ext_crc): New. (crc_ext_armv8): Remove. (insns): Rename crc_ext_armv8 to arm_ext_crc. (arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC. (armv8a_ext_table, armv8r_ext_table, arm_option_extension_value_table): Redefine the crc extension in terms of ARM_EXT2_CRC. * gas/testsuite/gas/arm/crc-ext.s: New. * gas/testsuite/gas/arm/crc-ext.d: New. include/ChangeLog: * opcode/arm.h (ARM_EXT2_CRC): New extension feature to replace CRC_EXT_ARMV8. (CRC_EXT_ARMV8): Remove and mark bit as unused. (ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of CRC_EXT_ARMV8. opcodes/ChangeLog: * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): Change the coproc CRC conditions to use the extension feature set, second word, base on ARM_EXT2_CRC.
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich2-34/+33
..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich2-21/+35
... instead of an operand one: There's only ever one operand here anyway.
2019-11-14x86: make AnySize an insn attributeJan Beulich1-1/+1
... instead of an operand one. Which operand it applies to can be determined from other operand properties, but as it turns out the only place it is actually used at doesn't even need further qualification.
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu1-44/+65
This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM, VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M Floating-point Extension is enabled. According to the ARMv8.1-M ARM, section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point Extension and/or Armv8.1-M MVE". [1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm instruction for mve_ext. (do_vfp_nsyn_pop): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm instruction for mve_ext. (do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks. (insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop, vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead of fpu_vfp_ext_v1xd. * testsuite/gas/arm/v8_1m-mve.s: New. * testsuite/gas/arm/v8_1m-mve.d: New.
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu1-2/+0
This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode. Previously VMOV and VMVN with cmode 1101 were not allowed. The cmode changes also required updating of the MVE conflict checking. Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV and VMVN, respectively. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with cmode 1101. (is_mve_encoding_conflict): Update cmode conflict checks for MVE_VMVN_IMM. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu1-2/+1
This patch is fixes the '.fpu' behaviour. Currently, using '.fpu' resets the previously selected '.fpu' options (by overwriting them), but does not reset previous FPU options selected by other means (ie. when using '.arch_extension fp' in conjunction with '.fpu <x>', the FPU is not reset). Example: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ ADD (already existing bits, does not reset) vfms.f32 s0, s1, s2 @ OK .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR After the patch this becomes: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ RESET TO VFPV2 vfms.f32 s0, s1, s2 @ ERROR .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR gas/ChangeLog: 2019-11-11 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits. (fpu_any): Remove OBJ_ELF guards. * gas/testsuite/gas/arm/fpu-rst.s: New. * gas/testsuite/gas/arm/fpu-rst.d: New. * gas/testsuite/gas/arm/fpu-rst.l: New.
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-34/+23
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
2019-11-12x86: eliminate ImmExt abuseJan Beulich1-48/+2
Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12x86: introduce operand type "instance"Jan Beulich1-29/+44
Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu1-42/+33
We should check suffix in instruction mnemonic when matching instruction. In Intel syntax, normally we check for memory operand size. But the same mnemonic with 2 different encodings can have the same memory operand size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand size in Intel syntax to distinguish them. When there is no suffix in mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic suffix. gas/ PR gas/25167 * config/tc-i386.c (match_template): Don't check instruction suffix set from operand. * testsuite/gas/i386/code16.d: New file. * testsuite/gas/i386/code16.s: Likewise. * testsuite/gas/i386/i386.exp: Run code16. * testsuite/gas/i386/x86-64-branch-4.l: Updated. opcodes/ PR gas/25167 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. * i386-tbl.h: Regenerated.
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-6/+7
This is to further shrink the operand type representation.
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-43/+45
This is to further shrink the operand type representation.
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-14/+14
This is to further shrink the operand type representation.
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich2-9/+10
This is to further shrink the operand type representation.
2019-11-08x86: introduce operand type "class"Jan Beulich1-41/+59
Many operand types, in particular the various kinds of registers, can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field.
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson1-4/+83
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+7
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson1-0/+49
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat' directive for the AArch64 backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on aarch64-none-elf and aarch64-none-linux-gnu with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format. * testsuite/gas/aarch64/bfloat16-directive-le.d: New test. * testsuite/gas/aarch64/bfloat16-directive-be.d: New test. * testsuite/gas/aarch64/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson1-0/+47
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat16' directive for the Arm backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function (included in the previous patch) in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on arm-none-eabi and arm-none-linux-gnueabihf with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-arm.c (md_atof): Add encoding for bfloat16 * testsuite/gas/arm/bfloat16-directive-le.d: New test. * testsuite/gas/arm/bfloat16-directive-be.d: New test. * testsuite/gas/arm/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson1-29/+54
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions). This patch contains some general refactoring of the atof_ieee function, exposing a function that allows a higher level of control over the format of IEEE-like floating point numbers. This has been done in order to be able to add a directive for assembling floating point literals in the bfloat16 format in the following patches. Committed on behalf of Mihail Ionescu. Tested on arm-none-eabi, arm-none-linux-gnueabihf, aarch64-none-elf and aarch64-none-linux-gnuwith no issues. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * as.h (atof_ieee_detail): Add prototype for atof_ieee_detail function. (atof_ieee): Move some code into the atof_ieee_detail function. (atof_ieee_detail): Add function that provides a higher level of control over generating IEEE-like numbers. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson1-24/+217
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+6
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-0/+1
Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-0/+4
Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
generated by cgit v1.1 at 2024-12-11 23:58:35 +0000