aboutsummaryrefslogtreecommitdiff
path: root/gas/config
AgeCommit message (Collapse)AuthorFilesLines
2021-08-11Fix a typo in the RX asse,bler. The Double-precision floating-point ↵Darius Galis1-1/+1
exception handling control register name is DECNT not DCENT. * config/rx-parse.y (DECNT): Fixed typo. * testsuite/gas/rx/dpopm.sm (DECNT): Fixed typo. * testsuite/gas/rx/dpushm.sm (DECNT): Fixed typo. * testsuite/gas/rx/macros.inc (DECNT): Fixed typo.
2021-08-11Fix an internal error in the CSKY assembler when asked to resolve an ↵Nick Clifton1-1/+2
overlarge constant. PR 28215 * config/tc-csky.c (md_apply_fix): Correctly handle a fixup that involves an overlarge constant.
2021-08-11Add a -mno-dollar-line-separator command line option to the AVR assembler.Matt Jacobson2-3/+16
Some frontends, like the gcc Objective-C frontend, emit symbols with $ characters in them. The AVR target code in gas treats $ as a line separator, so the code doesn?t assemble correctly. Provide a machine-specific option to disable treating $ as a line separator. * config/tc-avr.c (enum options): Add option flag. (struct option): Add option -mno-dollar-line-separator. (md_parse_option): Adjust treatment of $ when option is present. * config/tc-avr.h: Use avr_line_separator_chars.
2021-08-11Fix typo in previous deltaNick Clifton1-2/+2
2021-08-11gas: fold IEEE encoding of -Inf with that of +InfJan Beulich1-42/+3
The respective results differ only by the sign bits - there's no need to have basically identical (partially even arch-specific) logic twice. Simply set the sign bit at the end of encoding the various formats.
2021-08-11gas: support NaN flavorsJan Beulich2-17/+34
Like for infinity, there isn't just a single NaN. The sign bit may be of interest and, going beyond infinity, whether the value is quiet or signalling may be even more relevant to be able to encode. Note that an anomaly with x86'es double extended precision NaN values gets taken care of at the same time: For all other formats a positive value with all mantissa bits set was used, while here a negative value with all non-significant mantissa bits clear was chose for an unknown reason. For m68k, since I don't know their X_PRECISION floating point value layout, a warning gets issued if any of the new flavors was attempted to be encoded that way. However likely it may be that, given that the code lives in a source file supposedly implementing IEEE-compliant formats, the bit patterns of the individual words match x86'es, I didn't want to guess so. And my very, very old paper doc doesn't even mention floating point formats other than single and double.
2021-08-11Arm64: leave .bfloat16 processing to common codeJan Beulich1-49/+1
With x86 support having been implemented by extending atof-ieee.c, avoid unnecessary code duplication in md_atof(). This will then also allow to take advantage of adjustments made there without needing to mirror them here.
2021-08-11Arm32: leave more .bfloat16 processing to common codeJan Beulich1-46/+3
With x86 support having been implemented by extending atof-ieee.c, avoid unnecessary code duplication in md_atof(). This will then also allow to take advantage of adjustments made there without needing to mirror them here.
2021-08-11x86: introduce .bfloat16 directiveJan Beulich2-5/+18
This is to be able to generate data acted upon by AVX512-BF16 and AMX-BF16 insns. While not part of the IEEE standard, the format is sufficiently standardized to warrant handling in config/atof-ieee.c. Arm, where custom handling was implemented, may want to leverage this as well. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86: introduce .hfloat directiveJan Beulich1-1/+2
This is to be able to generate data passed to {,V}CVTPH2PS and acted upon by AVX512-FP16 insns. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86/ELF: fix .ds.x outputJan Beulich1-0/+1
The ELF psABI-s are quite clear here: On 32-bit the underlying data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make s_space() capable of handling 'x' (and 'p') type floating point being other than 12 bytes wide (also adjusting documentation). This requires duplicating the definition of X_PRECISION in the target speciifc header; the compiler would complain if this was out of sync with config/atof-ieee.c. Note that for now padding space doesn't get separated from actual storage, which means that things will work correctly only for little- endian cases, and which also means that by specifying large enough numbers padding space can be set to non-zero. Since the logic is needed for a single little-endian architecture only for now, I'm hoping that this might be acceptable for the time being; otherwise the change will become more intrusive. Note also that this brings the emitted data size of .ds.x vs .tfloat in line for non-ELF targets as well; the issue will be even more obvious when further taking into account a subsequent patch fixing .dc.x/.dcb.x (where output sizes currently differ depending on input format). Extend existing x86 testcases.
2021-08-11x86/ELF: fix .tfloat outputJan Beulich3-2/+29
The ELF psABI-s are quite clear here: On 32-bit the data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make ieee_md_atof() capable of handling such padding, and specify the needed padding for x86 (leaving non-ELF targets alone for now). Split the existing x86 testcase.
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-3/+42
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-08-04gas: correctly output XCOFF tbss symbols with XTY_CM type.Clément Chigot1-1/+2
Global tbss symbols weren't correctly handled and were generating a symbol with XTY_SD instead of XTY_CM as expected. gas/ * config/tc-ppc.c (ppc_frog_symbol): Generate a XTY_CM when a symbol has a storage class of XMC_UL.
2021-08-04gas: always add dummy symbols when creating XCOFF sections.Clément Chigot1-17/+11
Most of the algorithms for XCOFF in tc-ppc.c assume that the csects field of a ppc_xcoff_section isn't NULL. This was already made for most of the sections with the creation of a dummy symbol. This patch simply mades it default when creating a xcoff_section. gas/ * config/tc-ppc.c (ppc_init_xcoff_section): Always create the dummy symbol. (md_begin): Adjust ppc_init_xcoff_section call. (ppc_comm): Likewise. (ppc_change_csect): Likewise.
2021-07-30gas: ensure XCOFF DWARF subsection are initialized to 0Clément Chigot1-1/+1
debug_abbrev doesn't use end_exp to compute its size. However, it must be NULL. Otherwise, ppc_xcoff_end might try to access uninitialized memory. gas/ * config/tc-ppc.c (ppc_dwsect): Use XCNEW instead of XNEW when creating a new subsection.
2021-07-29gas: improve C_BSTAT and C_STSYM symbols handling on XCOFFClément Chigot2-2/+7
A C_BSTAT debug symbol specifies the beginning of a static block. Its n_value is the index of the csect containing static symbols. A C_STSYM debug symbol represents the stabstring of a statically allocated symbol. Its n_value is the offset in the csect pointed by the containing C_BSTAT. These two special n_value were not correctly handled both when generating object files with gas or when reading them with objdump. This patch tries to improve that and, above all, to allow gas-generated object files with such symbols to be accepted by AIX ld. bfd/ * coff-bfd.c (bfd_coff_get_syment): Adjust n_value of symbols having fix_value = 1 in order to be an index and not a memory offset. * coffgen.c (coff_get_symbol_info): Likewize. (coff_print_symbol): Likewize. gas/ * config/tc-ppc.c (ppc_frob_label): Don't change within if already set. (ppc_stabx): Remove workaround changing exp.X_add_symbol's within. * config/tc-ppc.h (struct ppc_tc_sy): Update comments. * symbols.c (resolve_symbol_value): Remove symbol update when final_val is 0 and it's an AIX debug symbol. * testsuite/gas/ppc/aix.exp: Add new tests. * testsuite/gas/ppc/xcoff-stsym-32.d: New test. * testsuite/gas/ppc/xcoff-stsym-64.d: New test. * testsuite/gas/ppc/xcoff-stsym.s: New test.
2021-07-28x86: Simplify check for distinct TMM register operandsH.J. Lu1-15/+10
If any pair of operands in AMX instructions with 3 TMM register operands are the same, the instruction will UD. Don't call register_number to check for distinct TMM register operands since all TMM register operands have the same size. * config/tc-i386.c (check_VecOperands): Remove register_number call when checking for distinct TMM register operands.
2021-07-28PowerPC: ignore sticky options for .machineAlan Modra1-4/+16
PowerPC gas and objdump for a long time have allowed certain -m/-M options that extend a base cpu with extra functional units to be specified before the base cpu. For example, "-maltivec -mpower4" is the same as "-mpower4 -maltivec". See https://sourceware.org/pipermail/binutils/2008-January/054935.html It doesn't make as much sense that .machine keep any of these "sticky" flags when handling a new base cpu. See gcc PR101393. I think that instead .machine ought to override the command line. That's what this patch does. It is still possible to extend cpu functionality with .machine. For example the following can be assembled when selecting a basic -mppc on the command line: .machine power5 .machine altivec frin 1,2 lvsr 3,4,5 Here, ".machine altivec" extends the ".machine power5" so that both the power5 "frin" instruction and the altivec "lvsr" instruction are enabled. Swapping the two ".machine" directives would result in failure to assemble "lvsr". This change will expose some assembly errors, such as the one in glibc/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c, a file compiled with -maltivec but containing asm volatile (".machine push;\n" ".machine \"power5\";\n" "vspltisb %0,0;\n" "vspltisb %1,-1;\n" "vpkuwus %0,%0,%1;\n" "mfvscr %0;\n" "stvx %0,0,%2;\n" ".machine pop;" : "=v" (v0), "=v" (v1) : "r" (vscr_ptr) : "memory"); It's just wrong to choose power5 for a bunch of altivec instructions and in fact all of those .machine directives are unnecessary. * config/tc-ppc.c (ppc_machine): Don't use command line sticky options.
2021-07-26PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti.Andrea Corallo1-0/+3
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (reg_names): Alias 'ra_auth_code' to r12.
2021-07-26PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+14
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_pacg'. (do_t_pacbti_pacg): New function. (insns): Define 'pacg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pacg'.
2021-07-26PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_autg'. (insns): Define 'autg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add autg test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'autg'.
2021-07-26PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+14
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_bxaut'. (do_t_pacbti_nonop): New function. (insns): Define 'bxaut' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'bxaut' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'bxaut'.
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+4
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (pacbti_ext): Define. (BAD_PACBTI): New macro. (armv8_1m_main_ext_table): Add 'pacbti' extension. include/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * opcode/arm.h (ARM_EXT3_PACBTI, ARM_AEXT3_V8_1M_MAIN_PACBTI): New macro.
2021-07-26PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_pac'. (insns): Add 'pac' insn. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add pac tests. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pac'.
2021-07-26PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (insns): Add 'aut.' (T16_32_TAB): Add '_aut'. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add 'aut' tests. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'aut'.
2021-07-26PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+22
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (enum operand_parse_code): Add OP_SP and OP_R12. (parse_operands): Add switch cases for OP_SP and OP_R12. (T16_32_TAB): Add '_pacbti'. (do_t_pacbti): New function. (insns): Add 'pacbti'. * testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.
2021-07-26PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+1
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (insns): Add 'bti' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: New file. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add bti instruction.
2021-07-21as_bad_subtractAlan Modra28-80/+47
Many places report errors of the nature "can't resolve a - b". This provides a utility function to report such errors consistently. I removed the section reporting and quotes around symbol names while I was at it. Compare ifunc-2.s:4: Error: can't resolve `bar1' {.text.1 section} - `foo1' {.text.1 section} with ifunc-2.s:4: Error: can't resolve bar1 - foo1 In many cases the section names don't help the user very much in figuring out what went wrong, and the quotes if present arguably ought to be placed around the entire expression: can't resolve `bar1 - foo1' The patch also tidies some tc_get_reloc functions that leak memory on error paths. * write.h (as_bad_subtract): Declare. * write.c (as_bad_subtract): New function. (fixup_segment): Use as_bad_subtract. * config/tc-arc.c (md_apply_fix): Likewise. * config/tc-avr.c (md_apply_fix, tc_gen_reloc): Likewise. * config/tc-cris.c (md_apply_fix): Likewise. * config/tc-d10v.c (md_apply_fix): Likewise. * config/tc-d30v.c (md_apply_fix): Likewise. * config/tc-ft32.c (md_apply_fix): Likewise. * config/tc-h8300.c (tc_gen_reloc): Likewise. * config/tc-m68hc11.c (md_apply_fix): Likewise. * config/tc-mmix.c (mmix_frob_file): Likewise. * config/tc-mn10200.c (tc_gen_reloc): Likewise. * config/tc-nds32.c (nds32_apply_fix): Likewise. * config/tc-pru.c (md_apply_fix): Likewise. * config/tc-riscv.c (md_apply_fix): Likewise. * config/tc-s12z.c (md_apply_fix): Likewise. * config/tc-s390.c (md_apply_fix): Likewise. * config/tc-tilegx.c (md_apply_fix): Likewise. * config/tc-tilepro.c (md_apply_fix): Likewise. * config/tc-v850.c (md_apply_fix): Likewise. * config/tc-vax.c (md_apply_fix): Likewise. * config/tc-xc16x.c (tc_gen_reloc): Likewise. * config/tc-xgate.c (md_apply_fix): Likewise. * config/tc-xstormy16.c (xstormy16_md_apply_fix): Likewise. * config/tc-xtensa.c (md_apply_fix): Likewise. * config/tc-z80.c (tc_gen_reloc): Likewise. * config/tc-spu.c (md_apply_fix): Likewise. (tc_gen_reloc): Delete dead code. Free memory on error. * config/tc-cr16.c (tc_gen_reloc): Use as_bad_subtract. Free on error. * config/tc-crx.c (tc_gen_reloc): Likewise. * config/tc-ppc.c (tc_gen_reloc): Likewise. * testsuite/gas/i386/ifunc-2.l: Adjust to suit changed error message. * testsuite/gas/mips/lui-2.l: Likewise. * testsuite/gas/tic6x/reloc-bad-1.l: Likewise.
2021-07-14gas: default TC_VALIDATE_FIX_SUB to 0Alan Modra4-2/+16
gas/write.c provides a fallback TC_VALIDATE_FIX_SUB define that can be a problem for some targets, the problem being that a non-zero definition of TC_VALIDATE_FIX_SUB says that some uses of fx_subsy are OK, in effect that the target will handle fx_subsy in md_apply_fix and/or tc_gen_reloc. A lot of targets don't have the necessary md_apply_fix and tc_gen_reloc support. So a safer default is to disallow fx_subsy by default. I've had a good look over target usage of fx_subsy, and think I've caught all the cases where targets need TC_VALIDATE_FIX_SUB. Possible failures would be limited to alpha, microblaze, ppc and s390 (the targets that define UNDEFINED_DIFFERENCE_OK), or targets that generate fixups with BFD_RELOC_GPREL32/16 and use a syntax explicitly showing a difference expression. * write.c (TC_VALIDATE_FIX_SUB): Default to 0. * config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF. * config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF. Do define for XCOFF.
2021-07-14objdump: add DWARF support for AIXClément Chigot1-1/+1
DWARF sections have special names on AIX which need be handled by objdump in order to correctly print them. This patch also adds the correlation in bfd for future uses. bfd/ * libxcoff.h (struct xcoff_dwsect_name): Add DWARF name. * coff-rs6000.c (xcoff_dwsect_names): Update. * coffcode.h (sec_to_styp_flags): Likewise. (coff_new_section_hook): Likewise. binutils/ * dwarf.h (struct dwarf_section): Add XCOFF name. * dwarf.c (struct dwarf_section_display): Update. * objdump.c (load_debug_section): Add XCOFF name handler. (dump_dwarf_section): Likewise. gas/ * config/tc-ppc.c (ppc_change_debug_section): Update to match new name's field.
2021-07-12Add the SEC_ELF_OCTETS flag to debug sections created by the assembler.Tucker1-0/+16
PR 28054 gas * config/obj-elf.c (obj_elf_change_section): Set the SEF_ELF_OCTETS flag on debug sections.
2021-07-07Fix problems translating messages when a percentage sign appears at the end ↵Nick Clifton1-4/+15
of a string. PR 28051 gas * config/tc-i386.c (offset_in_range): Reformat error messages in order to fix problems when translating. (md_assemble): Likewise. * messages.c (as_internal_value_out_of_range): Likewise. * read.c (emit_expr_with_reloc): Likewise. * testsuite/gas/all/overflow.l Change expected output format. * po/gas.pot: Regenerate. bfd * coff-rs6000.c (xcoff_reloc_type_tls): Reformat error messages in order to fix problems when translating. * cofflink.c (_bfd_coff_write_global_sym): Likewise. * elfnn-aarch64.c (_bfd_aarch64_erratum_843419_branch_to_stub): Likewise. * po/bfd.pot: Regenerate.
2021-07-06PR 28053: Fix spelling mistakes: usupported -> unsupported and relocatation ↵Yuri Chornoivan1-1/+1
-> relocation.
2021-07-02Re: Fix minor NDS32 renaming snafuAlan Modra1-2/+1
Some extern declarations differ in constnes to their definitions too. Let's make sure this sort of thing doesn't happen again, but putting the externs in a header where they belong. gas/ * config/tc-nds32.c (nds32_keyword_gpr): Don't declare. (md_begin): Constify k. opcodes/ * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return. (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg. (nds32_field_table, nds32_opcode_table, nds32_keyword_table), (nds32_opcodes, nds32_operand_fields, nds32_keywords), (nds32_keyword_gpr): Move declarations to.. * nds32-asm.h: ..here, constifying to match definitions.
2021-07-02Fix minor NDS32 renaming snafu.Nick Clifton1-2/+2
* config/tc-nds32.c: Change all references of keyword_gpr to nds32_keyword_gpr.
2021-07-01opcodes: constify & scope microblaze opcodesMike Frysinger1-2/+2
This is exporting the variable "opcodes" as a large writable blob. This is not a namespace friendly name, so add a "microblaze" prefix, and then sprinkle const over its definition & use.
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger1-3/+3
This table is huge (~350k), so stop putting it into writable .data since it's only const data.
2021-06-24gas: update csect alignment for PPC prefixed instructions on XCOFFClément Chigot1-0/+5
Power10 prefixed instructions must not cross 64-byte boundaries. This is already handled. However, on XCOFF, the csect must be updated to match the new alignment. * config/tc-ppc.c (md_assemble): Update ppc_current_csect alignment when finding prefixed instructions.
2021-06-22picojava assembler and disassembler fixesAlan Modra1-4/+1
Commit 54758c3e398d made changes to the picojava support based on https://sourceware.org/pipermail/binutils/2005-November/045136.html An update from picojava to picojava II, I think. Unfortunately the patch neglected any changes to the gas testsuite, resulting in "FAIL: pj" since that date. This patch makes a few relatively simple changes to cure the regression. gas/ * config/tc-pj.c (md_apply_fix): Apply PJ_CODE_REL32 relocs. * testsuite/gas/pj/ops.s: Update jsr, ret, getstatic, putstatic, getfield, putfield, invokevirtual, invokespecial, invokestatic, invokeinterface, goto_w, jsr_w assembly. Delete version 1 picojava opcodes. * testsuite/gas/pj/ops.d: Match expected output. opcodes/ * pj-dis.c (print_insn_pj): Don't print trailing tab. Do print separator for pcrel insns.
2021-06-19ubsan errors when 32-bit bfdAlan Modra1-3/+3
A shift count exceeding the size of the value is undefined behaviour, and so is negating a signed LONG_MIN. * config/tc-z80.c (signed_overflow, unsigned_overflow): Avoid UB.
2021-06-17Fix an assertion failure in the AArch64 assembler triggered by incorrect ↵Nick Clifton1-3/+12
instruction syntax. PR 27904 * config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type): Generate a syntax error message if the reloc qualifier does not match the instruction's size.
2021-06-17gas: handle csect in bss section for XCOFFClément Chigot1-3/+7
Latest gcc versions are now generating csects instead of .lcomm for bss symbols. Some adjustements are needed in order to handle them. * config/tc-ppc.c (md_begin): Create bss section with dummy symbol. (ppc_frob_symbol): Output XTY_CM for bss csects. (ppc_fix_adjustable): Adjust condition to avoid bss csects.
2021-06-17gas: ensure sections contents is zero for BFD_RELOC_PPC*_TLSM on XCOFF.Clément Chigot1-5/+12
AIX ld expects the section contents for relocations BFD_RELOC_PPC_TLSM or BFD_RELOC_PPC64_TLSM to be zero. Actually, it seems to be the case for all the TLS relocations generated by AIX assembly but only these two are mandatory. * config/tc-ppc.c (md_apply_fix): Adjust addend to nullify section contents for BFD_RELOC_PPC_TLSM or BFD_RELOC_PPC64_TLSM. * testsuite/gas/ppc/xcoff-tlsm-32.d: New test. * testsuite/gas/ppc/xcoff-tlsm-64.d: New test. * testsuite/gas/ppc/xcoff-tlsm.s: New test. * testsuite/gas/ppc/aix.exp: Run new tests.
2021-06-15x86: bring "gas --help" output for --32 etc in sync with realityJan Beulich1-3/+7
The testsuite uses the output to determine whether BFD64 is in effect. --x32 is supported for ELF only; don't advertise it for PE/COFF. --64 is also supported for Mach-O; advertise it. Adjust the testsuite's BFD64 check accordingly. Also replace "code" by "object", since it's the object format that the options primarily control. It's also _initial_ code bitness, but this can be changed by directives.
2021-06-15x86: simplify .dispNN settingJan Beulich1-51/+17
First of all eliminate the disp{16,32,32s} static variables, which are used solely for setting a temporary variable in build_modrm_byte(). The effect there can be had without use of such a temporary and without operand_type_or(), by just setting the single bit each that needs setting. Then use operand_type_and_not(..., anydisp) when all dispNN bits want clearing together.
2021-06-15x86: slightly simplify offset_in_range()Jan Beulich1-2/+2
Applying a mask with all bits set (or its inverse, with hence all bits clear) won't alter the result (or won't trigger the warning). Re-arrange the code to eliminate two more of the somewhat odd (2 << width_minus_1) constructs.
2021-06-15x86: harmonize disp with imm handlingJan Beulich1-23/+28
Certain disp values may trigger "... shortened to ..." warnings when equivalent imm ones don't. In some of the cases there are also differences (for non-64-bit code) between BFD64 and !BFD64 builds. The resulting encodings (i.e. use [or not] of the shorter disp8 / imm8 forms) are also different in some cases. Make this handling consistent. Note that using equivalent 16-bit mode displacements / immediates continues to expose entirely different behavior (see the disp-imm-16 testcase added by an earlier patch). This may want to be the subject of further changes, but it'll then quickly become obvious that e.g. keying use of extend_to_32bit_address() to non-64-bit mode isn't appropriate either: Once we allow wrapping operands, we would better do so consistently, in which case all of this would need to become dependent upon address or operand size instead of mode.
2021-06-15x86: make offset_in_range()'s warning contents useful (again)Jan Beulich1-6/+2
In case there is something which gets shortened (perhaps only on a BFD64 build targeting a 32-bit binary), seeing the full original value is often helpful to understand what's actually going wrong. Of course for non-64-bit binaries we better wouldn't be seeing such warnings at all, as they're often indicative of a behavioral difference between BFD64 and !BFD64 builds. Prior to "gas: drop sprint_value()", which introduced the use of bfd_sprintf_vma(), the output had other shortcomings.
2021-06-15x86: off-by-1 in offset_in_range()Jan Beulich1-1/+1
Just like e.g. 0x10000 triggers a warning for size 2, -0x10000 ought to as well. Note that some of the encodings produced aren't ones one would expect, and hence the generated code is not being checked for in the new testcases.
generated by cgit v1.1 at 2025-01-02 10:30:57 +0000