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2016-07-19sparc: make a field type bfd_reloc_code_real_typeTrevor Saunders1-1/+1
gas/ChangeLog: 2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sparc.c (struct pop_entry): Make the type of reloc bfd_reloc_code_real_type.
2016-07-19sparc: remove a sentinalTrevor Saunders1-16/+11
gas/ChangeLog: 2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sparc.c (pop_table): Remove sentinel. (NUM_PERC_ENTRIES): Use ARRAY_SIZE on pop_table. (md_begin): Adjust.
2016-07-19tc-z8k.c: make some argument types bfd_reloc_code_real_typeTrevor Saunders1-3/+8
gas/ChangeLog: 2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-z8k.c (newfix): Make type of type argument bfd_reloc_code_real_type. (apply_fix): Likewise.
2016-07-16Don't include libbfd.h outside of bfd, part 2Alan Modra8-8/+0
Make bfd_default_set_arch_mach available to a bunch of gas backend files. bfd/ * archures.c (bfd_default_set_arch_mach): Make available in bfd.h. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-epiphany.c: Don't include libbfd.h. * config/tc-frv.c: Likewise. * config/tc-ip2k.c: Likewise. * config/tc-iq2000.c: Likewise. * config/tc-m32c.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mt.c: Likewise. * config/tc-nios2.c: Likewise.
2016-07-16Don't include libbfd.h outside of bfd, part 1Alan Modra5-8/+3
Make BFD_ALIGN available to objcopy. Fix assertions. Don't use bfd_log2 in ppc32elf.em or bfd_malloc in xtensaelf.em and bucomm.c. bfd/ * libbfd-in.h (BFD_ALIGN): Move to.. * bfd-in.h: ..here. * elf32-ppc.h (struct ppc_elf_params): Add pagesize. * elf32-ppc.c (default_params): Adjust init. (ppc_elf_link_params): Set pagesize_p2. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. binutils/ * ar.c: Don't include libbfd.h. * objcopy.c: Likewise. * bucomm.c (bfd_get_archive_filename): Use xmalloc rather than bfd_malloc. gas/ * config/bfin-parse.y: Don't include libbfd.h. * config/tc-bfin.c: Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-metag.c: Likewise. (create_dspreg_htabs, create_scond_htab): Use gas_assert not BFD_ASSERT. * Makefile.am: Update dependencies. * Makefile.in: Regenerate. ld/ * ldlang.c: Don't include libbfd.h. * emultempl/nds32elf.em: Likewise. * emultempl/ppc64elf.em: Likewise. * emultempl/ppc32elf.em: Likewise. (pagesize): Delete. (params): Update init. (ppc_after_open_output): Use params.pagesize. Don't call bfd_log2. (PARSE_AND_LIST_ARGS_CASES): Use params.pagesize. * emultempl/sh64elf.em: Don't include libbfd.h. (after_allocation): Use ASSERT, not BFD_ASSERT. * emultempl/xtensaelf.em: Don't include libbfd.h. (replace_insn_sec_with_prop_sec): Use xmalloc, not bfd_malloc. * Makefile.am: Update dependencies. * Makefile.in: Regenerate.
2016-07-14MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbolsMaciej W. Rozycki2-0/+19
Don't convert PC-relative REL relocations against absolute symbols to section-relative references and retain the original symbol reference instead. Offsets into the absolute section may overflow the limited range of their in-place addend field, causing an assembly error, e.g.: $ cat test.s .text .globl foo .ent foo foo: b bar .end foo .set bar, 0x12345678 $ as -EB -32 -o test.o test.s test.s: Assembler messages: test.s:3: Error: relocation overflow $ With the original reference retained the source can now be assembled and linked successfully: $ as -EB -32 -o test.o test.s $ objdump -dr test.o test.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo>: 0: 1000ffff b 0 <foo> 0: R_MIPS_PC16 bar 4: 00000000 nop ... $ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o $ objdump -dr test test: file format elf32-tradbigmips Disassembly of section .text: 12340000 <foo>: 12340000: 1000159d b 12345678 <bar> 12340004: 00000000 nop ... $ For simplicity always retain the original symbol reference, even if it would indeed fit. Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch relocations against absolute symbols to be converted on RELA targets to section-relative references. This is an intended effect of this change. Absolute symbols carry no ISA annotation in their `st_other' field and their value is not going to change with linker relaxation, so it is safe to discard the original reference and keep the calculated final symbol value only in the relocation's addend. Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring absolute symbols can be safely converted even on REL targets, as there the in-place addend of these relocations covers the entire 32-bit address space so it can hold the calculated final symbol value, and likewise the value referred won't be affected by any linker relaxation. Add a set of suitable test cases and enable REL linker tests which now work and were previously used as dump patterns for RELA tests only. gas/ * config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro. (mips_force_relocation_abs): New prototype. * config/tc-mips.c (mips_force_relocation_abs): New function. * testsuite/gas/mips/branch-absolute.d: Adjust dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/gas/mips/branch-absolute-addend.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend.d: New test. * testsuite/gas/mips/micromips-branch-absolute-addend.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips-elf.exp: Run `branch-absolute-addend', `mips16-branch-absolute', `mips16-branch-absolute-addend' and `micromips-branch-absolute-addend'.
2016-07-14MIPS/GAS: Keep the ISA bit in the addend of branch relocationsMaciej W. Rozycki1-9/+1
Correct a problem with the ISA bit being stripped from the addend of compressed branch relocations, affecting RELA targets. It has been there since microMIPS support has been added, with: commit df58fc944dbc6d5efd8d3826241b64b6af22f447 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Sun Jul 24 14:20:15 2011 +0000 <https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS: microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 relocations originally affected, and the R_MIPS16_PC16_S1 relocation recently added with commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually triggering a linker error, due to its heightened processing strictness level: $ cat test.s .text .set mips16 foo: b bar .set bar, 0x1235 .align 4, 0 $ as -EB -n32 -o test.o test.s $ objdump -dr test.o test.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: f000 1000 b 4 <foo+0x4> 0: R_MIPS16_PC16_S1 *ABS*+0x1230 ... $ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o test.o: In function `foo': (.text+0x0): Branch to a non-instruction-aligned address $ This is because the ISA bit of the branch target does not match the ISA bit of the referring branch, hardwired to 1 of course. Retain the ISA bit then, so that the linker knows this is really MIPS16 code referred: $ objdump -dr fixed.o fixed.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: f000 1000 b 4 <foo+0x4> 0: R_MIPS16_PC16_S1 *ABS*+0x1231 ... $ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o $ Add a set of MIPS16 tests to cover the relevant cases, excluding linker tests though which would overflow the in-place addend on REL targets and use them as dump patterns for RELA targets only. gas/ * config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1> <BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1> <BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the addend calculated. * testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit in `bar', export `foo'. * testsuite/gas/mips/mips16-branch-absolute.d: Adjust accordingly. * testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: Likewise. ld/ * testsuite/ld-mips-elf/mips16-branch-absolute.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except from `mips16-branch-absolute' and `mips16-branch-absolute-addend', referred indirectly only.
2016-07-11TLS: DTPOFF can accept offsets, stored into addendum. Remove the need of baseClaudiu Zissulescu1-23/+2
gas/ChangeLog: 2016-07-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff. (tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum as it is no longer needed. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-07-08MIPS/GAS: Remove extraneous `install_insn' call from `append_insn'Maciej W. Rozycki1-1/+0
Complement: commit 1e91584932efd70020c8c98037d0cb93a0552a20 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Wed Mar 9 09:17:02 2005 +0000 <https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), and remove a call to `install_insn' from `append_insn', which as from that change has become redundant. This is because such a call, to place an instruction's bit pattern in output, is already made from `move_insn', called from `add_relaxed_insn' or `add_fixed_insn' as appropriate, either of which now always is and has to be made from `append_insn' before the repeated call to `install_insn' is made. Previously the place where this second invocation is made was the only one where the output stream was updated, although the update was made inline rather than with a function call. Remove the repeated call then, to reclaim some performance. gas/ * config/tc-mips.c (append_insn): Remove extraneous `install_insn' call.
2016-07-05x86: fix register check in check_qword_reg()Jan Beulich1-1/+1
A missing 'r' (or wrong 'e') register prefix needs to be complained about if the template allows for a 64-bit register, not a 32-bit one. I assume this was a copy-and-paste type of mistake (from check_long_reg()).
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy1-17/+67
Feature flag handling was not perfect, +nofp16 disabled fp instructions too. New feature flag macros were added to check features with multiple bits set (matters for FP_F16 and SIMD_F16 opcode feature tests). The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should use one of the AARCH64_CPU_HAS_* macros. AARCH64_CPU_HAS_FEATURE now checks all feature bits. The aarch64_features table now contains the dependencies as a separate field (so when the feature is enabled all dependencies are enabled and when it is disabled everything that depends on it is disabled). Note that armv8-a+foo+nofoo is not equivalent to armv8-a if +foo turns on dependent features that nofoo does not turn off. gas/ * config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add require field. (aarch64_features): Initialize require fields. (aarch64_parse_features): Handle dependencies. (aarch64_feature_enable_set, aarch64_feature_disable_set): New. (md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES. * testsuite/gas/aarch64/illegal-nofp16.s: New. * testsuite/gas/aarch64/illegal-nofp16.l: New. * testsuite/gas/aarch64/illegal-nofp16.d: New. include/ * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New. (AARCH64_CPU_HAS_ANY_FEATURES): New. (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES. (AARCH64_OPCODE_HAS_FEATURE): Remove.
2016-07-01x86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich1-0/+17
Additionally warn about scaling factors other than 1 for the latter two, as those get ignored by the hardware.
2016-07-01x86/MPX: fix address size handlingJan Beulich1-4/+9
While address overrides are ignored in 64-bit mode (and hence shouldn't really result in an error, but upon v1 converting this to a warning I was told otherwise), trying to use 16-bit addressing is documented to result in #UD, and hence the assembler should reject the attempt. (The added test case at once also checks that bndc{l,n,u} won't accept 16-bit register operands.)
2016-07-01x86/Intel: don't accept bogus instructionsJan Beulich1-5/+27
... due to their last byte looking like a suffix, when after its stripping a matching instruction can be found. Since memory operand size specifiers in Intel mode get converted into suffix representation internally, we need to keep track of the actual mnemonic suffix which may have got trimmed off, and check its validity while looking for a matching template. I tripper over this quite some time again after support for AMD's SSE5 instructions got removed, as at that point some of the SSE5 mnemonics, other than expected, didn't fail to assemble. But the problem affects many more instructions, namely (almost) all MMX, SSE, and AVX ones as it looks. I don't think it makes sense to add a testcase covering all of them, nor do I think it makes sense to pick out some random examples for a new test case.
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich2-1/+57
The dual purpose mnemonic (string move vs scalar double move) breaks the assumption that the isstring flag would be set on both the first and last entry in the current set of templates, which results in bogus or missing diagnostics for the string move variant of the mnemonic. Short of mostly rewriting i386_index_check() and its interaction with the rest of the code, simply shrink the template set to just string instructions when encountering the second memory operand, and run i386_index_check() a second time for the first memory operand after that reduction.
2016-06-30MIPS/GAS: Fix a comment typo in `get_append_method'Maciej W. Rozycki1-1/+1
gas/ * config/tc-mips.c (get_append_method): Fix a comment typo.
2016-06-30MIPS16/GAS: Fix delay slot filling across fragsMatthew Fortune1-7/+2
Fix an assertion failure like: test.s: Assembler messages: test.s:3: Internal error! Assertion failure in append_insn at .../gas/config/tc-mips.c:7523. Please report this bug. triggered by assembling MIPS16 code like: hello: addiu $4, $4, 4 jr $31 with the generation of a listing file enabled, e.g.: $ as -mips16 -O2 -aln=test.lst The cause of the problem is the lack of support for moving instructions across frags in MIPS16 jump swapping, which triggers more easily with listing enabled as in that case every instruction gets placed in its own frag. It would trigger even with listing disabled though if the instruction to swap a MIPS16 jump with was unfortunately enough placed as last in a frag that became full. This scenario is already handled correctly with branch swapping in regular MIPS and microMIPS code, so reuse it for MIPS16 code as well, and now that all MIPS16 handling has become the same as the regular MIPS and microMIPS cases remove MIPS16 special casing altogether. This effectively complements: commit 464ab0e55ade01d2bb0b4fa45c429af7a2f85a26 Author: Maciej W. Rozycki <macro@linux-mips.org> Date: Mon Aug 6 20:33:00 2012 +0000 <https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS: Correct microMIPS branch swapping assertion") for the MIPS16 case. The assertion itself was introduced with: commit 1e91584932efd70020c8c98037d0cb93a0552a20 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Wed Mar 9 09:17:02 2005 +0000 <https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction merely noted our existing lack of support for MIPS16 jump swapping across frags. gas/ * config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special case MIPS16 handling. * testsuite/gas/mips/branch-swap-3.d: New test. * testsuite/gas/mips/branch-swap-4.d: New test. * testsuite/gas/mips/mips16@branch-swap-3.d: New test. * testsuite/gas/mips/mips16@branch-swap-4.d: New test. * testsuite/gas/mips/micromips@branch-swap-3.d: New test. * testsuite/gas/mips/micromips@branch-swap-4.d: New test. * testsuite/gas/mips/branch-swap-3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-30MIPS/GAS: Simplify non-MIPS16 branch swapping sequenceMaciej W. Rozycki1-3/+4
Simplify non-MIPS16 branch swapping by copying the MIPS16 variant, which sets the new position for the current instruction first and reduces the calculation of the new position of the previous instruction. Also refer to previous instruction's frag and position via `delay' for consistency. Reintroduce an explanatory comment, updated, previously removed with: commit 1e91584932efd70020c8c98037d0cb93a0552a20 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Wed Mar 9 09:17:02 2005 +0000 <https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework MIPS nop-insertion code, add -mfix-vr4130 [5/11]"). gas/ * config/tc-mips.c (append_insn): Simplify non-MIPS16 branch swapping sequence.
2016-06-30Allow ARC target to be configured with --with-cpu=<cpu-name>.Andrew Burgess1-2/+7
gas * config.in (TARGET_WITH_CPU): Undefine. * configure.ac: Add --with-cpu support, and define in config.h. * configure: Regenerate. * config/tc-arc.c: Use TARGET_WITH_CPU to select default CPU. * NEWS: Mention new configure option.
2016-06-29Correct fix for typoNick Clifton1-1/+1
2016-06-29Fix typoNick Clifton1-1/+1
2016-06-28MIPS16: Add R_MIPS16_PC16_S1 branch relocation supportMaciej W. Rozycki1-7/+47
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1' and the usual MIPS16 bit shuffling applies to relocated field handling, as per the encoding of the branch target in the extended form of the MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions. include/ * elf/mips.h (R_MIPS16_PC16_S1): New relocation. bfd/ * elf32-mips.c (elf_mips16_howto_table_rel): Add R_MIPS16_PC16_S1. (mips16_reloc_map): Likewise. * elf64-mips.c (mips16_elf64_howto_table_rel): Likewise. (mips16_elf64_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfn32-mips.c (elf_mips16_howto_table_rel): Likewise. (elf_mips16_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfxx-mips.c (mips16_branch_reloc_p): New function. (mips16_reloc_p): Handle R_MIPS16_PC16_S1. (b_reloc_p): Likewise. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_check_relocs): Likewise. * reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-mips.c (mips16_reloc_p): Handle BFD_RELOC_MIPS16_16_PCREL_S1. (b_reloc_p): Likewise. (limited_pcrel_reloc_p): Likewise. (md_pcrel_from): Likewise. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise. (md_convert_frag): Likewise. (mips_fix_adjustable): Update comment. * testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file. * testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-3.l: Remove file. * testsuite/gas/mips/mips16-branch-absolute.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.s: Add padding. * testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid implicit instruction padding, avoid MIPS16 JR->JRC conversion. * testsuite/gas/mips/branch-weak-6.d: New test. * testsuite/gas/mips/branch-weak-7.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-branch-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-3.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test. * testsuite/ld-mips-elf/mips16-branch.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-27Make the kernel dwarf stack unwinder work for ARC targets.Vineet Gupta1-1/+1
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use cfi_add_CFA_def_cfa to generate default CFA with offset * testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
2016-06-27dlx: move prototype of dlx_set_skip_hi16 to elf/dlx.hTrevor Saunders2-1/+2
bfd/ChangeLog: 2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf32-dlx.h: New file. * elf32-dlx.c: Adjust. gas/ChangeLog: 2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-dlx.c: Include bfd/elf32-dlx.h. * config/tc-dlx.h: Remove prototype of dlx_set_skip_hi16.
2016-06-27xtensa: remove a sentinalTrevor Saunders1-15/+14
gas/ChangeLog: 2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c (xtensa_elf_suffix): Use ARRAY_SIZE instead of a sentinal element. (map_suffix_reloc_to_operator): Likewise. (map_operator_to_reloc): Likewise.
2016-06-27nds32: remove a sentinalTrevor Saunders1-14/+5
gas/ChangeLog: 2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-nds32.c (md_begin): Use ARRAY_SIZE instead of a sentinal element in relax_table.
2016-06-25aarch64: make the type of reg_entry::type aarch64_reg_typeTrevor Saunders1-10/+10
gas/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-aarch64.c: Make the type of reg_entry::type aarch_reg_type.
2016-06-25remove a few sentinalsTrevor Saunders4-30/+26
gas/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-bfin.c (bfin_cpus): Remove sentinal. (md_parse_option): Adjust. * config/tc-aarch64.c (aarch64_parse_abi): Replace use of a sentinal with iteration from 0 to ARRAY_SIZE. * config/tc-mcore.c (md_begin): Likewise. * config/tc-visium.c (visium_parse_arch): Likewise. opcodes/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * mcore-opc.h: Remove sentinal. * mcore-dis.c (print_insn_mcore): Adjust.
2016-06-25simplify tic54x_set_default_include ()Trevor Saunders1-14/+9
its only called with an argument of 0, so we might as well remove the code supporting other values. gas/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-tic54x.c (tic54x_set_default_include): remove argument and simplify accordingly. (tic54x_include): Adjust. (tic54x_mlib): Likewise.
2016-06-25xtensa: prototype xtensa_make_property_section in elf/xtensa.hTrevor Saunders1-4/+0
There's no reason to have multiple prototypes for the same function. include/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf/xtensa.h (xtensa_make_property_section): New prototype. gas/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c (xtensa_make_property_section): Remove prototype. bfd/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf32-xtensa.c (xtensa_make_property_section): Remove prototype.
2016-06-25MIPS16/GAS: Restore unsupported relocation diagnosticsMaciej W. Rozycki1-53/+48
Correct a MIPS16 relocation handling regression in GAS introduced with: commit 177b4a6ad0047c8995fbc55016bc4f4b68d53b4a Author: Alexandre Oliva <aoliva@redhat.com> Date: Mon Mar 18 18:56:18 2002 +0000 discussed at <https://sourceware.org/ml/binutils/2002-03/msg00345.html>, which removed a preparatory call to `mips16_extended_frag' previously made from `md_estimate_size_before_relax'. As a result the function is never called with its `sec' parameter non-NULL and consequently all the unsupported relocation checks within are dead and never trigger, causing any unhandled relocations to silently resolve to 0. Unfortunately there was no sufficient test suite coverage back then to catch this. Remove all dead code then, and all the associated comments. Update the remaining call to `mips16_extended_frag' from `mips_relax_frag' to pass the relocation section as the `sec' parameter and use it to mark frags which require an external relocation, as extended. Finally handle any outstanding MIPS16 relocations in `md_convert_frag' and report an error since we don't support any except with percent operators. gas/ * config/tc-mips.c (append_insn): Use any `O_symbol' expression unchanged with relaxed MIPS16 instructions. (mips16_extended_frag): Adjust accordingly. Return 1 right away if a relocation will be required for the symbol requested. Remove dead first relaxation pass code. (mips_relax_frag): Pass `sec' down to `mips16_extended_frag'. (md_convert_frag): Adjust symbol value calculation. Raise an error if a relocation is required for the symbol requested. * testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns, add error output. * testsuite/gas/mips/mips16@relax-swap3.l: New error output. * testsuite/gas/mips/mips16-pcrel-relax-0.d: New test. * testsuite/gas/mips/mips16-pcrel-relax-1.d: New test. * testsuite/gas/mips/mips16-pcrel-relax-2.d: New test. * testsuite/gas/mips/mips16-pcrel-relax-3.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-0.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-1.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-2.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-3.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute.d: New test. * testsuite/gas/mips/mips16-branch-reloc-0.d: New test. * testsuite/gas/mips/mips16-branch-reloc-1.d: New test. * testsuite/gas/mips/mips16-branch-reloc-2.d: New test. * testsuite/gas/mips/mips16-branch-reloc-3.d: New test. * testsuite/gas/mips/mips16-branch-addend-0.d: New test. * testsuite/gas/mips/mips16-branch-addend-1.d: New test. * testsuite/gas/mips/mips16-branch-addend-2.d: New test. * testsuite/gas/mips/mips16-branch-addend-3.d: New test. * testsuite/gas/mips/mips16-branch-absolute.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-0.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-1.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-2.d: New test. * testsuite/gas/mips/mips16-absolute-reloc-3.d: New test. * testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output. * testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output. * testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output. * testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output. * testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output. * testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output. * testsuite/gas/mips/mips16-pcrel-absolute.l: New error output. * testsuite/gas/mips/mips16-branch-reloc-2.l: New error output. * testsuite/gas/mips/mips16-branch-reloc-3.l: New error output. * testsuite/gas/mips/mips16-branch-addend-2.l: New error output. * testsuite/gas/mips/mips16-branch-addend-3.l: New error output. * testsuite/gas/mips/mips16-branch-absolute.l: New error output. * testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output. * testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output. * testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source. * testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source. * testsuite/gas/mips/mips16-pcrel-absolute.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-0.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-1.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-2.s: New test source. * testsuite/gas/mips/mips16-branch-reloc-3.s: New test source. * testsuite/gas/mips/mips16-branch-addend-0.s: New test source. * testsuite/gas/mips/mips16-branch-addend-1.s: New test source. * testsuite/gas/mips/mips16-branch-addend-2.s: New test source. * testsuite/gas/mips/mips16-branch-addend-3.s: New test source. * testsuite/gas/mips/mips16-branch-absolute.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source. * testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-23MIPS/GAS: Keep the original microMIPS symbol reference in branch relocsMaciej W. Rozycki1-5/+20
Keep original microMIPS symbols in references from branch relocations so that the ISA bit is retained and can be verified for validity in static link. No need to update WRT MIPS16 symbols because we keep them all anyway for other reasons. gas/ * config/tc-mips.c (b_reloc_p): New function. (mips_fix_adjustable): Also keep the original microMIPS symbol referred from branch relocations. * testsuite/gas/mips/branch-local-1.d: New test. * testsuite/gas/mips/branch-local-n32-1.d: New test. * testsuite/gas/mips/branch-local-n64-1.d: New test. * testsuite/gas/mips/micromips@branch-misc-4-64.d: Update relocations. * testsuite/gas/mips/branch-local-1.s: New test source. * testsuite/gas/mips/mips.exp: Run the new cases.
2016-06-23[ARC] Misc minor edits/fixesGraham Markall1-36/+37
The code supporting -mspfp, -mdpfp, and -mfpuda options are in sections of code that are commented as being for backward compatibility only, and having no effect. However, they do have an effect, enabling the SPX, DPX, and DPA instruction subclasses respectively. This commit moves the code supporting these options away from the comments indicating that they are dummy options, and also fixes a small issue where -mnps400 had the additional effect of enabling SPX instructions. A couple of other minor edits (that make no functional change) are also included. gas/ChangeLog: * config/tc-arc.c (options, md_longopts, md_parse_option): Move -mspfp, -mdpfp and -mfpuda out of the sections for dummy options. Correct erroneous enabling of SPFP instructions when using -mnps400. include/ChangeLog: * opcode/arc.h: Make insn_class_t alphabetical again. opcodes/ChangeLog: * arc-opc.c: Correct description of availability of NPS400 features.
2016-06-22xtensa: include elf/xtensa.h in tc-xtensa.cTrevor Saunders1-4/+1
There's no reason to define these macros twice. gas/ChangeLog: 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c: Include elf/xtensa.h.
2016-06-21MIPS/GAS: Handle resolved R6 PC-relative relocationsMaciej W. Rozycki1-8/+54
Complement commit 7361da2c952e ("Add support for MIPS R6.") and fix internal errors like: foo.s: Assembler messages: foo.s: Internal error! Assertion failure in md_apply_fix at .../gas/config/tc-mips.c:15028. Please report this bug. triggered by resolved R6 PC-relative relocations in sources containing R6 code fragments wrapped into ISA override blocks embedded within code otherwise assembled for an older ISA. gas/ * config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL> <BFD_RELOC_LO16_PCREL>: New switch cases. (md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>: Move switch cases along `BFD_RELOC_MIPS_JMP'. <BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2> <BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle the resolved case. * testsuite/gas/mips/pcrel-reloc-4.d: New test. * testsuite/gas/mips/pcrel-reloc-4-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-5.d: New test. * testsuite/gas/mips/pcrel-reloc-5-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-6.d: New test. * testsuite/gas/mips/pcrel-reloc-6.l: New list test. * testsuite/gas/mips/pcrel-reloc-4.s: New test source. * testsuite/gas/mips/pcrel-reloc-6.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21MIPS/GAS: Fix null pointer dereferences in R6 PC-relative relocation checksMaciej W. Rozycki1-2/+2
Avoid segmentation faults in alignment checks made in `md_apply_fix' for BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2 relocations caused by dereferencing `fixP->fx_addsy' which will be null if the relocation processed has been fully resolved. gas/ * config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS_18_PCREL_S3> <BFD_RELOC_MIPS_19_PCREL_S2>: Avoid null pointer dereferences via `fixP->fx_addsy'.
2016-06-21MIPS/GAS: Correct BFD_RELOC_MIPS_18_PCREL_S3 calculationMaciej W. Rozycki1-1/+14
The PC-relative R_MIPS_PC18_S3 relocation and consequently its BFD internal BFD_RELOC_MIPS_18_PCREL_S3 representation is calculated from the address of the aligned doubleword containing the location being relocated: (sign_extend(A) + S - (P & ~0x7)) >> 3 rather than the address of the location itself. Reflect this in calculations made by GAS so that the relocated field is set correctly if resolved by GAS, such as with local symbols in the same section which do not require relocations to be propagated to the link stage. gas/ * config/tc-mips.c (md_pcrel_from) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate relocation from the containing aligned doubleword. (tc_gen_reloc) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate the addend from the containing aligned doubleword.
2016-06-21MIPS/GAS: Use the module level ISA setting for R6 relaxationMaciej W. Rozycki1-2/+2
Use the module level ISA setting rather than the last ISA selected with a `.set' directive in the source file in determination as to whether to keep PC-relative relocations and then with the original symbol referred, for the purpose of R6 linker relaxation. This is so that with e.g. code like this: b foo .set mips32r2 ... it's the command line options or any `.module' directive that decides how to encode any relocation for `foo' rather than the presence of `.set mips32r2'. gas/ * config/tc-mips.c (mips_force_relocation): Use `file_mips_opts' rather than `mips_opts' for the R6 ISA check. (mips_fix_adjustable): Likewise. * testsuite/gas/mips/pcrel-reloc-1.d: New test. * testsuite/gas/mips/pcrel-reloc-1-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-2.d: New test. * testsuite/gas/mips/pcrel-reloc-2-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-3.d: New test. * testsuite/gas/mips/pcrel-reloc-3-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-1.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-13/+57
gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.
2016-06-20MIPS/GAS: Update comment on jump reloc conversionMaciej W. Rozycki1-2/+2
Complement commit 44d3da233815 ("MIPS/GAS: Treat local jump relocs the same no matter if REL or RELA") and update and clarify the comment on jump reloc conversion. gas/ * config/tc-mips.c (mips_fix_adjustable): Update comment on jump reloc conversion.
2016-06-20Update the feature set for the Vulcan AArch64 cpu.Virendra Pathak1-2/+2
gas * config/tc-aarch64.c (aarch64_cpus): Update vulcan feature set.
2016-06-17opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.Jose E. Marchesi1-26/+25
This patch fixes and expands the definition of the read/write instructions for ancillary-state, privileged and hyperprivileged registers in opcodes. It also adds support for three new v9m hyperprivileged registers: %hmcdper, %hmcddfr and %hva_mask_nz. Finally, the patch expands existing tests (and adds several new ones) in order to cover all the read/write instructions in all its variants. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (rdasr): New macro. (wrasr): Likewise. (rdpr): Likewise. (wrpr): Likewise. (rdhpr): Likewise. (wrhpr): Likewise. (sparc_opcodes): Use the macros above to fix and expand the definition of read/write instructions from/to asr/privileged/hyperprivileged instructions. * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and %hva_mask_nz. Prefer softint_set and softint_clear over set_softint and clear_softint. (print_insn_sparc): Support %ver in Rd. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper, %hmcddfr and %hva_mask_nz. (sparc_ip): New handling of asr/privileged/hyperprivileged registers, adapted to the new form of the sparc opcodes table. * testsuite/gas/sparc/rdasr.s: New file. * testsuite/gas/sparc/rdasr.d: Likewise. * testsuite/gas/sparc/wrasr.s: Likewise. * testsuite/gas/sparc/wrasr.d: Likewise. * testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and wrasr tests. * testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged registers require it. * testsuite/gas/sparc/wrpr.s: Complete to cover all privileged registers and write instruction modalities. * testsuite/gas/sparc/wrpr.d: Likewise. * testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged registers. * testsuite/gas/sparc/rdhpr.d: Likewise. * testsuite/gas/sparc/wrhpr.s: Likewise. * testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17opcodes,gas: adjust sparc insns and make GAS aware of itJose E. Marchesi1-15/+25
This patch marks the SPARC instructions in the opcodes table with their proper opcode architectures, and makes the assembler aware of them. This allows the assembler to properly realize when a new instruction needs a higher architecture (after v9b) and to react accordingly emitting an error message or bumping the architecture. It also expands architecture mismatch tests to cover architectures higher than v9b, and fixes a couple of minor bugs in the GAS testsuite. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc_opcodes): Adjust instructions opcode architecture according to the hardware capabilities they require. (sparc_priv_regs): New table. (sparc_hpriv_regs): Likewise. (sparc_asr_regs): Likewise. (v9anotv9m): Define. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): adjust the GAS architectures to use the right opcode architecture. (sparc_md_end): Handle v9{c,d,e,v,m}. (sparc_ip): Fix some comments. * testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this instruction, which is v9d. * testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1' instruction from the test, as %mwait is not readable. * testsuite/gas/sparc/mwait.d: Likewise. * testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e mismatch architecture errors. * testsuite/gas/sparc/mism-2.s: New file.
2016-06-17gas: sparc: fix collision of registers and pseudo-ops.Jose E. Marchesi1-141/+240
The current sparc assembler breaks when the name of an ancillary-state register, privileged register or hyperprivileged register has a %-pseudo-operation name as a prefix. For example, %hmcdper and %hm(), or %hintp and %hi(). This patch fixes it by introducing a new table `perc_table' (for %-table) that contains an entry for every %name supported by the assembler, other than the general registers. This table is used to detect name collisions when the assembler tries to detect a %-pseudo-op. This patch also fixes a related bug, making sure that v9a_asr_table and hpriv_reg_table are sorted in reverse lexicographic order, as otherwise the search code may fail. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (priv_reg_table): Use NULL instead of the empty string to mark the end of the array. (hpriv_reg_table): Likewise. (v9a_asr_table): Likewise. (cmp_reg_entry): Handle entries with NULL names. (F_POP_V9): Define. (F_POP_PCREL): Likewise. (F_POP_TLS_CALL): Likewise. (F_POP_POSTFIX): Likewise. (struct pop_entry): New type. (pop_table): New variable. (enum pop_entry_type): New type. (struct perc_entry): Likewise. (NUM_PERC_ENTRIES): Define. (perc_table): New variable. (cmp_perc_entry): New function. (md_begin): Sort hpriv_reg_table and v9a_asr_table, and initialize perc_table. (sparc_ip): Handle entries with NULL names in priv_reg_table, hpriv_reg_table and v9a_asr_table. Use perc_table to handle %-pseudo-ops.
2016-06-15Fix simple gas testsuite failures.Nick Clifton5-1/+11
binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20 reloc. gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the instruction size. * config/tc-mcore.c (md_assemble): Likewise. * config/tc-mn10200.c (md_assemble): Likewise. * config/tc-moxie.c (md_assemble): Likewise. * config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32. * testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of exception targets. Add alpha, hppa, microblaze and rl78 to list of exceptions. (forward): Add microblaze to list of exceptions. (fwdexp): Add alpha to list of exceptions. (redef2): Add arm-epoc-pe and rl78 to list of exceptions. (redef3): Add rl78 and x86_64 cygwin to list of exceptions. (do_930509a): Alpha sort list of exception targets. Add h8300 and mn10200 to list of exceptions. (align2): Expect to fail for nds32. (cond): Add alpha and rl78 to list of exceptions. * testsuite/gas/all/none.d: Skip for ft32 and hppa. * testsuite/gas/all/string.d: Skip for tic4x. * testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff target does not support ELF. * testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target. * testsuite/gas/cfi/cfi-alpha-2.d: All extended format names. * testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH tests for sh-pe and sh-rtemscoff targets. * testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to list of exceptions. (type): Run the noifunc version for alpha-freebsd and visium. * testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore, mn10200 or moxie targets. * testsuite/gas/ft32/insn.d: Update expected disassembly. * testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin targets. * testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for mcore and rx targets. * testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k, rl78 and vax. (purge): Expect to fail on the ns32k and vax. * testsuite/gas/nds32/alu-2.d: Update expected disassembly. * testsuite/gas/nds32/ls.d: Likewise. * testsuite/gas/nds32/sys-reg.d: Likewise. * testsuite/gas/nds32/usr-spe-reg.d: Likewise. * testsuite/gas/pe/aligncomm-d.d: Skip for the sh. * testsuite/gas/pe/section-align-3.d: Likewise. * testsuite/gas/pe/section-exclude.d: Likewise. * testsuite/gas/ppc/test2xcoff32.d: Pass once all the required data has been seen. * testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow for variations in whitespace. * testsuite/gas/tilepro/t_constants.d: Pass once all the required data has been seen. * testsuite/gas/tilepro/t_constants.s (.safe_word): New macro. Installs a 32-bit value without generating warnings on 64-bit hosts. Use the new macro to replace the .word directives. opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer constants to match expected behaviour. (nds32_parse_opcode): Likewise. Also for whitespace.
2016-06-14Fix compile time warning building gas for the NDS32 with gcc v6.1.1Nick Clifton1-1/+1
gas * config/tc-nds32.c (nds32_get_align): Avoid left shifting a signed constant.
2016-06-13MIPS/GAS: Don't convert RELA JALR relocations on R6Maciej W. Rozycki1-5/+7
Revert an inadvertent change to make RELA JALR relocations section-relative on MIPS R6 targets made with commit 7361da2c952e ("Add support for MIPS R6."). There is no need to make this a special case and the comment introduced with the said change clearly indicates this was not intended. gas/ * config/tc-mips.c (mips_fix_adjustable): Don't convert RELA JALR relocations on R6. * testsuite/gas/mips/jal-svr4pic-local.d: New test. * testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test. * testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test. * testsuite/gas/mips/jal-svr4pic-local-n32.d: New test. * testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New test. * testsuite/gas/mips/jal-svr4pic-local-n64.d: New test. * testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New test. * testsuite/gas/mips/jal-svr4pic-local.s: New test source. * testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-13Accept vulcan as a cpu name for the AArch64 port of GAS.Virendra Pathak1-0/+3
* config/tc-aarch64.c (aarch64_cpus): Add Broadcom Vulcan. * doc/c-aarch64.texi: Document that vulcan is a valid processor name.
2016-06-13Fix compile time warning messages building with gcc v6.1.1Nick Clifton4-3/+13
etc * texi2pod.pl: Escape curly braces, whilst searching for keyword strong. gas * config/tc-arm.c: For non-ELF based targets skip ARM feature sets that are not supported. * config/tc-arc.c (md_apply_fix): Avoid left shifting a signed constant. * config/tc-cr16.c (check_range): Likewise. * config/tc-nios2.c (nios2_check_overflow): Likewise.
2016-06-09[AARCH64][GAS] Fix two -Wstack-usage warnings.Renlin Li1-7/+5
Warning triggerd by gcc 5 with -O0 flag. error: stack usage might be unbounded [-Werror=stack-usage=] gas/ 2016-06-08 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (print_operands): Substitute size. (output_operand_error_record): Likewise.
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