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2021-03-24x86: derive opcode length from opcode valueJan Beulich1-16/+34
In the majority of cases we can easily determine the length from the encoding, irrespective of whether a prefix is specified there as well. We further don't even need to record the value in the table entries, as it's easy enough to determine it (without any guesswork, unless an insn with major opcode 00 appeared that requires a 2nd opcode byte to be specified explicitly) when installing the chosen template for further processing. Should an encoding appear which - has a major opcode byte of 66, F3, or F2, - requires a 2nd opcode byte to be specified explicitly, - doesn't have a mandatory prefix we'd need to convert all templates presently encoding a mandatory prefix this way to the Prefix_0X<nn> model to eliminate the respective guessing i386-gen does.
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich2-73/+48
Just like is already done for legacy encoded insns, record the mandatory prefix information in the respective opcode modifier field. Do this without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-2/+3
This is in preparation of opcode_length going away as a field in the templates. Identify pseudo prefixes by a base opcode of zero instead: No real prefix has an opcode of zero. This at the same time allows dropping a curious special case from i386-gen. Since most attributes are identical for all pseudo prefixes, take the opportunity and also template them.
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich1-1/+1
In preparation to use PREFIX_0X<nn> attributes also in VEX/XOP/EVEX encoding templates, renumber the pseudo-enumerators such that their values can then also be used directly in the respective prefix bit fields.
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-48/+26
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") used the opcodeprefix field for two distinct purposes. In preparation of having VEX/XOP/EVEX and non-VEX templates become similar in the representatioon of both encoding space and opcode prefixes, split the field to have a separate one holding an insn's opcode space.
2021-03-23x86: don't open-code PREFIX_NONEJan Beulich1-11/+6
Use the constant rather than literal zero. While at it fold two conditionals (using the same base opcode and prefix) in load_insn_p().
2021-03-23x86: unbreak certain MPX insn operand formsJan Beulich2-9/+17
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") dropped the mandatory prefix bytes from legacy encoded insn templates, but failed to also adjust affected MPX-specific checks in two places. For the expressions to remain halfway readable, introduce local variables to hold current_templates->start.
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska2-5/+5
bfd/ChangeLog: * bfd-in.h (startswith): Add startswith function. (CONST_STRNEQ): Remove. * bfd-in2.h (startswith): Regenerate with make headers. * archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith. (_bfd_slurp_extended_name_table): Likewise. * archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise. * bfd.c (bfd_get_sign_extend_vma): Likewise. (bfd_convert_section_size): Likewise. (bfd_convert_section_contents): Likewise. * coff-stgo32.c (go32exe_create_stub): Likewise. (go32exe_check_format): Likewise. * coffcode.h (styp_to_sec_flags): Likewise. (GNU_DEBUGALTLINK): Likewise. * coffgen.c (_bfd_coff_section_already_linked): Likewise. (coff_gc_sweep): Likewise. (bfd_coff_gc_sections): Likewise. * cofflink.c (coff_link_add_symbols): Likewise. (process_embedded_commands): Likewise. * compress.c (bfd_is_section_compressed_with_header): Likewise. (bfd_init_section_decompress_status): Likewise. * dwarf2.c (find_debug_info): Likewise. (place_sections): Likewise. * ecoff.c (_bfd_ecoff_slurp_armap): Likewise. * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. (assign_section_numbers): Likewise. (elfcore_grok_win32pstatus): Likewise. * elf32-arm.c (cmse_scan): Likewise. (elf32_arm_gc_mark_extra_sections): Likewise. (elf32_arm_size_dynamic_sections): Likewise. (is_arm_elf_unwind_section_name): Likewise. * elf32-bfin.c (bfin_size_dynamic_sections): Likewise. * elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise. * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. * elf32-csky.c (csky_elf_size_dynamic_sections): Likewise. * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise. * elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise. * elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise. * elf32-metag.c (elf_metag_size_dynamic_sections): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise. * elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise. * elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise. * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise. * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. * elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise. (elf32_tic6x_size_dynamic_sections): Likewise. * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise. (xtensa_is_insntable_section): Likewise. (xtensa_is_littable_section): Likewise. (xtensa_is_proptable_section): Likewise. (xtensa_property_section_name): Likewise. (xtensa_callback_required_dependence): Likewise. * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise. * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise. * elf64-ia64-vms.c (is_unwind_section_name): Likewise. (get_reloc_section): Likewise. (elf64_ia64_size_dynamic_sections): Likewise. (elf64_ia64_object_p): Likewise. * elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. * elflink.c (elf_link_add_object_symbols): Likewise. (_bfd_elf_gc_mark_extra_sections): Likewise. (bfd_elf_parse_eh_frame_entries): Likewise. (_bfd_elf_section_already_linked): Likewise. * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise. * elfnn-ia64.c (is_unwind_section_name): Likewise. (elfNN_ia64_size_dynamic_sections): Likewise. (elfNN_ia64_object_p): Likewise. * elfxx-mips.c (FN_STUB_P): Likewise. (CALL_STUB_P): Likewise. (CALL_FP_STUB_P): Likewise. (_bfd_mips_elf_section_from_shdr): Likewise. (_bfd_mips_elf_fake_sections): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_link): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elfxx-x86.c (elf_i386_is_reloc_section): Likewise. (elf_x86_64_is_reloc_section): Likewise. * hpux-core.c (thread_section_p): Likewise. * libcoff.h (bfd_pei_p): Likewise. * linker.c (REAL): Likewise. (unwrap_hash_lookup): Likewise. (_bfd_generic_link_add_one_symbol): Likewise. * mmo.c (mmo_internal_write_section): Likewise. * osf-core.c (osf_core_core_file_p): Likewise. * pef.c (bfd_pef_print_symbol): Likewise. * pei-x86_64.c (pex64_print_all_pdata_sections): Likewise. * som.c (som_slurp_symbol_table): Likewise. (som_slurp_armap): Likewise. * wasm-module.c (wasm_compute_custom_section_file_position): Likewise. binutils/ChangeLog: * dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith. * emul_aix.c (ar_emul_aix_parse_arg): Likewise. * objcopy.c (is_mergeable_note_section): Likewise. * objdump.c (dump_dwarf_section): Likewise. * prdbg.c (pr_method_type): Likewise. (pr_class_baseclass): Likewise. (tg_class_baseclass): Likewise. * readelf.c (process_lto_symbol_tables): Likewise. * stabs.c (ULLHIGH): Likewise. (parse_stab_argtypes): Likewise. (stab_demangle_function_name): Likewise. gas/ChangeLog: * config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith. (x86_64_section_word): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. gdb/ChangeLog: * arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith. (_initialize_arm_tdep): Likewise. ld/ChangeLog: * emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith. * emultempl/beos.em: Likewise. * emultempl/elf.em: Likewise. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise. * ldctor.c (ctor_prio): Likewise. * ldelf.c (ldelf_try_needed): Likewise. (ldelf_parse_ld_so_conf): Likewise. (ldelf_after_open): Likewise. (output_rel_find): Likewise. (ldelf_place_orphan): Likewise. * ldfile.c (ldfile_add_library_path): Likewise. * ldlang.c (lang_add_input_file): Likewise. * ldmain.c (get_sysroot): Likewise. (get_emulation): Likewise. (add_archive_element): Likewise. * ldwrite.c (unsplittable_name): Likewise. (clone_section): Likewise. * lexsup.c (parse_args): Likewise. * pe-dll.c (is_import): Likewise. (pe_implied_import_dll): Likewise. opcodes/ChangeLog: * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. * arc-dis.c (parse_option): Likewise. * arm-dis.c (parse_arm_disassembler_options): Likewise. * cris-dis.c (print_with_operands): Likewise. * h8300-dis.c (bfd_h8_disassemble): Likewise. * i386-dis.c (print_insn): Likewise. * ia64-gen.c (fetch_insn_class): Likewise. (parse_resource_users): Likewise. (in_iclass): Likewise. (lookup_specifier): Likewise. (insert_opcode_dependencies): Likewise. * mips-dis.c (parse_mips_ase_option): Likewise. (parse_mips_dis_option): Likewise. * s390-dis.c (disassemble_init_s390): Likewise. * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-03-182021-03-18 Christian Groessler <chris@groessler.org>Christian Groessler1-16/+26
* config/tc-z8k.c (apply_fix): Handle 7-bit relocations correctly. Problem found by Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>.
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen1-0/+13
bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc. gas/ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc. (riscv_multi_subset_supports): Add INSN_CLASS_ZB*. * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext.d: Likewise. include/ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
2021-03-12aix: implement TLS relocation for gas and ldClément Chigot2-45/+203
Add support for TLS in XCOFF. Amongst the things done by this commit: - Update XCOFF auxialiary header to match new version and allow TLS sections. - Add TLS sections (.tdata and .tbss) support in gas and ld. - Add support for the TLS relocations in gas and ld. Two different types BFD_RELOC are created for PPC and PPC64 as the size is a pointer, thus distinct in 32 or 64bit. The addresses given by ld to .tdata and .tbss is a bit special. In XCOFF, these addresses are actually offsets from the TLS pointer computed at runtime. AIX assembly and linker does the same. In top of that, the .tdata must be before .data (this is mandatory for AIX loader). Thus, the aix ld script is recomputing "." before .data to restore its original value. There might be a simpler way, but this one is working. Optimisation linked to TLS relocations aren't yet implemented. bfd/ * reloc.c (BFD_RELOC_PPC_TLS_LE, BFD_RELOC_PPC_TLS_IE, BFD_RELOC_PPC_TLS_M, BFD_RELOC_PPC_TLS_ML, BFD_RELOC_PPC64_TLS_GD, BFD_RELOC_PPC64_TLS_LD, BFD_RELOC_PPC64_TLS_LE, BFD_RELOC_PPC64_TLS_IE, BFD_RELOC_PPC64_TLS_M, BFD_RELOC_PPC64_TLS_ML): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_tls for TLS relocations. (xcoff_howto_table): Implement TLS relocations. (_bfd_xcoff_reloc_type_lookup): Add cases TLS relocations. (xcoff_reloc_type_tls): New function. * coff64-rs6000.c (xcoff_calculate_relocation): Likewise. (xcoff_howto_table): Likewise. (_bfd_xcoff_reloc_type_lookup): Likewise. * coffcode.h (sec_to_styp_flags): Handle TLS sections. (styp_to_sec_flags): Likewise. (coff_compute_section_file_positions): Avoid file offset optimisation for .data when the previous section is .tdata. (coff_write_object_contents): Handle TLS sections. * coffswap.h (coff_swap_aouthdr_out): Add support for new fields in aouthdr. * libxcoff.h (xcoff_reloc_type_tls): Add prototype. * xcofflink.c (xcoff_link_add_symbols): Handle XMC_UL. (xcoff_need_ldrel_p): Add cases for TLS relocations. (xcoff_create_ldrel): Add l_symndx for TLS sections. gas/ * config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section, (ppc_xcoff_bss_section, ppc_xcoff_tdata_section, (ppc_xcoff_tbss_section): New variables. (ppc_text_subsegment, ppc_text_csects, ppc_data_subgments, (ppc_data_csects): Removed. (ppc_xcoff_section_is_initialized, ppc_init_xcoff_section, ppc_xcoff_parse_cons): New functions. (md_being): Initialize XCOFF sections. (ppc_xcoff_suffix): Add support for TLS relocations (fixup_size, md_apply_fix): Add support for new BFD_RELOC. (ppc_change_csect): Handle XMC_TL, XMC_UL. Correctly, add XMC_BS to .bss section. Handle new XCOFF section variables. (ppc_comm): Likewise. (ppc_toc): Likewise. (ppc_symbol_new_hook): Likewise. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Add tbss support. * config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): New define. (ppc_xcoff_parse_cons): Add prototype. (struct ppc_xcoff_section): New structure. ld/ * emultempl/aix.em: Ensure .tdata section is removed if empty, even with -r flag. * scripttempl/aix.sc: Handle TLS sections. * testsuite/ld-powerpc/aix52.exp: Add new tests. * testsuite/ld-powerpc/aix-tls-reloc-32.d: New test. * testsuite/ld-powerpc/aix-tls-reloc-64.d: New test. * testsuite/ld-powerpc/aix-tls-reloc.ex: New test. * testsuite/ld-powerpc/aix-tls-reloc.s: New test. * testsuite/ld-powerpc/aix-tls-section-32.d: New test. * testsuite/ld-powerpc/aix-tls-section-64.d: New test. * testsuite/ld-powerpc/aix-tls-section.ex: New test. * testsuite/ld-powerpc/aix-tls-section.s: New test. include/ * coff/internal.h (struct internal_aouthdr): Add new fields. * coff/rs6000.h (AOUTHDRÃ): Add new fields. * coff/rs6k64.h (struct external_filehdr): Likewise. * coff/xcoff.h (_TDATA), _TBSS): New defines (RS6K_AOUTHDR_TLS_LE, RS6K_AOUTHDR_RAS, RS6K_AOUTHDR_ALGNTDATA, RS6K_AOUTHDR_SHR_SYMTAB, RS6K_AOUTHDR_FORK_POLICY, RS6K_AOUTHDR_FORK_COR): New defines. (XMC_TU): Removed. (XMC_UL): New define.
2021-03-12aix: implement R_TOCU and R_TOCL relocationsClément Chigot1-8/+145
Implement support for largetoc on XCOFF. R_TOCU and R_TOCL are referenced by the new BFD defines: BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. A new toc storage class is added XMC_TE. In order to correctly handle R_TOCU, the logic behind xcoff_reloc_type_toc is changed to compute the whole TOC offset instead of just the difference between the "link" offset and the "assembly" offset. In gas, add a function to transform addis format used by AIX "addis RT, D(RA)" into the ELF format "addis RT, RA, SI". bfd/ * reloc.c (BFD_RELOC_PPC_TOC16_HI, BFD_RELOC_PPC_TOC16_LO): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_toc for R_TOCU and R_TOCL. (xcoff_howto_table): Remove src_mask for TOC relocations. Add R_TOCU and R_TOCL howtos. (_bfd_xcoff_reloc_type_lookup): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (xcoff_reloc_type_toc): Compute the whole offset. Implement R_TOCU and R_TOCL. * coff64-rs6000.c (xcoff64_calculate_relocation): Likewise. (xcoff64_howto_table): Likewise. (xcoff64_reloc_type_lookup): Likewise. gas/ * config/tc-ppc.c (ppc_xcoff_suffix): New function. (MAP, MAP32, MAP64): New macros for XCOFF. (ppc_xcoff_fixup_addis): New function. (ppc_is_toc_sym): Handle XMC_TE. (fixup_size): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (md_assemble): Call ppc_xcoff_fixup_addis for XCOFF. (ppc_change_csect): Handle XMC_TE. (ppc_tc): Enable .tc symbols to have only a XMC_TC or XMC_TE storage class. (ppc_symbol_new_hook): Handle XMC_TE. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Likewise. (md_apply_fix): Handle BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. ld/ * scripttempl/aix.sc: Add .te to .data section. * testsuite/ld-powerpc/aix52.exp: Add test structure for AIX7+. Add aix-largetoc-1 test. * testsuite/ld-powerpc/aix-largetoc-1-32.d: New test. * testsuite/ld-powerpc/aix-largetoc-1-64.d: New test. * testsuite/ld-powerpc/aix-largetoc-1.ex: New test. * testsuite/ld-powerpc/aix-largetoc-1.s: New test.
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-9/+12
RepPrefixOk, HLEPrefixOk, and NoTrackPrefixOk can't be specified together, so can share an enum-like field. IsLockable can be inferred from HLE setting and hence only needs specifying when neither of them is present.
2021-02-26Correct an error message in the ARM assembler.Nick Clifton1-1/+1
PR 27411 * config/tc-arm.c (do_t_add_sub): Correct error message. * testsuite/gas/arm/pr27411.s: New test. * testsuite/gas/arm/pr27411.d: New test driver. * testsuite/gas/arm/pr27411.l: Expected error output for new test.
2021-02-24PR23691, gas .y files vs. automatic make dependenciesAlan Modra2-2/+2
A number of targets, bfin, rl78, rx, can show odd failures when bfd/reloc.c changes BFD_RELOC_* enum values, if recompiling over a build dir with existing objects. The problem is caused by bfin-parse.o and similar not being recompiled and so using stale BFD_RELOC_* values. This isn't fixed by making bfin-parse.c depend on bfd/reloc.c, which isn't necessary anyway. bfin-parse.o should have been recompiled due to bfd/bfd.h changing when extracted bfd/reloc.c BFD_RELOC_* values change, but that wasn't happening. The problem is that automake generates a makefile that loads gas/config/.deps/ dependency file for objects with corresponding sources mentioned in EXTRA_as_new_SOURCES. Unless we want to mess around generating explicit dependencies, I think that mean moving some object files to the build gas/config/. This patch does that, removing some hacks for m68k-parse.c that should no longer be necessary, and removes some rules that catered to old bison producing code that triggers compiler warnings. PR 23691 * Makefile.am (TARGET_CPU_CFILES): Split off config/xtensa-relax.c.. (TARGET_CPU_HFILES): ..and config/xtensa-relax.h.. (TARGET_EXTRA_FILES): ..to here. Add config/bfin-lex-wrapper.c, and use alongside TARGET_CPU_CFILES. (EXTRA_DIST): Update location of generated .c files. (config/m68k-parse.c): New rule replacing m68k-parse.c rule. (config/bfin-parse.c, config/rl78-parse.cm config/rx-parse.c), (config/bfin-lex.c, config/bfin-lex-wrapper.@OBJEXT@): Similarly. (itbl-lex-wrapper.@OBJEXT@): Simplify to just the needed dependencies. (itbl-parse.@OBJEXT@): Delete rule using NO_WERROR. (itbl-parse.c, itbl-parse.h): Tidy. * config/bfin-lex-wrapper.c: Include config/bfin-lex.c. * config/bfin-lex.l: Include config/bfin-parse.h. * configure.ac (extra_objects): Move object files corresponding to .y and .l files now in config/ to config/. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-02-19Fix compile time warnings when building riscv assembler.Nick Clifton1-3/+3
* config/tc-riscv.c (riscv_ip): Fix compile time warnings about misleading indentation.
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-89/+92
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-24/+113
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.
2021-02-16gas: Allow SHF_GNU_RETAIN on all sectionsH.J. Lu1-6/+12
Since SHF_GNU_RETAIN is allowed on all sections, strip SHF_GNU_RETAIN when checking incorrect section attributes. PR gas/27412 * config/obj-elf.c (obj_elf_change_section): Strip SHF_GNU_RETAIN when checking incorrect section attributes. * testsuite/gas/elf/elf.exp: Run section28 and section29. * testsuite/gas/elf/section28.d: New file. * testsuite/gas/elf/section28.s: Likewise. * testsuite/gas/elf/section29.d: Likewise. * testsuite/gas/elf/section29.s: Likewise.
2021-02-16x86: honor template rather than actual operands when updating i.xstateJan Beulich1-5/+5
This undoes a change to md_assemble() that 32930e4edbc0 ("x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker") did without any explanation. This broke a CVTPI2PS property test that a subsequent test will add, and the updates to existing tests also demonstrate what was wrong: For example, AVX insns update the full YMM, even if a Vex128 variant is in use.
2021-02-16x86: record register use for SIMD insns without respective explicit operandsJan Beulich1-0/+12
VZERO{ALL,UPPER} modify YMM registers despite having no operands. While {,V}{LD,ST}MXCSR don't modify XMM registers, MXCSR and XMMn collectively form underlying machine state.
2021-02-15IBM Z: Implement instruction set extensionsAndreas Krebbel1-0/+2
opcodes/ * s390-mkopc.c (main): Accept arch14 as cpu string. * s390-opc.txt: Add new arch14 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH14. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch14. * doc/c-s390.texi: Document arch14 march option. * testsuite/gas/s390/s390.exp: Run the arch14 related tests. * testsuite/gas/s390/zarch-arch14.d: New test. * testsuite/gas/s390/zarch-arch14.s: New test.
2021-02-09Remove arm-symbianelfAlan Modra2-27/+1
* configure.ac: Delete arm*-*-symbianelf* entry. * configure: Regenerate. bfd/ * config.bfd (arm*-*-symbianelf*): Move from obsolete to removed. * configure.ac: Delete symbian entries. * elf-bfd.h (enum elf_target_os): Delete is_symbian. * elf32-arm.c: Remove symbian support. Formatting. * targets.c: Delete symbian entries. * configure: Regenerate. binutils/ * testsuite/lib/binutils-common.exp (supports_gnu_osabi): Remove symbianelf. gas/ * Makefile.am (TARG_ENV_HFILES): Remove config/te-symbian.h. * config/tc-arm.c (elf32_arm_target_format): Remove TE_SYMBIAN support. * config/te-symbian.h: Delete. * configure.tgt: Remove arm-*-symbianelf*. * testsuite/gas/arm/arch4t-eabi.d: Don't mention symbianelf in target selection. * testsuite/gas/arm/arch4t.d: Likewise. * testsuite/gas/arm/got_prel.d: Likewise. * testsuite/gas/arm/mapdir.d: Likewise. * testsuite/gas/arm/mapmisc.d: Likewise. * testsuite/gas/arm/mapsecs.d: Likewise. * testsuite/gas/arm/mapshort-eabi.d: Likewise. * testsuite/gas/arm/thumb-eabi.d: Likewise. * testsuite/gas/arm/thumb.d: Likewise. * testsuite/gas/arm/thumbrel.d: Likewise. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove earmsymbian.c. Don't include symbian dep file. * configure.tgt: Remove arm*-*-symbianelf* entry. * emulparams/armsymbian.sh: Delete. * ld.texi: Don't mention symbian. * scripttempl/armbpabi.sc: Delete. * testsuite/ld-arm/symbian-seg1.d: Delete. * testsuite/ld-arm/symbian-seg1.s: Delete. * testsuite/ld-arm/arm-elf.exp: Don't run symbian-seg1. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2021-02-08opcodes: tic54x: namespace exported variablesMike Frysinger1-14/+14
The tic54x exports some fairly generic variable names that can conflict with programs that use them, so put proper tic54x_ prefixes on all of them.
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu1-10/+0
bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Removed INSN_CLASS_ZB*. * testsuite/gas/riscv/bitmanip-insns-32.d: Removed. * testsuite/gas/riscv/bitmanip-insns-64.d: Removed. * testsuite/gas/riscv/bitmanip-insns.s: Removed. include/ * opcode/riscv-opc.h: Removed macros for zb* extensions. * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (MASK_RVB_IMM): Removed. (riscv_opcodes): Removed zb* instructions. (riscv_ext_version_table): Removed versions for zb*.
2021-02-01PR27283 gas for alpha fails to build with gcc 11Alan Modra1-1/+1
PR 27283 * config/tc-alpha.c (insert_operand): Delete dead code.
2021-01-26nios2: Don't disable relaxation with --gdwarf-NH.J. Lu1-4/+0
GCC 11 passes --gdwarf-5 to assembler to enable DWARF5 debug info. Don't disable relaxation when --gdwarf-N is specified. The assembler generated debug information will treat the sequence of the relaxed instructions as a single instruction. PR gas/27243 * config/tc-nios2.c (md_begin): Don't disable relaxation with --gdwarf-N. * testsuite/gas/nios2/relax.d: New file. * testsuite/gas/nios2/relax.s: Likewise.
2021-01-18PR27198, segv in S_IS_WEAKAlan Modra1-0/+3
Fix a NULL dereference seen when assembling invalid input. PR 27198 * config/tc-i386.c (need_plt32_p): Return FALSE for NULL symbol. * testsuite/gas/i386/pr27198.d, * gas/testsuite/gas/i386/pr27198.err, * gas/testsuite/gas/i386/pr27198.s: New test. * gas/testsuite/gas/i386/i386.exp: Run it.
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2-59/+55
bfd/ * elfnn-riscv.c: Indent, labels and GNU coding standards tidy, also aligned the code. gas/ * config/tc-riscv.c: Indent and GNU coding standards tidy, also aligned the code. * config/tc-riscv.h: Likewise. include/ * opcode/riscv.h: Indent and GNU coding standards tidy, also aligned the code. opcodes/ * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. (riscv_fpr_names_abi): Likewise. (riscv_opcodes): Likewise. (riscv_insn_types): Likewise.
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu1-58/+66
Error and warning messages usually starting with lower case letter, and without the period at the end. Besides, add the prefixed "internel:" at the beginning of the messages when they are caused internally. Also fix indents and typos. bfd/ * elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages. gas/ * config/tc-riscv.c: Error and warning messages tidy. * testsuite/gas/riscv/priv-reg-fail-fext.l: Updated. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. opcodes/ * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-161/+130
The GNU coding standards said the comments should be complete sentences and end with a period and two spaces. But sometimes it should be more cleaner when the comments only include a word or codes. Therefore, I made the following changes after referring to other target/generic codes, * Try to write sentences in comments, must end with a period and two spaces. * End with two spaces without a period for codes/instructions only. * End with one space without a period for a single word/variable only. Besids, also rewrite/remove some comments which are obsolete or too long, and fix indents for comments. bfd/ * elfnn-riscv.c: Comments tidy and improvement. * elfxx-riscv.c: Likewise. * elfxx-riscv.h: Likewise. gas/ * config/tc-riscv.c: Comments tidy and improvement. Also update comment "fallthru" to "Fall through" that end with a period and two spaces. include/ * elf/riscv.h: Comments tidy and improvement. * opcode/riscv-opc.h: Likewise. * opcode/riscv.h: Likewise. opcodes/ * riscv-dis.c: Comments tidy and improvement. * riscv-opc.c: Likewise.
2021-01-14gas: make [248]byte directives available everywhereMike Frysinger1-4/+0
These aren't specific to ELF at all, and seem generally useful. So pull them out of the ELF backend and into the common core.
2021-01-14gas: bfin: fix build time warningsMike Frysinger1-1/+4
2021-01-13x86: Don't generate GOT_symbol for PLT relocationsH.J. Lu1-19/+20
Don't generate the _GLOBAL_OFFSET_TABLE_ symbol for PLT relocations since it isn't needed. PR gas/27178 * config/tc-i386.c (lex_got::gotrel): Add need_GOT_symbol. Don't generate GOT_symbol for PLT relocations. * testsuite/gas/i386/i386.exp: Run PR gas/27178 tests. * testsuite/gas/i386/no-got.d: New file. * testsuite/gas/i386/no-got.s: Likewise. * testsuite/gas/i386/x86-64-no-got.d: Likewise. * testsuite/gas/i386/x86-64-no-got.s: Likewise.
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-31/+0
This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-07ELF: Don't generate unused section symbolsH.J. Lu1-0/+3
For ELF targets, section symbols are required only for relocations. With -ffunction-sections -fdata-sections, there can be many unused section symbols. Sizes of libstdc++.a on Linux/x86-64 in GCC 11 are With unused section symbols : 39411698 bytes Without unused section symbols: 39227002 bytes The unused section symbols in libstdc++.a occupy more than 180 KB. Add BSF_SECTION_SYM_USED to indicate if a section symbol should be included in the symbol table. The BSF_SECTION_SYM_USED should be set if the section symbol is used for relocation or the section symbol is always included in the symbol table. Add keep_unused_section_symbols to bfd_target to indicate if unused section symbols should be kept. If TARGET_KEEP_UNUSED_SECTION_SYMBOLS is defined as FALSE, unused ection symbols will be removed. Tested on Linux/x86. Other ELF backends need to: 1. Define TARGET_KEEP_UNUSED_SECTION_SYMBOLS to FALSE. 2. Mark used section symbols in assembler backend. 3. Remove unused section symbols from expected assembler and linker outputs. bfd/ PR 27109 * aix386-core.c (core_aix386_vec): Initialize keep_unused_section_symbol to TARGET_KEEP_UNUSED_SECTION_SYMBOLS. * aout-target.h (MY (vec)): Likewise. * binary.c (binary_vec): Likewise. * cisco-core.c (core_cisco_be_vec): Likewise. (core_cisco_le_vec): Likewise. * coff-alpha.c (alpha_ecoff_le_vec): Likewise. * coff-i386.c (TARGET_SYM): Likewise. (TARGET_SYM_BIG): Likewise. * coff-ia64.c (TARGET_SYM): Likewise. * coff-mips.c (mips_ecoff_le_vec): Likewise. (mips_ecoff_be_vec): Likewise. (mips_ecoff_bele_vec): Likewise. * coff-rs6000.c (rs6000_xcoff_vec): Likewise. (powerpc_xcoff_vec): Likewise. * coff-sh.c (sh_coff_small_vec): Likewise. (sh_coff_small_le_vec): Likewise. * coff-tic30.c (tic30_coff_vec): Likewise. * coff-tic54x.c (tic54x_coff0_vec): Likewise. (tic54x_coff0_beh_vec): Likewise. (tic54x_coff1_vec): Likewise. (tic54x_coff1_beh_vec): Likewise. (tic54x_coff2_vec): Likewise. (tic54x_coff2_beh_vec): Likewise. * coff-x86_64.c (TARGET_SYM): Likewise. (TARGET_SYM_BIG): Likewise. * coff64-rs6000.c (rs6000_xcoff64_vec): Likewise. (rs6000_xcoff64_aix_vec): Likewise. * coffcode.h (CREATE_BIG_COFF_TARGET_VEC): Likewise. (CREATE_BIGHDR_COFF_TARGET_VEC): Likewise. (CREATE_LITTLE_COFF_TARGET_VEC): Likewise. * elfxx-target.h (TARGET_BIG_SYM): Likewise. (TARGET_LITTLE_SYM): Likewise. * hppabsd-core.c (core_hppabsd_vec): Likewise. * hpux-core.c (core_hpux_vec): Likewise. * i386msdos.c (i386_msdos_vec): Likewise. * ihex.c (ihex_vec): Likewise. * irix-core.c (core_irix_vec): Likewise. * mach-o-target.c (TARGET_NAME): Likewise. * mmo.c (mmix_mmo_vec): Likewise. * netbsd-core.c (core_netbsd_vec): Likewise. * osf-core.c (core_osf_vec): Likewise. * pdp11.c (MY (vec)): Likewise. * pef.c (pef_vec): Likewise. (pef_xlib_vec): Likewise. * plugin.c (plugin_vec): Likewise. * ppcboot.c (powerpc_boot_vec): Likewise. * ptrace-core.c (core_ptrace_vec): Likewise. * sco5-core.c (core_sco5_vec): Likewise. * som.c (hppa_som_vec): Likewise. * srec.c (srec_vec): Likewise. (symbolsrec_vec): Likewise. * tekhex.c (tekhex_vec): Likewise. * trad-core.c (core_trad_vec): Likewise. * verilog.c (verilog_vec): Likewise. * vms-alpha.c (alpha_vms_vec): Likewise. * vms-lib.c (alpha_vms_lib_txt_vec): Likewise. * wasm-module.c (wasm_vec): Likewise. * xsym.c (sym_vec): Likewise. * elf.c (ignore_section_sym): Return TRUE if BSF_SECTION_SYM_USED isn't set. (elf_map_symbols): Don't include ignored section symbols. * elfcode.h (elf_slurp_symbol_table): Also set BSF_SECTION_SYM_USED on STT_SECTION symbols. * elflink.c (bfd_elf_final_link): Generated section symbols only when emitting relocations or reqired. * elfxx-x86.h (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): New. * syms.c (BSF_SECTION_SYM_USED): New. * targets.c (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): New. (bfd_target): Add keep_unused_section_symbols. (bfd_keep_unused_section_symbols): New. * bfd-in2.h: Regenerated. binutils/ PR 27109 * objcopy.c (copy_object): Handle section symbols for non-relocatable inputs. * testsuite/binutils-all/readelf.exp (readelf_test): Check is_elf_unused_section_symbols. * testsuite/binutils-all/readelf.s-64: Updated. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: New file. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. * testsuite/binutils-all/readelf.ss-unused: Likewise. * testsuite/lib/binutils-common.exp (is_elf_unused_section_symbols): New proc. gas/ChangeLog: PR 27109 * read.c (s_reloc): Call symbol_mark_used_in_reloc on the section symbol. * subsegs.c (subseg_set_rest): Set BSF_SECTION_SYM_USED if needed. * write.c (adjust_reloc_syms): Call symbol_mark_used_in_reloc on the section symbol. (set_symtab): Don't generate unused section symbols. (maybe_generate_build_notes): Call symbol_mark_used_in_reloc on the section symbol. * config/obj-elf.c (elf_adjust_symtab): Call symbol_mark_used_in_reloc on the group signature symbol. * testsuite/gas/cfi/cfi-label.d: Remove unused section symbols from expected output. * testsuite/gas/elf/elf.exp (run_elf_list_test): Check is_elf_unused_section_symbols. * testsuite/gas/elf/section2.e: Updated. * testsuite/gas/elf/section2.e-unused: New file. * testsuite/gas/elf/symver.d: Remove unused section symbols. * testsuite/gas/i386/ilp32/elf/symver.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-3.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-5.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-unwind.d: Likewise. * testsuite/gas/i386/size-1.d: Likewise. * testsuite/gas/i386/size-3.d: Likewise. * testsuite/gas/i386/svr4.d: Likewise. * testsuite/gas/i386/x86-64-size-1.d: Likewise. * testsuite/gas/i386/x86-64-size-3.d: Likewise. * testsuite/gas/i386/x86-64-size-5.d: Likewise. * testsuite/gas/i386/x86-64-unwind.d: Likewise. ld/ PR 27109 * testsuite/ld-elf/export-class.sd: Adjust the expected output. * testsuite/ld-elf/loadaddr3b.d: Likewise. * testsuite/ld-i386/ibt-plt-1.d: Likewise. * testsuite/ld-i386/ibt-plt-2a.d: Likewise. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-3a.d: Likewise. * testsuite/ld-i386/ibt-plt-3c.d: Likewise. * testsuite/ld-i386/pr19636-1d.d: Likewise. * testsuite/ld-i386/pr19636-1l.d: Likewise. * testsuite/ld-i386/pr19636-2c.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/pr17154-i386-now.d: Likewise. * testsuite/ld-ifunc/pr17154-i386.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64-now.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64.d: Likewise. * testsuite/ld-x86-64/bnd-branch-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/pr19609-4e.d: Likewise. * testsuite/ld-x86-64/pr19609-6a.d: Likewise. * testsuite/ld-x86-64/pr19609-6b.d: Likewise. * testsuite/ld-x86-64/pr19609-7b.d: Likewise. * testsuite/ld-x86-64/pr19609-7d.d: Likewise. * testsuite/ld-x86-64/pr19636-2l.d: Likewise. * testsuite/ld-x86-64/pr20253-1d.d: Likewise. * testsuite/ld-x86-64/pr20253-1h.d: Likewise. * testsuite/ld-x86-64/pr21038b-now.d: Likewise. * testsuite/ld-x86-64/pr21038b.d: Likewise. * testsuite/ld-x86-64/pr21038c-now.d: Likewise. * testsuite/ld-x86-64/pr21038c.d: Likewise. * testsuite/ld-x86-64/pr23854.d: Likewise. * testsuite/ld-x86-64/pr25416-3.d: Likewise. * testsuite/ld-x86-64/pr25416-4.d: Likewise. * testsuite/ld-i386/plt-pic.pd: Likewise. * testsuite/ld-i386/plt-pic2.dd: Likewise. * testsuite/ld-i386/plt.pd: Likewise. * testsuite/ld-i386/plt2.dd: Likewise. * testsuite/ld-i386/tlsbin.rd: Likewise. * testsuite/ld-i386/tlsbin2.rd: Likewise. * testsuite/ld-i386/tlsbindesc.rd: Likewise. * testsuite/ld-i386/tlsdesc.rd: Likewise. * testsuite/ld-i386/tlsgdesc.rd: Likewise. * testsuite/ld-i386/tlsnopic.rd: Likewise. * testsuite/ld-i386/tlspic.rd: Likewise. * testsuite/ld-i386/tlspic2.rd: Likewise. * testsuite/ld-x86-64/mpx3.dd: Likewise. * testsuite/ld-x86-64/mpx3n.dd: Likewise. * testsuite/ld-x86-64/mpx4.dd: Likewise. * testsuite/ld-x86-64/mpx4n.dd: Likewise. * testsuite/ld-x86-64/pe-x86-64-1.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-2.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-3.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-4.od: Likewise. * testsuite/ld-x86-64/plt.pd: Likewise. * testsuite/ld-x86-64/plt2.dd: Likewise. * testsuite/ld-x86-64/tlsbin.rd: Likewise. * testsuite/ld-x86-64/tlsbin2.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsdesc.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc.rd: Likewise. * testsuite/ld-x86-64/tlspic.rd: Likewise. * testsuite/ld-x86-64/tlspic2.rd: Likewise. * testsuite/ld-elf/sec64k.exp: Check is_elf_unused_section_symbols.
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich1-0/+2
Add support for the pause hint instruction, as specified in the Zihintpause extension. The pause instruction is encoded as a special form of a memory fence (which is available as part of the base instruction set). The chosen encoding does not mandate any particular memory ordering and therefore is a true hint. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Added INSN_CLASS_ZIHINTPAUSE. * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for the pause hint instruction. * testsuite/gas/riscv/pause.s: Likewise. include/ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN for pause hint instruction. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE. opcodes/ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf1-1/+13
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we should update them to INSN_ALIAS when we have supported their true instruction in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW] to encode them. Besides, the orc.b has the same encoding both in rv32 and rv64, so we just keep one of them in the opcode table. This patch is implemented according to the following link, https://github.com/riscv/riscv-bitmanip/pull/101 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> Jim Wilson <jimw@sifive.com> Andrew Waterman <andrew@sifive.com> Maxim Blinov <maxim.blinov@embecosm.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*. (riscv_get_default_ext_version): Do not check the default_isa_spec when the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT. * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase. * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise. * testsuite/gas/riscv/bitmanip-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*. (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the frozen extensions. opcodes/ * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2021-01-06RISC-V: Implement support for big endian targets.Marcus Comstedt2-7/+27
RISC-V instruction/code is always little endian, but data might be big-endian. Therefore, we can not use the original bfd_get/bfd_put to get/put the code for big endian targets. Add new riscv_get_insn and riscv_put_insn to always get/put code as little endian can resolve the problem. Just remember to update them once we have supported the 48-bit/128-bit instructions in the future patches. bfd/ * config.bfd: Added targets riscv64be*-*-*, riscv32be*-*-* and riscvbe*-*-*. Also added riscv_elf[32|64]_be_vec. * configure.ac: Handle riscv_elf[32|64]_be_vec. * configure: Regenerate. * elfnn-riscv.c: Include <limits.h> and define CHAR_BIT for riscv_is_insn_reloc. (riscv_get_insn): RISC-V instructions are always little endian, but bfd_get may be used for big-endian, so add new riscv_get_insn to handle the insturctions. (riscv_put_insn): Likewsie. (riscv_is_insn_reloc): Check if we are relocaing an instruction. (perform_relocation): Call riscv_is_insn_reloc to decide if we should use riscv_[get|put]_insn or bfd_[get|put]. (riscv_zero_pcrel_hi_reloc): Use riscv_[get|put]_insn, bfd_[get|put]l32 or bfd_[get|put]l16 for code. (riscv_elf_relocate_section): Likewise. (riscv_elf_finish_dynamic_symbol): Likewise. (riscv_elf_finish_dynamic_sections): Likewise. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_pc): Likewise. (riscv_elf_object_p): Handled for big endian. (TARGET_BIG_SYM, TARGET_BIG_NAME): Defined. * targets.c: Add riscv_elf[32|64]_be_vec. (_bfd_target_vector): Likewise. gas/ * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and elf32-bigriscv. (install_insn): Always write instructions as little endian. (riscv_make_nops): Likewise. (md_convert_frag_branch): Likewise. (md_number_to_chars): Write data in target endianness. (options, md_longopts): Add -mbig-endian and -mlittle-endian options. (md_parse_option): Handle the endian options. * config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not already defined. * configure.tgt: Added riscv64be*, riscv32be*, riscvbe*. ld/ * configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*, riscv32be*-*-linux*, and riscv64be*-*-linux*. * Makefile.am: Added eelf32briscv.c, eelf32briscv_ilp32f.c and eelf32briscv_ilp32.c. * Makefile.in: Regenerate. * emulparams/elf32briscv.sh: Added. * emulparams/elf32briscv_ilp32.sh: Likewise. * emulparams/elf32briscv_ilp32f.sh: Likewise. * emulparams/elf64briscv.sh: Likewise. * emulparams/elf64briscv_lp64.sh: Likewise. * emulparams/elf64briscv_lp64f.sh: Likewise.
2021-01-04elf: Allow mixed ordered/unordered inputs for non-relocatable linkH.J. Lu1-1/+3
For non-relocatable link with SHF_LINK_ORDER inputs, allow mixed indirect and data inputs with ordered and unordered inputs: 1. Add pattern to bfd_section for the matching section name pattern in linker script and update BFD_FAKE_SECTION. 2. Sort the consecutive bfd_indirect_link_order sections with the same pattern to allow linker script to overdide input section order. 3. Place unordered sections before ordered sections. 4. Change the offsets of the indirect input sections only. bfd/ PR ld/26256 * elflink.c (compare_link_order): Place unordered sections before ordered sections. (elf_fixup_link_order): Add a link info argument. Allow mixed ordered and unordered input sections for non-relocatable link. Sort the consecutive bfd_indirect_link_order sections with the same pattern. Change the offsets of the bfd_indirect_link_order sections only. (bfd_elf_final_link): Pass info to elf_fixup_link_order. * section.c (bfd_section): Add pattern. (BFD_FAKE_SECTION): Initialize pattern to NULL. * bfd-in2.h: Regenerated. gas/ PR ld/26256 * config/obj-elf.c (obj_elf_change_section): Also filter out SHF_LINK_ORDER. ld/ PR ld/26256 * ldlang.c (gc_section_callback): Set pattern. * testsuite/ld-elf/pr26256-1.s: New file. * testsuite/ld-elf/pr26256-1.t: Likewise. * testsuite/ld-elf/pr26256-1a.d: Likewise. * testsuite/ld-elf/pr26256-1b.d: Likewise. * testsuite/ld-elf/pr26256-2.s: Likewise. * testsuite/ld-elf/pr26256-2.t: Likewise. * testsuite/ld-elf/pr26256-2a.d: Likewise. * testsuite/ld-elf/pr26256-2b-alt.d: Likewise. * testsuite/ld-elf/pr26256-2b.d: Likewise. * testsuite/ld-elf/pr26256-3.s: Likewise. * testsuite/ld-elf/pr26256-3a.d: Likewise. * testsuite/ld-elf/pr26256-3a.t: Likewise. * testsuite/ld-elf/pr26256-3b.d: Likewise. * testsuite/ld-elf/pr26256-3b.t: Likewise.
2021-01-01PR27116, Spelling errors found by Debian style checkerAlan Modra3-5/+5
PR 27116 bfd/ * xcofflink.c: Correct spelling in comments. binutils/ * coffgrok.c (do_type): Correct spelling of auxiliary in errors. * doc/binutils.texi: Correct grammar. * readelf.c (process_version_sections): Correct spelling of auxiliary in warning. * testsuite/binutils-all/vax/objdump.exp: Comment grammar fix. config/ * override.m4: Correct comment grammar. gas/ * config/tc-i386.c: Correct comment spelling. * config/tc-riscv.c: Likewise. * config/tc-s390.c: Correct comment grammar. * doc/c-i386.texi: Correct spelling. * doc/c-s390.texi: Correct grammar. gold/ * tilegx.cc: Correct comment spelling. gprof/ * README: Correct grammar. * gprof.texi: Likewise. include/ * coff/internal.h: Correct comment spelling. * coff/sym.h: Likewise. * opcode/aarch64.h: Likewise. ld/ * configure.tgt: Correct comment grammar. * emultempl/m68hc1xelf.em: Likewise. * ld.texi: Correct grammar.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra237-237/+237
2021-01-01gas: Change to "swym 0" as canonical nop insn for MMIXHans-Peter Nilsson1-1/+1
While "set $0, $0" works, that's not the documented instruction to do nothing for MMIX. However, I'm not changing it for "nop_type 5" as seen in gas.exp and org-1.s, because "set $0, $0" seems like it could be re-used there, for some future ISA. gas/ * config/tc-mmix.h (md_single_noop_insn): Change to "swym 0".
2020-12-16constify elfNN_bedAlan Modra1-16/+11
elfNN_bed was made writable as an expedient means of communicating ld -z max-page-size and ld -z common-page-size values to BFD linker code, and even for objcopy to communicate segment alignment between copy_private_bfd_data, rewrite_elf_program_header and assign_file_positions_for_load_sections. Some time later elfNN_bed elf_osabi was written by gas. It turns out none of these modifications to elfNN_bed was necessary, so make it const again. include/ * bfdlink.h (struct bfd_link_info): Add maxpagesize and commonpagesize. bfd/ * elfxx-target.h (elfNN_bed): Constify. * bfd.c (bfd_elf_set_pagesize): Delete. (bfd_emul_set_maxpagesize, bfd_emul_set_commonpagesize): Delete. * elf.c (get_program_header_size): Get commonpagesize from link info. (_bfd_elf_map_sections_to_segments): Get maxpagesize from link info. (assign_file_positions_for_load_sections): Likewise. (assign_file_positions_for_non_load_sections): Likewise. (rewrite_elf_program_header): Add maxpagesize param. Set map_p_align. (copy_private_bfd_data): Don't call bfd_elf_set_maxpagesize. Instead pass maxpagesize to rewrite_elf_program_header. * elf32-nds32.c (relax_range_measurement): Add link_info param. Get maxpagesize from link_info. Adjust caller. * bfd-in2.h: Regenerate. gas/ * config/obj-elf.c (obj_elf_section): Don't set elf_osabi here. (obj_elf_type): Likewise. ld/ * ld.h (ld_config_type): Delete maxpagesize and commonpagesize. * emultempl/elf.em: Use link_info rather than config for maxpagesize and commonpagesize. * emultempl/ppc32elf.em: Likewise. * ldexp.c (fold_binary, fold_name): Likewise. * ldemul.c (after_parse_default): Likewise. (set_output_arch_default): Don't call bfd_emul_set_maxpagesize or bfd_emul_set_commonpagesize.
2020-12-16PR27071, gas bugs uncovered by fuzzingAlan Modra2-1/+22
PR 27071 * config/obj-elf.c (elf_obj_symbol_clone_hook): New function. (elf_format_ops): Set symbol_clone_hook. * config/obj-elf.h (elf_obj_symbol_clone_hook): Declare. (obj_symbol_clone_hook): Define. * listing.c (buffer_line): Avoid integer overflow on paper_width set to zero.
2020-12-11Add support for the .bss pseudo-op to the Z80 assembler.Nick Clifton1-0/+10
PR 27047 * config/tc-z80.c (s_bss): New function. (md_pseudo_table): Add bss entry.
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+33
https://github.com/riscv/riscv-asm-manual/pull/61 We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h and zext.w. In a certain sense, zext.b is not a pseudo - It is an alias of andi. Similarly, sext.b and sext.h are aliases of other rvb instructions, when we enable b extension; But they are pseudos when we just enable rvi. However, this patch does not consider the rvb cases. Besides, zext.w is only valid in rv64. gas/ * config/tc-riscv.c (riscv_ext): New function. Use md_assemblef to expand the zext and sext pseudos, to give them a chance to be expanded into c-ext instructions. (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH. * testsuite/gas/riscv/ext.s: New testcase. * testsuite/gas/riscv/ext-32.d: Likewise. * testsuite/gas/riscv/ext-64.d: Likewise. include/ * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added. opcodes/ * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-4/+10
bfd/ * elfxx-riscv.c (riscv_ext_dont_care_version): New function. Return TRUE if we don't care the versions of the extensions. These extensions are added to the subset list for special purposes, with the explicit versions or the RISCV_UNKNOWN_VERSION versions. (riscv_parse_add_subset): If we do care the versions of the extension, and the versions are unknown, then report errors for the non-implicit extensions, and return directly for the implicit one. (riscv_arch_str1): Do not output i extension after e, and the extensions which versions are unknown. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. * testsuite/gas/riscv/march-imply-i.s: New testcase. * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version of i is less than 2.1, and zi* are supported in the chosen spec, so enable the fence.i and csr instructions, also output the implicit zi* to the arch string. * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are not supported in the spec 2.2. Enable the related instructions since i's version is less than 2.1, but do not output them. * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version of i is 2.1, so don't add it's implicit zi*, and disable the related instructions. * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise. * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi* explicitly, so enable the related instructions. * testsuite/gas/riscv/march-imply-i2p0.d: Removed. * testsuite/gas/riscv/march-imply-i2p1.d: Removed. include/ * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. opcodes/ * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by zifencei and zicsr.
2020-12-08gas: Generate a new section for SHF_GNU_RETAINH.J. Lu2-18/+20
For .globl foo2 .section .data.foo,"aR" .align 4 .type foo2, @object .size foo2, 4 foo2: .long 2 .globl foo1 .section .data.foo .align 4 .type foo1, @object .size foo1, 4 foo1: .long 1 generate a new section if the SHF_GNU_RETAIN bit doesn't match. * config/obj-elf.c (SEC_ASSEMBLER_SHF_MASK): New. (get_section_by_match): Also check if SEC_ASSEMBLER_SHF_MASK of sh_flags matches. Rename info to sh_info. (obj_elf_change_section): Don't check previous SHF_GNU_RETAIN. Rename info to sh_info. (obj_elf_section): Rename info to sh_info. Set sh_flags for SHF_GNU_RETAIN. * config/obj-elf.h (elf_section_match): Rename info to sh_info. Add sh_flags. * testsuite/gas/elf/elf.exp: Run section27. * testsuite/gas/elf/section24b.d: Updated. * testsuite/gas/elf/section27.d: New file. * testsuite/gas/elf/section27.s: Likewise.
2020-12-01RISC-V: Support to add implicit extensions.Nelson Chu1-1/+3
We have to parse and add all arch string extensions at first, and then start to add their implicit extensions. That means we can always add arch string extensions at the end of the subset list, but we need to search the right place to add their implicit extensions. For now we follow the following rules to add the implicit extensions, * Add zicsr and zifencei only when the i's version less than 2.1. * Add d, f and zicsr when q is found. * Add f and zicsr when d is found. * Add zicsr when f is found. Besides, we do not add the implicit extensions if they are already added in the subset list, or we cannot find their default versions according to the chosen ISA spec. bfd/ * elfnn-riscv.c (riscv_merge_std_ext): Updated since riscv_lookup_subset is changed. * elfxx-riscv.c (riscv_ext_order): New Array used to compare the extensions' order quickly. (riscv_init_ext_order): New function. Init the riscv_ext_order according to the riscv_supported_std_ext and parse_config[i].class automatically. (riscv_compare_subsets): New function. Similar to the strcmp, but compare the subsets with the specific order. (riscv_lookup_subset): Return TRUE and set `current` to the subset if it is found. Otherwise, return FALSE and set `current` to the place where we should insert the subset. (riscv_add_implicit_subset): New function. Search the list first, and then find the right place to add the implicit_subset. (riscv_parse_add_subset): Since We have to add all arch string extensions first, and then start to add their implicit extensions. We can add arch string extensions in order by the original riscv_add_subset, and then add the implicit subsets by the riscv_add_implicit_subset. Besides, do not add the implicit extensions if we failed to find their default versions. (riscv_parse_std_ext): Updated. (riscv_parse_add_implicit_subsets): New function. Add all implicit extensions according to the arch string extensions. (riscv_parse_subset): Call riscv_init_ext_order and riscv_parse_add_implicit_subsets, before and after parsing the arch string. Remove parts of the ISA conflict checking since the implicit extensions are added. * elfxx-riscv.h (riscv_lookup_subset): Updated. gas/ * config/tc-riscv.c (riscv_subset_supports): Updated. * testsuite/gas/riscv/march-imply-i2p0.d: New testcase. Need to add the implicit zicsr and zifencei when i's version less than 2.1. * testsuite/gas/riscv/march-imply-i2p1.d: New testcase. * testsuite/gas/riscv/march-imply-d.d: Likewise. * testsuite/gas/riscv/march-imply-f.d: Likewise. * testsuite/gas/riscv/march-imply-q.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iq.l: Updated. * testsuite/gas/riscv/march-fail-rv32id.d: Removed. * testsuite/gas/riscv/march-fail-rv32id.l: Likewise. * testsuite/gas/riscv/march-fail-rv64iq.d: Likewise. * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
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