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AgeCommit message (Expand)AuthorFilesLines
2016-12-02[ARC] Sync cpu names with the ones accepted by GCC.Claudiu Zissulescu1-22/+85
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-15/+20
2016-11-27Fix spelling in comments in .l files (gas)Ambrogino Modigliani1-1/+1
2016-11-27Fix spelling in comments in C source files (gas)Ambrogino Modigliani34-67/+67
2016-11-25gas: fix CBCOND diagnostics for invalid immediate operands.Jose E. Marchesi1-2/+3
2016-11-23RISCV/GAS Add missing break in md_apply_fix.Kuan-Lin Chen1-0/+1
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi1-58/+54
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra1-18/+2
2016-11-21[GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL s...Renlin Li1-2/+5
2016-11-18[ARC] Fix and extend features of .cpu directive.Claudiu Zissulescu1-18/+59
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+3
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+21
2016-11-15Fix SPARC relocations generated for the .eh_frame section.Nick Clifton1-1/+4
2016-11-13Assemble 'bad' moxie instructionAnthony Green1-0/+7
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+2
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+1
2016-11-11[AArch64] Fix feature dependencies for +simd and +cryptoSzabolcs Nagy1-2/+2
2016-11-04arc/nps400: Validate address type operands correctlyAndrew Burgess1-3/+16
2016-11-04S/390: Fix 16 bit pc relative relocs.Andreas Krebbel1-4/+20
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme1-0/+2
2016-11-04Add support for ARM Cortex-M23 processorThomas Preud'homme1-0/+2
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess1-125/+30
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall1-2/+4
2016-11-03gas/arc: Replace short_insn flag with insn length fieldGraham Markall1-45/+18
2016-11-04New option falkor for Qualcomm server partSiddhesh Poyarekar2-0/+6
2016-11-03[ARM] Allow MOV/MOV.W to accept all possible immediatesJiong Wang1-16/+69
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+3
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+22
2016-11-01Add support for RISC-V architecture.Nick Clifton2-0/+2509
2016-10-27gas/arc: Don't rely on bfd list of cpu type for cpu selectionAndrew Burgess1-91/+100
2016-10-26Revert "bison warning fixes"Alan Modra2-2/+2
2016-10-21X86: Remove pcommit instructionH.J. Lu1-2/+0
2016-10-19[GAS][ARM]Generate unpredictable warning for pc used in data processing instr...Renlin Li1-0/+15
2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu1-2/+1
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra32-16/+140
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra8-10/+15
2016-10-06bison warning fixesAlan Modra2-2/+2
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra1-1/+3
2016-09-26tc-xtensa.c: fixup xg_reverse_shift_count typoTrevor Saunders1-1/+1
2016-09-26PowerPC .gnu.attributesAlan Modra1-0/+24
2016-09-22Remove legacy basepri_mask MRS/MSR special regThomas Preud'homme1-1/+0
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford1-1/+1
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford1-4/+4
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-25/+33
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-1/+16
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-3/+38
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+27
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-15/+59
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-23/+222
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