| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-10-10 | x86: fold Size{16,32,64} template attributes | Jan Beulich | 1 | -6/+6 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 1 | -0/+2 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -0/+52 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 1 | -0/+2 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -0/+17 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -0/+2 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 1 | -0/+1 |
| 2018-10-05 | [Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 | Sudakshina Das | 1 | -0/+13 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 1 | -0/+12 |
| 2018-10-05 | [Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 | Sudakshina Das | 1 | -0/+2 |
| 2018-10-05 | or1k: Add the l.adrp insn and supporting relocations | Stafford Horne | 1 | -0/+6 |
| 2018-10-03 | AArch64: Close sequences at the end of sections | Tamar Christina | 2 | -0/+21 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 1 | -2/+4 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 2 | -8/+23 |
| 2018-09-25 | S/390: Fix symbolic displacement in lay | Andreas Krebbel | 1 | -1/+1 |
| 2018-09-20 | S12Z/GAS: Correct a signed vs unsigned comparison error with GCC 4.1 | Maciej W. Rozycki | 1 | -11/+13 |
| 2018-09-20 | PPC/GAS: Correct a signed vs unsigned comparison error with GCC 4.1 | Maciej W. Rozycki | 1 | -1/+1 |
| 2018-09-20 | ARC: Fix build errors with large constants and C89 | Maciej W. Rozycki | 1 | -2/+2 |
| 2018-09-20 | Andes Technology has good news for you, we plan to update the nds32 port of b... | Nick Clifton | 2 | -1626/+2847 |
| 2018-09-18 | Fix Aarch64 bug in warning filtering. | Tamar Christina | 1 | -1/+1 |
| 2018-09-17 | x86: Add -mvexwig=[0|1] option to assembler | H.J. Lu | 1 | -11/+34 |
| 2018-09-14 | x86: Support VEX/EVEX WIG encoding | H.J. Lu | 1 | -17/+14 |
| 2018-09-14 | csky: Support PC relative diff relocation | Lifang Xia | 2 | -0/+9 |
| 2018-09-14 | x86: fold CRC32 templates | Jan Beulich | 1 | -11/+7 |
| 2018-09-13 | x86: Swap destination/source to encode VEX only if possible | H.J. Lu | 1 | -3/+4 |
| 2018-09-13 | x86: also allow D on 3-operand insns | Jan Beulich | 1 | -19/+22 |
| 2018-09-13 | x86: use D attribute also for SIMD templates | Jan Beulich | 1 | -9/+25 |
| 2018-09-13 | x86: improve operand reversal | Jan Beulich | 1 | -7/+33 |
| 2018-09-13 | x86: add code comment on deprecated status of pseudo-suffixes | Jan Beulich | 1 | -1/+2 |
| 2018-09-06 | PR23570, AVR .noinit section defaults to PROGBITS | Alan Modra | 1 | -19/+0 |
| 2018-09-04 | gas, sparc: Allow non-fpop2 instructions before floating point branches | Daniel Cederman | 1 | -5/+6 |
| 2018-09-03 | Change the .section directive for the AVR assembler so that the .noinit secti... | Nick Clifton | 1 | -0/+19 |
| 2018-08-31 | PowerPC64 higher REL16 relocations | Alan Modra | 2 | -13/+43 |
| 2018-08-31 | x86: Extend assembler to generate GNU property notes | H.J. Lu | 2 | -12/+296 |
| 2018-08-30 | RISC-V: Allow instruction require more than one extension | Jim Wilson | 1 | -11/+21 |
| 2018-08-29 | [MIPS] Add Loongson 2K1000 proccessor support. | Chenghua Xu | 1 | -1/+4 |
| 2018-08-29 | [MIPS] Add Loongson 3A2000/3A3000 proccessor support. | Chenghua Xu | 1 | -1/+4 |
| 2018-08-29 | [MIPS] Add Loongson 3A1000 proccessor support. | Chenghua Xu | 1 | -2/+5 |
| 2018-08-29 | [MIPS/GAS] Add Loongson EXT2 Instructions support. | Chenghua Xu | 1 | -1/+16 |
| 2018-08-29 | [MIPS/GAS] Split Loongson EXT Instructions from loongson3a. | Chenghua Xu | 1 | -2/+16 |
| 2018-08-29 | [MIPS/GAS] Split Loongson CAM Instructions from loongson3a | Chenghua Xu | 1 | -2/+17 |
| 2018-08-23 | RISC-V: Reject empty rouding mode and fence operand. | Jim Wilson | 1 | -0/+3 |
| 2018-08-21 | Fix handling of undocumented SLL instruction for the Z80 target. | Arnold Metselaar | 1 | -13/+29 |
| 2018-08-21 | Use operand->extract to provide defaults for optional PowerPC operands | Alan Modra | 1 | -78/+74 |
| 2018-08-18 | S12Z: Move opcode header to public include directory. | John Darrington | 1 | -1/+1 |
| 2018-08-11 | x86: Add CpuCMOV and CpuFXSR | H.J. Lu | 1 | -0/+6 |
| 2018-08-10 | x86: Don't display --32/--64/--x32 without BFD64 | H.J. Lu | 1 | -2/+2 |
| 2018-08-09 | x86: Display default x86-specific options for "as --help" | H.J. Lu | 1 | -12/+27 |
| 2018-08-07 | Correct the parsing of derferred register addressing in the PDP11 assembler. | James Patrick Conlon | 1 | -5/+13 |
| 2018-08-06 | [ARC] Check if an input asm file is rf16 compliant | claziss | 1 | -0/+25 |
