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2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu1-2/+1
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra32-16/+140
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra8-10/+15
2016-10-06bison warning fixesAlan Modra2-2/+2
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra1-1/+3
2016-09-26tc-xtensa.c: fixup xg_reverse_shift_count typoTrevor Saunders1-1/+1
2016-09-26PowerPC .gnu.attributesAlan Modra1-0/+24
2016-09-22Remove legacy basepri_mask MRS/MSR special regThomas Preud'homme1-1/+0
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford1-1/+1
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford1-4/+4
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-25/+33
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-1/+16
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-3/+38
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+27
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-15/+59
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-23/+222
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-1/+41
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+64
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-4/+52
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-31/+130
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-4/+1
2016-09-21[AArch64][SVE 12/32] Remove boolean parameters from parse_address_mainRichard Sandiford1-24/+21
2016-09-21[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interfaceRichard Sandiford1-106/+108
2016-09-21[AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_floatRichard Sandiford1-8/+6
2016-09-21[AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford1-6/+14
2016-09-21[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovableRichard Sandiford1-33/+29
2016-09-21[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_VRichard Sandiford1-22/+31
2016-09-21[AArch64][SVE 06/32] Generalise parse_neon_reg_listRichard Sandiford1-5/+8
2016-09-21[AArch64][SVE 05/32] Rename parse_neon_type_for_operandRichard Sandiford1-2/+2
2016-09-21[AArch64][SVE 04/32] Rename neon_type_el to vector_type_elRichard Sandiford1-16/+16
2016-09-21[AArch64][SVE 03/32] Rename neon_el_type to vector_el_typeRichard Sandiford1-4/+4
2016-09-21[AArch64][SVE 01/32] Remove parse_neon_operand_typeRichard Sandiford1-27/+4
2016-09-14gas: improve architecture mismatch diagnostics in sparcJose E. Marchesi1-1/+1
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi1-11/+45
2016-09-14[ARC] Fix parsing dtpoff relocation expression.Claudiu Zissulescu1-1/+1
2016-09-12S/390: Add alternate processor names.Andreas Krebbel1-13/+31
2016-09-12S/390: Fix facility bit default.Andreas Krebbel1-1/+4
2016-09-08Allow PROCESSOR_IAMCU for Intel MCUH.J. Lu1-1/+1
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu1-21/+2
2016-09-07[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.Richard Earnshaw1-9/+9
2016-08-31PowerPC VLE sh_flags and p_flagsAlan Modra1-5/+9
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme1-18/+27
2016-08-25Remove _S version of ARM MSR/MRS special registersThomas Preud'homme1-2/+2
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+2
2016-08-19ARM: Issue a warning when the MRRC and MRRC2 instructions are used with the s...Tamar Christina1-0/+8
2016-08-11[AArch64] Reject -0.0 as an 8-bit FP immediateRichard Sandiford1-1/+1
2016-08-05Ensure ARM VPUSH and VPOP instructions do not affect more than 16 registers.Nick Clifton2-37/+53
2016-08-05Fix the generation of alignment frags in code sections for AArch64.Nick Clifton1-3/+7
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