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2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-3/+17
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-0/+6
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-0/+2
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das1-0/+2
2018-11-09S/390: Fix optional operand handling after memory addressesAndreas Krebbel1-24/+23
2018-11-09PowerPC, don't use bfd reloc howto in md_assembleAlan Modra1-11/+249
2018-11-07rx: Add target rx-*-linux.Yoshinori Sato1-0/+4
2018-11-06[arm] Check for neon and condition in vcvt.f16.f32Matthew Malcomson1-0/+2
2018-11-06PowerPC instruction mask checksAlan Modra1-14/+23
2018-11-06PowerPC instruction operand flag validationAlan Modra1-0/+9
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-2/+2
2018-11-05x86: Disable GOT relaxation with data prefixH.J. Lu1-6/+7
2018-10-29Move struc-symbol.h to symbols.cAlan Modra20-116/+75
2018-10-28PR23837, Segmentation fault in resolve_symbol_valueAlan Modra1-2/+1
2018-10-23S/390: Support vector alignment hintsAndreas Krebbel1-0/+15
2018-10-23S12Z: Handle 16 bit fixups which are constant.John Darrington1-0/+3
2018-10-22Apply alpha BFD_RELOC_8 fixupsAlan Modra1-0/+6
2018-10-20PR23800, .eqv doesn't always defer expression evaluationAlan Modra1-1/+16
2018-10-19This set of changes clarifies the conditions for the R5900 short loop fix and...Fredrik Noring1-5/+17
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-6/+6
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-0/+52
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+17
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das1-0/+1
2018-10-05[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32Sudakshina Das1-0/+13
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das1-0/+12
2018-10-05[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32Sudakshina Das1-0/+2
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-0/+6
2018-10-03AArch64: Close sequences at the end of sectionsTamar Christina2-0/+21
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina1-2/+4
2018-10-03AArch64: Wire through instr_sequenceTamar Christina2-8/+23
2018-09-25S/390: Fix symbolic displacement in layAndreas Krebbel1-1/+1
2018-09-20S12Z/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki1-11/+13
2018-09-20PPC/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki1-1/+1
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki1-2/+2
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton2-1626/+2847
2018-09-18Fix Aarch64 bug in warning filtering.Tamar Christina1-1/+1
2018-09-17x86: Add -mvexwig=[0|1] option to assemblerH.J. Lu1-11/+34
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-17/+14
2018-09-14csky: Support PC relative diff relocationLifang Xia2-0/+9
2018-09-14x86: fold CRC32 templatesJan Beulich1-11/+7
2018-09-13x86: Swap destination/source to encode VEX only if possibleH.J. Lu1-3/+4
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-19/+22
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-9/+25
2018-09-13x86: improve operand reversalJan Beulich1-7/+33
2018-09-13x86: add code comment on deprecated status of pseudo-suffixesJan Beulich1-1/+2
2018-09-06PR23570, AVR .noinit section defaults to PROGBITSAlan Modra1-19/+0
2018-09-04gas, sparc: Allow non-fpop2 instructions before floating point branchesDaniel Cederman1-5/+6