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AgeCommit message (Expand)AuthorFilesLines
2018-07-22x86: Determine vector length from the last vector operandH.J. Lu1-10/+25
2018-07-21gas/config/tc-i386.c: Break long lineH.J. Lu1-4/+6
2018-07-20x86: Rename match_reg_size to match_operand_sizeH.J. Lu1-11/+12
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu1-2/+16
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich1-1/+19
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-2/+43
2018-07-16x86: fix operand size checkingJan Beulich1-54/+61
2018-07-13Allow bit-patterns in the immediate field of ARM neon mov instructions.Nick Clifton1-4/+15
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das1-0/+2
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich1-7/+2
2018-07-11x86: simplify legacy prefix emissionJan Beulich1-10/+4
2018-07-11x86: fix "REP RET" with -madd-bnd-prefixJan Beulich1-4/+10
2018-07-02microMIPS/GAS: Handle several percent-ops with macrosMaciej W. Rozycki1-1/+20
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme1-42/+42
2018-06-29RISC-V: Add gas support for "fp" register.Jim Wilson1-0/+3
2018-06-29[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases.Ramana Radhakrishnan1-0/+16
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+2
2018-06-26Fix the MSP430 assembler's parsing of register names.Nick Clifton1-8/+18
2018-06-20Change the ARM assembler's ADR and ADRl pseudo-ops so that they will only set...Nick Clifton1-4/+6
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber1-0/+11
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-0/+14
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+14
2018-06-11MIPS/GAS: Correct `-O0' and `-O' option help, add `-O1' and `-O2'Maciej W. Rozycki1-2/+3
2018-06-08[arm][gas] Add support for Arm Cortex-A76kyrtka011-0/+3
2018-06-08[AArch64][gas] Add support for Arm Cortex-A76kyrtka011-0/+3
2018-06-07Fix AArch64 unintialized variable which can cause diagnostic failures.Tamar Christina1-0/+2
2018-06-06Update the AArch64 assembler to note that the Qualcomm Saphira cpu supports A...Sameera Deshpande1-1/+1
2018-06-04xtensa: add separate property sections optionMax Filippov1-1/+21
2018-06-01x86: relax redundant REX prefix checkJan Beulich1-2/+3
2018-06-01x86: simplify control register checkJan Beulich1-5/+2
2018-06-01x86: tighten condition for emitting LOCK on control register accessesJan Beulich1-4/+3
2018-05-30Add znver2 support.Amit Pawar1-0/+2
2018-05-24RISC-V: Fix .align handling when .option norelax.Jim Wilson2-10/+22
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner1-14/+2
2018-05-18RISC-V: Add RV32E support.Jim Wilson1-10/+56
2018-05-18Add support for the Freescale s12z processor.John Darrington2-0/+3945
2018-05-16NDS32/GAS: Correct an `expr' global shadowing error for pre-4.8 GCCMaciej W. Rozycki1-2/+2
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-51/+81
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-10/+19
2018-05-12score gcc-8 warning fixesAlan Modra1-70/+66
2018-05-10Allow integer immediates for AArch64 fmov instructions.Tamar Christina1-21/+4
2018-05-10Allow integer immediate for VFP vmov instructions.Tamar Christina1-0/+8
2018-05-09gas: xtensa: fix literal movementMax Filippov1-21/+30
2018-05-09Fix binary compatibility between GCC and the TI compiler for the PRU target.Dimitar Dimitrov1-5/+13
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+41
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu1-3/+7
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner1-38/+26
2018-05-04-Wstringop-truncation warningsAlan Modra2-9/+11
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-40/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+40
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