Age | Commit message (Collapse) | Author | Files | Lines |
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symbols to the position of the debugging information.
PR 10668.
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sets a condition code with an instruction which uses a condition
code.
(mips_ip): In cases 'N' and 'M', look for $fccN rather than an
immediate value.
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mips_cpu is 5000, set interlocks and cop_interlocks.
(mips_ip): Give a better error message if the ISA level is wrong.
(md_parse_option): Recognize -mcpu=[v][r]5000.
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* config/tc-mips.c (COUNT_TOP_ZEROES): Added macro to count
leading zeroes.
(load_register): Ensure hi32 bits are not lost during lo32bit
processing. Fix shift offset that was overflowing into the next
instruction field. Add code to generate shorter sequences for
constants with a single contiguous seqeuence of ones.
Fri Sep 6 18:23:54 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/mips/dli.{s,d}: More test cases added.
NOTE: The COUNT_TOP_ZEROES macro is a bit bulky, and the same result
can be achieved by using a "standard" ffs() routine:
count = ffs(~v);
count = count == 0 ? 0 : 33 - count;
However the following timings (VR4300 CPU clock ticks on a CMA101
board) show the performance gain.
Number of ffs() for loop if/then/else conditional
leading ?:
zeroes
-------------------------------------------------------------------------------
0 167 179 266 251
1 1718 283 263 259
2 1670 379 287 295
3 1622 475 311 311
4 1574 571 295 287
5 1534 667 311 319
6 1478 763 307 299
7 1430 859 323 323
8 1382 962 287 295
9 1334 1051 319 311
10 1286 1154 299 307
11 1238 1250 323 331
12 1183 1346 299 307
13 1135 1442 331 323
14 1087 1546 311 319
15 1039 1642 335 343
16 991 1730 295 287
17 950 1834 311 319
18 895 1922 307 299
19 847 2026 331 323
20 799 2122 307 299
21 751 2218 323 323
22 703 2314 311 311
23 655 2417 343 335
24 599 2506 307 299
25 559 2602 331 331
26 511 2705 311 319
27 463 2801 343 335
28 407 2897 311 319
29 367 2993 343 335
30 311 3097 323 331
31 271 3185 355 355
32 215 3233 379 371
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* configure: Regenerated.
* config/te-sparcaout.h: New file.
* config/tc-sparc.h (TARGET_BYTES_BIG_ENDIAN): Define.
Ifdef TE_SPARCOUT define TARGET_FORMAT and SPARC_BIENDIAN.
* config/tc-sparc.c (INSN_BIG_ENDIAN): New macro.
(SPECIAL_CASE_{SETSW,SETX}): Define.
({NOP,OR,FMOVS,SETHI,SLLX,SRA}_INSN): Define.
(md_begin): Delete setting of `target_big_endian'.
(output_insn): New function.
(md_assemble): Rewrite. Add `setx' support.
(sparc_ip): Handle `0' operand char. Recognize setuw, setsw, setx
special cases.
(md_atof): Add little endian support.
(md_number_to_chars): Likewise.
(md_apply_fix): Likewise.
(md_longopts): Recognize -EL,-EB ifdef SPARC_BIENDIAN.
(md_parse_option): Likewise.
(md_show_usage): Print -EL, -EB ifdef SPARC_BIENDIAN.
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* config/tc-mips.c (load_register): Remove unnecessary code that
was causing the high 32bits of 64bit constants to be lost.
Fixes PR10503. The compiler was producing the assembler code:
dli $3,0xfffffffffffff
when constructing the softfloat library. Unfortunately it was being
incorrectly assembled.
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word fixups too.
Fixes "difference between forward references".
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routines to fetch/store the updated instruction from/to memory.
(v850_insert_operand): If the operand has a specialized insert
routine, call it.
Getting fixups closer. At least br <target> works now.
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be like identical function found in tc-ppc.c.
(get_reloc): Removed.
(v850_reloc_prefix): New function, parse lo(), hi() and hi0().
(md_assemble): emit fixups.
(md_pcrel_from): renamed from md_pcrel_from_section, emit proper
displacement.
(md_apply_fix3): handle fixups/relocs.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
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hi0() too.
Bugfix.
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* tc-d10v.c: Fixed ".word". Fixed problem with range checking
on addresses. Improved error messages.
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* tc-d10v.c (parallel_ok): Fix bug in parallel
checking code.
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"ep" or "r30" in sst and sld instructions.
(md_apply_fix3): Don't abort. Just warn that we don't
have relocs yet.
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(cc_name): New function.
(md_assemble): Handle V850_OPERAND_CC correctly.
setf stuff
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"insn"!
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any given register table.
(register_name): Pass appropriate table and size to reg_name_search.
(system_register_name): New function.
(SYSREG_NAME_CNT): Define.
(md_assemble): Handle operands which are system registers.
Still working on the parser..
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opcode doesn't want a register, then we don't have a match.
(md_assemble): Get size of the instruction from the opcode table.
So we choose the right opcode and so that we get the sizes right.
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* config/tc-v850.h: New file.
* configure (v850-*-elf): New target.
* configure.in (v850-*-elf): New target.
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* tc-d10v.c: All references to defined symbols should
now use the optimal instruction. .float and .double now work.
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Add support for openVMS/Alpha.
* as.h (PRINTF_LIKE): Don't define if VMS, for now.
* config/obj-evax.c: New file.
* config/obj-evax.h: New file.
* config/tc-alpha.c: Add support for EVAX format if OBJ_EVAX is
defined.
* config/tc-alpha.h: Add support for EVAX format if OBJ_EVAX is
defined. Add case for bfd_target_evax_flavour.
* config/vms-a-conf.h: New file.
* conf-a-gas.com: New file.
* configure.in: Add target alpha-*-*vms*.
* configure: Rebuild.
* makefile.vms: New file.
* read.c (s_lcomm): Align bss_seg on 8 byte boundary if OBJ_EVAX.
Don't call ffs on openVMS/Alpha.
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not to more than a 16 byte boundary.
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#ifndef OBJ_ELF lines. From Eric Valette <valette@crf.canon.fr>.
(tc_gen_reloc): If out of memory call as_fatal rather than
assert. If no howto found, call as_bad_where rather than
as_fatal. Change the error message slightly. Set howto to a
non-NULL value in order to keep going.
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* tc-d10v.c: Added code to support 32-bit fixups for stabs.
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OBJ_ELF.
PR 10181.
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* tc-d10v.c: Disable range checking on 16-bit values.
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* tc-d10v.c: Fixed bugs in short relocs and range checking.
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* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
pre-cursor to adding Thumb support. Also added cpu_variant flag
information to each of the asm_flg structures.
(md_parse_option): Updated ARM7 parsing to allow 't' for
thumb/halfword support, aswell as 'm' for long multiply.
(md_show_usage): Updated help message.
(md_assemble): Check that instruction flags are applicated to the
current cpu variant.
(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
signextension instructions.
(do_ldst): Generate halfword and signextension variants if
mnemonic flags match.
(ldst_extend): Do not allow shifts in the offset field of halfword
or signextension instructions.
(validate_offset_imm): Provide check on halfword and signextension
immediate range.
(add_to_lit_pool): Merge identical literal pool values.
Wed Jul 31 15:55:12 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/arm7t.s: Added.
* gas/arm/arm7t.d: Added.
* gas/arm/arm.exp: Updated to run the new test.
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(cons_fix_new_hppa): Don't coke on e_esel.
(tc_gen_reloc, SOM version): Handle R_COMP2 when used
to help generate exception handling tables.
(md_apply_fix): Don't try to apply fixups with an e_esel
selector.
(hppa_fix_adjustable): Fixups with e_esel selectors
are not adjustable.
Another stab at EH on the PA.
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* tc-d10v.c: Added lots of error checking. Added hacks
to support accumulator shifts.
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* tc-d10v.c (md_assemble): Now handles multiline
instructions.
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* tc-d10v.c: Fix packaging bug. Added range checking.
Added kludge for divs instruction. Fixed minor problem with
multiple text sections.
* tc-d10v.h (d10v_cleanup): Change prototype.
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Tue Jul 23 10:49:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c (md_apply_fix3): Fix all instruction
addresses to be right-shifted by 2.
end-sanitize-d10v
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Mon Jul 22 11:32:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: Many changes to get relocs working.
(register_name): No longer creates a symbol for register names.
(pre_defined_registers): moved to opcodes/d10v-opc.c.
(d10v_insert_operand): Now works correctly for either container.
* config/tc-d10v.h (d10v_cleanup): Declare.
end-sanitize-d10v
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BFD_RELOC_PCREL_LO16 are expected to be PC relative.
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* tc-alpha.c: Patches to track current minimum alignment to reduce
the number of fragments created with frag_align.
(alpha_current_align): New static variable.
(s_alpha_text): Reset alignment to 0.
(s_alpha_data, s_alpha_rdata, s_alpha_sdata): Likewise.
(s_alpha_stringer, s_alpha_space): New functions.
(s_alpha_cons, alpha_flush_pending_output): Remove functions.
(alpha_cons_align): New function to replace both of them.
(emit_insn): Only align if alpha_current_align is less than 2;
reset alpha_current_align to 2.
(s_alpha_gprel32): Likewise.
(s_alpha_section): New function. Basically duplicate the other
alpha section change hooks. Only define for ELF.
(s_alpha_float_cons): Simplify alignment handling.
(md_pseudo_table): Only define "rdata" and "sdata" if OBJ_ECOFF.
If OBJ_ELF, define "section", "section.s", "sect", and "sect.s".
Don't define the s_alpha_cons pseudo-ops. Do define
s_alpha_stringer and s_alpha_space pseudo-ops.
(alpha_align): Skip if less than current default alignment. Set
default alignment.
* tc-alpha.h (md_flush_pending_output): Remove.
(md_cons_align): Add.
* tc-alpha.c: Add oodles of function description comments.
(md_bignum_to_chars): Remove; there are no callers.
(md_show_usage): Mention some more variants.
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uaxword to use s_uacons.
(sparc_no_align_cons): New static variable.
(s_uacons): New static function.
(sparc_cons_align): If sparc_no_align_cons is set, just clear it
and return.
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allocating space for the unsupported architecture error message.
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Wed Jul 17 14:25:13 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: New file.
* config/tc-d10v.h: New file.
* configure (d10v-*-elf): New target.
* configure.in (d10v-*-elf): New target.
end-sanitize-d10v
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* config/tc-alpha.c (alpha_align): Change fill parameter
to a pointer. Take NULL as 0 or nop depending on section. Change
all callers.
(s_alpha_align): Rename local variables.
* doc/as.texinfo (.align): Document action of omitted
fill parameter.
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when an unsupported PC relative reloc is seen, rather than calling
abort.
PR 10073.
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OBJ_MAYBE_ELF.
(tc_gen_reloc): If fixup was changed to be PC relative, change
reloc type accordingly. Use name of reloc in error message.
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if fx_pcrel is set. Correct setting the addend case in the
OBJ_ELF case (from Andreas Schwab
<schwab@issan.informatik.uni-dortmund.de>).
(md_show_usage): Correct -mfc5200 to -m5200.
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scale factor.
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