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2020-03-20Add support for the xdef and xref pseudo-ops to the Z80 assembler.Sergey Belyashov1-0/+2
2020-03-17Fix a small set of Z80 problems.Sergey Belyashov2-59/+75
2020-03-13gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVEAndre Vieira1-3/+12
2020-03-11i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]H.J. Lu1-1/+365
2020-03-10More 1 << 31 signed overflowsAlan Modra5-9/+9
2020-03-06Add support for a ".file 0" directive if supporting DWARF 5 or higher.Nick Clifton1-1/+1
2020-03-06Add support for --dwarf-[3|4|5] to assembler command line.Nick Clifton1-2/+1
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich1-5/+15
2020-03-06x86: drop/replace IgnoreSizeJan Beulich1-5/+9
2020-03-06x86: fold (supposed to be) identical codeJan Beulich1-27/+14
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich1-0/+1
2020-03-06x86: drop Rex64 attributeJan Beulich1-3/+5
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich1-0/+15
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich1-4/+7
2020-03-04RISC-V: Support assembler modifier %got_pcrel_hi.Nelson Chu1-0/+1
2020-03-04Generate a warning in the ARM assembler if a PC-relative thumb load instructi...Alexandre Oliva1-0/+3
2020-03-04x86: support VMGEXITJan Beulich1-0/+2
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-13/+15
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov1-2/+2
2020-03-03x86: Improve -malign-branchHongtao Liu2-32/+135
2020-03-03Fix a potential illegal memory access in the Z80 assembler.Sergey Belyashov1-8/+24
2020-03-03Tidy obj-coff.hAlan Modra1-14/+0
2020-03-02miscellaneous SEC_SMALL_DATAAlan Modra4-55/+22
2020-02-28MIPS/fix_loongson3_llsc: fix when target has multi labelsYunQiang Su1-5/+44
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson1-24/+6
2020-02-26gas gettext warningAlan Modra1-1/+1
2020-02-26Indent labelsAlan Modra18-59/+59
2020-02-20RISC-V: Support the read-only CSR checking.Nelson Chu1-0/+69
2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu1-1/+21
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu1-7/+92
2020-02-21pdp11 reloc processingAlan Modra1-13/+17
2020-02-21PR25569, PDP11 ld -s clobbers last data byteAlan Modra1-20/+28
2020-02-19Various fixes for the Z80 support.Sergey Belyashov1-108/+115
2020-02-19x86: Mark cvtpi2ps and cvtpi2pd as MMXH.J. Lu1-1/+3
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-0/+2
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich1-48/+65
2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich1-4/+6
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich1-40/+37
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-1/+4
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich1-19/+49
2020-02-14x86: adjust segment override prefix emissionJan Beulich1-5/+7
2020-02-14x86: optimize away pointless segment overridesJan Beulich1-2/+9
2020-02-14x86: extend LEA's segment override warningJan Beulich1-3/+4
2020-02-13x86: Resolve PLT32 reloc aganst local symbol to sectionH.J. Lu1-2/+0
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich1-1/+1
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich1-3/+60
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich2-3/+5
2020-02-12x86: also disallow non-byte/-word registers with byte/word suffixJan Beulich1-45/+8
2020-02-12x86/Intel: improve diagnosticsJan Beulich1-4/+5
2020-02-11x86: drop ShortForm attributeJan Beulich1-3/+9
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