| Age | Commit message (Collapse) | Author | Files | Lines |
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2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
* configure.in (AC_CHECK_HEADERS): Add limits.h.
* configure: Regenerated.
* config.in: Likewise.
* config/tc-i386.c: Include "opcodes/i386-init.h".
(_i386_insn): Use i386_operand_type for types.
(cpu_arch_flags): Updated to new types with bitfield.
(cpu_arch_tune_flags): Likewise.
(cpu_arch_isa_flags): Likewise.
(cpu_arch): Likewise.
(i386_align_code): Likewise.
(set_code_flag): Likewise.
(set_16bit_gcc_code_flag): Likewise.
(set_cpu_arch): Likewise.
(md_assemble): Likewise.
(parse_insn): Likewise.
(process_operands): Likewise.
(output_branch): Likewise.
(output_jump): Likewise.
(parse_real_register): Likewise.
(mode_from_disp_size): Likewise.
(smallest_imm_type): Likewise.
(pi): Likewise.
(type_names): Likewise.
(pt): Likewise.
(pte): Likewise.
(swap_2_operands): Likewise.
(optimize_imm): Likewise.
(optimize_disp): Likewise.
(match_template): Likewise.
(check_string): Likewise.
(process_suffix): Likewise.
(check_byte_reg): Likewise.
(check_long_reg): Likewise.
(check_qword_reg): Likewise.
(check_word_reg): Likewise.
(finalize_imm): Likewise.
(build_modrm_byte): Likewise.
(output_insn): Likewise.
(disp_size): Likewise.
(imm_size): Likewise.
(output_disp): Likewise.
(output_imm): Likewise.
(gotrel): Likewise.
(i386_immediate): Likewise.
(i386_displacement): Likewise.
(i386_index_check): Likewise.
(i386_operand): Likewise.
(parse_real_register): Likewise.
(i386_intel_operand): Likewise.
(intel_e09): Likewise.
(intel_bracket_expr): Likewise.
(intel_e11): Likewise.
(cpu_arch_flags_not): New.
(cpu_flags_check_x64): Likewise.
(cpu_flags_all_zero): Likewise.
(cpu_flags_not): Likewise.
(i386_cpu_flags_biop): Likewise.
(cpu_flags_biop): Likewise.
(cpu_flags_match); Likewise.
(acc32): New.
(acc64): Likewise.
(control): Likewise.
(reg16_inoutportreg): Likewise.
(disp16): Likewise.
(disp32): Likewise.
(disp32s): Likewise.
(disp16_32): Likewise.
(anydisp): Likewise.
(baseindex): Likewise.
(regxmm): Likewise.
(imm8): Likewise.
(imm8s): Likewise.
(imm16): Likewise.
(imm32): Likewise.
(imm32s): Likewise.
(imm64): Likewise.
(imm16_32): Likewise.
(imm16_32s): Likewise.
(imm16_32_32s): Likewise.
(operand_type): Likewise.
(operand_type_check): Likewise.
(operand_type_match): Likewise.
(operand_type_register_match): Likewise.
(update_imm): Likewise.
(set_code_flag): Also update cpu_arch_flags_not.
(set_16bit_gcc_code_flag): Likewise.
(md_begin): Likewise.
(parse_insn): Use cpu_flags_check_x64 to check 64bit support.
Use cpu_flags_match to match instructions.
(i386_target_format): Update cpu_arch_isa_flags and
cpu_arch_tune_flags to i386_cpu_flags type with bitfield.
(smallest_imm_type): Check cpu_arch_tune to tune for i486.
(match_template): Don't initialize overlap0, overlap1,
overlap2, overlap3 and operand_types.
(process_suffix): Handle crc32 with 64bit register.
(MATCH): Removed.
(CONSISTENT_REGISTER_MATCH): Likewise.
* config/tc-i386.h (arch_entry): Updated to i386_cpu_flags
type.
opcodes/
2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
* configure.in (AC_CHECK_HEADERS): Add limits.h.
* configure: Regenerated.
* config.in: Likewise.
* i386-gen.c: Include "sysdep.h" instead of <stdlib.h> and
<string.h>. Use xstrerror instead of strerror.
(initializer): New.
(cpu_flag_init): Likewise.
(bitfield): Likewise.
(BITFIELD): New.
(cpu_flags): Likewise.
(opcode_modifiers): Likewise.
(operand_types): Likewise.
(compare): Likewise.
(set_cpu_flags): Likewise.
(output_cpu_flags): Likewise.
(process_i386_cpu_flags): Likewise.
(output_opcode_modifier): Likewise.
(process_i386_opcode_modifier): Likewise.
(output_operand_type): Likewise.
(process_i386_operand_type): Likewise.
(set_bitfield): Likewise.
(operand_type_init): Likewise.
(process_i386_initializers): Likewise.
(process_i386_opcodes): Call process_i386_opcode_modifier to
process opcode_modifier. Call process_i386_operand_type to
process operand_types.
(process_i386_registers): Call process_i386_operand_type to
process reg_type.
(main): Check unused bits in i386_cpu_flags and i386_operand_type.
Sort cpu_flags, opcode_modifiers and operand_types. Call
process_i386_initializers.
* i386-init.h: New.
* i386-tbl.h: Regenerated.
* i386-opc.h: Include <limits.h>.
(CHAR_BIT): Define as 8 if not defined.
(Cpu186): Changed to position of bitfiled.
(Cpu286): Likewise.
(Cpu386): Likewise.
(Cpu486): Likewise.
(Cpu586): Likewise.
(Cpu686): Likewise.
(CpuP4): Likewise.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuMMX): Likewise.
(CpuMMX2): Likewise.
(CpuSSE): Likewise.
(CpuSSE2): Likewise.
(Cpu3dnow): Likewise.
(Cpu3dnowA): Likewise.
(CpuSSE3): Likewise.
(CpuPadLock): Likewise.
(CpuSVME): Likewise.
(CpuVMX): Likewise.
(CpuSSSE3): Likewise.
(CpuSSE4a): Likewise.
(CpuABM): Likewise.
(CpuSSE4_1): Likewise.
(CpuSSE4_2): Likewise.
(Cpu64): Likewise.
(CpuNo64): Likewise.
(D): Likewise.
(W): Likewise.
(Modrm): Likewise.
(ShortForm): Likewise.
(Jump): Likewise.
(JumpDword): Likewise.
(JumpByte): Likewise.
(JumpInterSegment): Likewise.
(FloatMF): Likewise.
(FloatR): Likewise.
(FloatD): Likewise.
(Size16): Likewise.
(Size32): Likewise.
(Size64): Likewise.
(IgnoreSize): Likewise.
(DefaultSize): Likewise.
(No_bSuf): Likewise.
(No_wSuf): Likewise.
(No_lSuf): Likewise.
(No_sSuf): Likewise.
(No_qSuf): Likewise.
(No_xSuf): Likewise.
(FWait): Likewise.
(IsString): Likewise.
(RegKludge): Likewise.
(IsPrefix): Likewise.
(ImmExt): Likewise.
(NoRex64): Likewise.
(Rex64): Likewise.
(Ugh): Likewise.
(Reg8): Likewise.
(Reg16): Likewise.
(Reg32): Likewise.
(Reg64): Likewise.
(FloatReg): Likewise.
(RegMMX): Likewise.
(RegXMM): Likewise.
(Imm8): Likewise.
(Imm8S): Likewise.
(Imm16): Likewise.
(Imm32): Likewise.
(Imm32S): Likewise.
(Imm64): Likewise.
(Imm1): Likewise.
(BaseIndex): Likewise.
(Disp8): Likewise.
(Disp16): Likewise.
(Disp32): Likewise.
(Disp32S): Likewise.
(Disp64): Likewise.
(InOutPortReg): Likewise.
(ShiftCount): Likewise.
(Control): Likewise.
(Debug): Likewise.
(Test): Likewise.
(SReg2): Likewise.
(SReg3): Likewise.
(Acc): Likewise.
(FloatAcc): Likewise.
(JumpAbsolute): Likewise.
(EsSeg): Likewise.
(RegMem): Likewise.
(OTMax): Likewise.
(Reg): Commented out.
(WordReg): Likewise.
(ImplicitRegister): Likewise.
(Imm): Likewise.
(EncImm): Likewise.
(Disp): Likewise.
(AnyMem): Likewise.
(LLongMem): Likewise.
(LongMem): Likewise.
(ShortMem): Likewise.
(WordMem): Likewise.
(ByteMem): Likewise.
(CpuMax): New
(CpuLM): Likewise.
(CpuNumOfUints): Likewise.
(CpuNumOfBits): Likewise.
(CpuUnused): Likewise.
(OTNumOfUints): Likewise.
(OTNumOfBits): Likewise.
(OTUnused): Likewise.
(i386_cpu_flags): New type.
(i386_operand_type): Likewise.
(i386_opcode_modifier): Likewise.
(CpuSledgehammer): Removed.
(CpuSSE4): Likewise.
(CpuUnknownFlags): Likewise.
(Reg): Likewise.
(WordReg): Likewise.
(ImplicitRegister): Likewise.
(Imm): Likewise.
(EncImm): Likewise.
(Disp): Likewise.
(AnyMem): Likewise.
(LLongMem): Likewise.
(LongMem): Likewise.
(ShortMem): Likewise.
(WordMem): Likewise.
(ByteMem): Likewise.
(template): Use i386_cpu_flags for cpu_flags, use
i386_opcode_modifier for opcode_modifier, use
i386_operand_type for operand_types.
(reg_entry): Use i386_operand_type for reg_type.
* Makefile.am (HFILES): Add i386-init.h.
($(srcdir)/i386-init.h): New rule.
($(srcdir)/i386-tbl.h): Depend on $(srcdir)/i386-init.h
instead.
* Makefile.in: Regenerated.
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2007-09-06 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Handle invlpga, vmload,
vmrun and vmsave in SVME.
(process_suffix): Likewise.
gas/testsuite/
2007-09-06 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/svme.s: Updated to allow eax in 64bit.
* gas/i386/svme.d: Updated.
* gas/i386/svme64.d: Likewise.
opcodes/
2007-09-06 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Correct SVME instructions to allow 32bit register
operand in 64bit mode.
* i386-tbl.h: Regenerated.
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* config/tc-i386.c (i386_index_check): Don't use RegRex
on the reg_type field.
(parse_real_register): Use `||' instead of `|'.
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* config/tc-i386.c (process_operands): Remove segment override
check on SVME instructions.
(i386_index_check): Remove memory operand check on SVME
instructions.
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(md_assemble): Update init of insn. Use insn.reloc instead of
calculating from flag.
(get_imm): Set reloc rather than flag.
(calcop): Formatting.
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2007-08-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Handle cmpxchg8b in
Intel mode.
gas/testsuite/
2007-08-28 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/mem.s: New. Add tests for instructions with one
memory operand.
* gas/i386/x86-64-mem.s: Likewise.
* gas/i386/mem-intel.d: Updated.
* gas/i386/mem.d: Likewise.
* gas/i386/x86-64-mem-intel.d: Likewise.
* gas/i386/x86-64-mem.d: Likewise.
opcodes/
2007-08-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (Md): New.
(grps): Use 0 on invlpg. Use M on fxsave and fxrstor. Use
Md on ldmxcsr and stmxcsr. Use b_mode on clflush.
(OP_0fae): Clear bytemode for sfence.
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(mcf5253_ctrl): Add RAMBAR, MBAR, MBAR2.
(mcf5407_ctrl): New.
(m68k_cpus): Adjust 5407 entry.
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(m68k_cpus): Define 51QE cpu.
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* config/tc-arm.c (md_apply_fix): Cast bfd_vma values to long
before printing them.
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* doc/binutils.texi (objdump): Document -Mppcps.
gas/
* config/tc-ppc.c (parse_cpu): Handle "750cl".
(pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7".
(md_show_usage): Document -m750cl.
(md_assemble): Handle two delimiters in succession (eg. `),').
* doc/c-ppc.texi (PowerPC-Opts): Document -m750cl.
* testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests.
* testsuite/gas/ppc/ppc750ps.s: New file.
* testsuite/gas/ppc/ppc750ps.d: Likewise.
include/opcode/
* ppc.h (PPC_OPCODE_PPCPS): New.
opcodes/
* ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New.
(XOPS, XOPS_MASK, XW, XW_MASK): Likewise.
(PPCPS): Likewise.
(powerpc_opcodes): Add all pair singles instructions.
* ppc-dis.c (powerpc_dialect): Handle "ppcps".
(print_ppc_disassembler_options): Document -Mppcps.
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* config/tc-i386.c (x86_cons): Complain about invalid @got etc.
expressions.
(i386_immediate): Detect and complain about more cases of
invalid immediate expressions. Return failure rather than
converting them to zero.
(i386_displacement): Likewise.
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unrepresentable.
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gas/
* config/tc-arm.c (relaxed_symbol_addr): Compensate for alignment.
gas/testsuite/
* gas/arm/relax_load_align.d: new test.
* gas/arm/relax_load_align.s: new test.
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2007-08-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (check_byte_reg): Support pextrb and pinsrb.
gas/testsuite/
2007-08-09 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run sse4_1-intel, sse4_2-intel,
x86-64-sse4_1-intel and x86-64-sse4_2-intel.
* gas/i386/sse4_1-intel.d: New file.
* gas/i386/sse4_2-intel.d: Likewise.
* gas/i386/x86-64-sse4_1-intel.d: Likewise.
* gas/i386/x86-64-sse4_2-intel.d: Likewise.
* gas/i386/sse4_1.s: Add tests for Intel syntax.
* gas/i386/sse4_2.s: Likewise.
* gas/i386/x86-64-sse4_1.s: Likewise.
* gas/i386/x86-64-sse4_2.s: Likewise.
* gas/i386/sse4_1.d: Updated.
* gas/i386/sse4_2.d: Likewise.
* gas/i386/x86-64-sse4_1.d: Likewise.
* gas/i386/x86-64-sse4_2.d: Likewise.
opcodes/
2007-08-09 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoRex64 to pmovsxbw, pmovsxwd, pmovsxdq,
pmovzxbw, pmovzxwd, pmovzxdq and roundsd.
* i386-tbl.h: Regenerated.
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2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (check_long_reg): Allow cvtss2si to convert
DWORD memory to Reg64 in Intel synax.
(check_qword_reg): Allow cvtsd2si to convert QWORD memory to
Reg32 in Intel syntax.
gas/testsuite/
2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/simd.s: Add tests for cvtss2si/cvtsd2si in Intel
mode.
* gas/i386/x86-64-simd.s: Likewise.
* gas/i386/simd-intel.d: Updated.
* gas/i386/simd.d: Likewise.
* gas/i386/x86-64-simd-intel.d: Likewise.
* gas/i386/x86-64-simd.d: Likewise.
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(xg_expand_assembly_insn): Check for invalid extui operands.
(md_begin): Initialize xtensa_extui_opcode.
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2007-07-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Change i386 to PROCESSOR_I386.
(f32_15): Removed.
(jump_31): New.
(f32_patt): Remove f32_15.
(f16_patt): Likewise.
(i386_align_code): Updated to alt_long_patt for 64bit by
default.
* config/tc-i386.h (processor_type): Add PROCESSOR_I386.
2007-07-23 Evandro Menezes <evandro.menezes@amd.com>
* config/tc-i386.c (i386_align_code): Enable alignment up to
MAX_MEM_FOR_RS_ALIGN_CODE bytes. Remove special treatment
for K8.
* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Changed to
31.
gas/testsuite/
2007-07-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run nops16-1, nops-1-i386-i686, nops-1-k8,
nops-3-i386, nops-4, nops-4-i386, x86-64-nops-2, x86-64-nops-3,
x86-64-nops-4, x86-64-nops-4-core2 and x86-64-nops-4-k8.
* gas/i386/nops-1-i386-i686.d: New.
* gas/i386/nops-1-k8.d: Likewise.
* gas/i386/nops-3-i386.d : Likewise.
* gas/i386/nops-3-i686.d: Likewise.
* gas/i386/nops-4-i386.d: Likewise.
* gas/i386/nops-4.d: Likewise.
* gas/i386/nops16-1.d: Likewise.
* gas/i386/nops16-1.s: Likewise.
* gas/i386/x86-64-nops-1-k8.d: Likewise.
* gas/i386/x86-64-nops-2.d: Likewise.
* gas/i386/x86-64-nops-3.d: Likewise.
* gas/i386/x86-64-nops-4-core2.d: Likewise.
* gas/i386/x86-64-nops-4-k8.d: Likewise.
* gas/i386/x86-64-nops-4.d: Likewise.
* gas/i386/nops-1-i386.d: Updated.
* gas/i386/nops-1-i686.d: Likewise.
* gas/i386/nops-1.d: Likewise.
* gas/i386/nops-2-i386.d: Likewise.
* gas/i386/nops-2-merom.d : Likewise.
* gas/i386/nops-2.d: Likewise.
* gas/i386/nops-3.d: Likewise.
* gas/i386/x86-64-nops-1-merom.d: Likewise.
* gas/i386/x86-64-nops-1-nocona.d: Likewise.
* gas/i386/x86-64-nops-1.d: Likewise.
* gas/i386/x86-64-nops-1.s: Removed.
2007-07-23 Evandro Menezes <evandro.menezes@amd.com>
H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Don't run x86-64-nops-1-k8. Run
nops-3-i686 and nops-4-i686.
* gas/i386/nops-3-i686.d: New.
* gas/i386/nops-4-i686.d: Likewise.
* gas/i386/nops-4.s: Likewise.
* gas/i386/x86-64-nops-1-k8.d: Removed.
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integer.
Check the return value of insert_reg_alias and do not continue to create aliases once an insertion has failed.
(s_unreq): Delete the all-upper-case and all-lower-case alternatives as well.
* testsuite/gas/arm/arm.s: Add tests for re-aliasing a previously removed alias.
* testsuite/gas/arm/arm.l: Add new expected warning message.
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HAVE_64BIT_SYMBOLS.
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* config/tc-mips.c (mips_cpu_info_table): Add new entries for
{24k,24ke,34k,74k}f{2_1,1_1,x}. Also add an entry for 74kf3_2.
Deprecate *x and *fx.
* doc/c-mips.texi: Document the new CPU arguments. Deprecate
*x and *fx.
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2007-07-04 H.J. Lu <hongjiu.lu@intel.com>
* config/obj-coff.h (x86_64_target_format): Renamed to ...
(i386_target_format): This
(TARGET_FORMAT): Use i386_target_format.
* config/tc-i386.c (x86_64_target_format): Removed.
(i386_target_format): Handle PE formats.
gas/testsuite/
2007-07-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-nops-1 for x86_64-*-mingw*.
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* gas/m68k/mcf-coproc.d: New.
* gas/m68k/mcf-coproc.s: New.
* gas/m68k/all.exp: Add it.
gas/
* config/tc-m68k.c (m68k_ip): Add j & K operand types.
(install_operand): Add E encoding.
(md_begin): Check and skip initial '.' arg character.
(get_num): Add 0..511 case.
include/
* opcode/m68k.h: Document j K & E.
opcodes/
* m68k-dis.c (fetch_arg): Add E. Replace length switch with
direct masking.
(print_ins_arg): Add j & K operand types.
(match_insn_m68k): Check and skip initial '.' arg character.
(m68k_scan_mask): Likewise.
* m68k-opc.c (m68k_opcodes): Add coprocessor instructions.
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* config/obj-elf.c (elf_ecoff_set_ext): Make static when OBJ_MAYBE_ELF.
* config/obj-elf.h (obj_ecoff_set_ext): Comment.
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* elfxx-mips.c (mips_elf_calculate_relocation): Handle
R_MIPS_TLS_DTPREL32 and R_MIPS_TLS_DTPREL64.
* elf64-mips.c (mips_elf64_howto_table_rela): Support
R_MIPS_TLS_DTPREL64.
gas:
* config/tc-mips.c (s_dtprelword, s_dtpreldword,
s_dtprel_internal): New.
(mips_pseudo_table): Add .dtprelword and .dtpreldword.
(md_apply_fix): Handle BFD_RELOC_MIPS_TLS_DTPREL32 and
BFD_RELOC_MIPS_TLS_DTPREL64.
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coff section flag values to bfd section flag.
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* elf-attrs.c: New.
* Makefile.am (BFD32_BACKENDS): Add elf-attrs.lo.
(BFD32_BACKENDS_CFILES): Add elf-attrs.c.
(elf-attrs.lo): Generate dependencies.
* Makefile.in: Regenerate.
* configure.in (elf): Add elf-attrs.lo.
* configure: Regenerate.
* elf-bfd.h (struct elf_backend_data): Add entries for object
attributes.
(NUM_KNOWN_OBJ_ATTRIBUTES, obj_attribute, obj_attribute_list,
OBJ_ATTR_PROC, OBJ_ATTR_GNU, OBJ_ATTR_FIRST, OBJ_ATTR_LAST,
Tag_NULL, Tag_File, Tag_Section, Tag_Symbol, Tag_compatibility):
New.
(struct elf_obj_tdata): Add entries for object attributes.
(elf_known_obj_attributes, elf_other_obj_attributes,
elf_known_obj_attributes_proc, elf_other_obj_attributes_proc):
New.
(bfd_elf_obj_attr_size, bfd_elf_set_obj_attr_contents,
bfd_elf_get_obj_attr_int, bfd_elf_add_obj_attr_int,
bfd_elf_add_proc_attr_int, bfd_elf_add_obj_attr_string,
bfd_elf_add_proc_attr_string, bfd_elf_add_obj_attr_compat,
bfd_elf_add_proc_attr_compat, _bfd_elf_attr_strdup,
_bfd_elf_copy_obj_attributes, _bfd_elf_obj_attrs_arg_type,
_bfd_elf_parse_attributes, _bfd_elf_merge_object_attributes): New.
* elf.c (_bfd_elf_copy_private_bfd_data): Copy object attributes.
(bfd_section_from_shdr): Handle attributes sections.
* elflink.c (bfd_elf_final_link): Handle attributes sections.
* elfxx-target.h (elf_backend_obj_attrs_vendor,
elf_backend_obj_attrs_section, elf_backend_obj_attrs_arg_type,
elf_backend_obj_attrs_section_type): New.
(elfNN_bed): Update.
* elf32-arm.c (NUM_KNOWN_ATTRIBUTES, aeabi_attribute,
aeabi_attribute_list): Remove.
(struct elf32_arm_obj_tdata): Remove object attributes fields.
(check_use_blx, bfd_elf32_arm_set_vfp11_fix, using_thumb2,
elf32_arm_copy_private_bfd_data, elf32_arm_merge_eabi_attributes):
Update for new object attributes interfaces.
(uleb128_size, is_default_attr, eabi_attr_size,
elf32_arm_eabi_attr_size, write_uleb128, write_eabi_attribute,
elf32_arm_set_eabi_attr_contents, elf32_arm_bfd_final_link,
elf32_arm_new_eabi_attr, elf32_arm_get_eabi_attr_int,
elf32_arm_add_eabi_attr_int, attr_strdup,
elf32_arm_add_eabi_attr_string, elf32_arm_add_eabi_attr_compat,
copy_eabi_attributes, elf32_arm_parse_attributes): Remove. Moved
to generic code in elf-attrs.c.
(elf32_arm_obj_attrs_arg_type): New.
(elf32_arm_fake_sections): Do not handle .ARM.attributes.
(elf32_arm_section_from_shdr): Do not handle SHT_ARM_ATTRIBUTES.
(bfd_elf32_bfd_final_link): Remove.
(elf_backend_obj_attrs_vendor, elf_backend_obj_attrs_section,
elf_backend_obj_attrs_arg_type,
elf_backend_obj_attrs_section_type): New.
* elf32-bfin.c (bfin_elf_copy_private_bfd_data): Copy object
attributes.
* elf32-frv.c (frv_elf_copy_private_bfd_data): Likewise.
* elf32-iq2000.c (iq2000_elf_copy_private_bfd_data): Likewise.
* elf32-mep.c (mep_elf_copy_private_bfd_data): Likewise.
* elf32-mt.c (mt_elf_copy_private_bfd_data): Likewise.
* elf32-sh.c (sh_elf_copy_private_data): Likewise.
* elf64-sh64.c (sh_elf64_copy_private_data_internal): Likewise.
binutils:
* readelf.c (display_gnu_attribute): New.
(process_arm_specific): Rearrange as process_attributes.
(process_arm_specific): Replace by wrapper of process_attributes.
gas:
* as.c (create_obj_attrs_section): New.
(main): Call create_obj_attrs_section for ELF.
* read.c (s_gnu_attribute, skip_whitespace, skip_past_char,
skip_past_comma, s_vendor_attribute): New.
(potable): Add gnu_attribute for ELF.
* read.h (s_vendor_attribute): Declare.
* config/tc-arm.c (s_arm_eabi_attribute): Replace by wrapper
round s_vendor_attribute.
(aeabi_set_public_attributes): Update for new attributes
interfaces.
(arm_md_end): Remove attributes contents setting now done
generically.
include/elf:
* arm.h (elf32_arm_add_eabi_attr_int,
elf32_arm_add_eabi_attr_string, elf32_arm_add_eabi_attr_compat,
elf32_arm_get_eabi_attr_int, elf32_arm_set_eabi_attr_contents,
elf32_arm_eabi_attr_size, Tag_NULL, Tag_File, Tag_Section,
Tag_Symbol, Tag_compatibility): Remove.
* common.h (SHT_GNU_ATTRIBUTES): Define.
ld:
* emulparams/armelf.sh (OTHER_SECTIONS): Remove .ARM.attributes.
(ATTRS_SECTIONS): Define.
* scripttempl/elf.sc, scripttempl/elf32sh-symbian.sc,
scripttempl/elf_chaos.sc, scripttempl/elfi370.sc,
scripttempl/elfxtensa.sc: Handle ATTRS_SECTIONS.
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gas/
* config/tc-arm.c (parse_operands): Accept generic coprocessor regs
for OP_RVC.
(reg_names): Add fpinst, pfinst2, mvfr0 and mvfr1.
gas/testsuite/
* gas/arm/vfp1xD.d: Add new fmrx/fmxr tests.
* gas/arm/vfp1xD.s: Ditto.
* gas/arm/vfp1xD_t2.d: Ditto.
* gas/arm/vfp1xD_t2.s: Ditto.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add fmxr/fmrx mvfr0/mvfr1.
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2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Replace regKludge
with RegKludge.
opcodes/
2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (regKludge): Renamed to ...
(RegKludge): This.
* i386-opc.c (i386_optab): Replace regKludge with RegKludge.
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* elfxx-mips.c (mips_elf_calculate_relocation): Allow local stubs
to be used for calls from MIPS16 code.
gas/
* config/tc-mips.h (TC_SYMFIELD_TYPE): New.
* config/tc-mips.c (append_insn): Record which symbols have
R_MIPS16_26 relocations against them.
(mips_fix_adjustable): Don't reduce relocations against such symbols.
ld/testsuite/
* ld-mips-elf/mips16-local-stubs-1.s,
* ld-mips-elf/mips16-local-stubs-1.d: New tests.
* ld-mips-elf/mips-elf.exp: Run them.
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(frag_format_size): Handle RELAX_IMMED_STEP3.
(xtensa_relax_frag, md_convert_frag): Likewise.
* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_IMMED_STEP3.
(RELAX_IMMED_MAXSTEPS): Adjust.
* config/xtensa-relax.c (widen_spec_list): Add transitions from
wide branches to branch-over-jumps.
(build_transition): Handle wide branches in transition patterns.
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* config/tc-i386.c (disp_size): New.
(imm_size): Likewise.
(output_disp): Use disp_size and imm_size.
(output_imm): Use imm_size.
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use of literal_frag field.
* config/tc-xtensa.c (xtensa_mark_literal_pool_location): Record frag
in the literal_frag field.
(xtensa_move_literals): Use it here instead of searching. Update
literal_frag field with new value.
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gas/
* config/tc-arm.c (do_t_mov_cmp): Handle shift by register and
narrow shift by immediate.
gas/testsuite/
* gas/arm/thumb32.s: Add tests for shift instructions.
* gas/arm/thumb32.d: Ditto.
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* elf32-xtensa.c (extend_ebb_bounds_forward): Use renamed
XTENSA_PROP_NO_TRANSFORM flag instead of XTENSA_PROP_INSN_NO_TRANSFORM.
(extend_ebb_bounds_backward, compute_text_actions): Likewise.
(compute_ebb_proposed_actions, coalesce_shared_literal): Likewise.
(xtensa_get_property_predef_flags): Likewise.
(compute_removed_literals): Pass new arguments to is_removable_literal.
(is_removable_literal): Add sec, prop_table and ptblsize arguments.
Do not remove literal if the NO_TRANSFORM property flag is set.
gas/
* config/tc-xtensa.c (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
(XTENSA_PROP_NO_TRANSFORM): ...this.
(frag_flags_struct): Move is_no_transform out of the insn sub-struct.
(xtensa_mark_frags_for_org): New.
(xtensa_handle_align): Set RELAX_ORG frag subtype for rs_org.
(xtensa_post_relax_hook): Call xtensa_mark_frags_for_org.
(get_frag_property_flags): Adjust reference to is_no_transform flag.
(xtensa_frag_flags_combinable): Likewise.
(frag_flags_to_number): Likewise. Use XTENSA_PROP_NO_TRANSFORM.
* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_ORG.
include/elf/
* xtensa.h (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
(XTENSA_PROP_NO_TRANSFORM): ...this.
ld/
* emultempl/xtensaelf.em (replace_insn_sec_with_prop_sec): Use renamed
XTENSA_PROP_NO_TRANSFORM flag instead of XTENSA_PROP_INSN_NO_TRANSFORM.
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gas/
* config/tc-arm.c (s_align): Pad code sections appropriately.
gas/testsuite/
* gas/arm/thumb.d: Update expected output.
* gas/arm/thumb2_relax.d: Ditto.
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gas/
* config/tc-arm.c (insns): Correct Thumb-2 ldrd/strd opcodes.
gas/testsuite/
* gas/arm/thumb32.d: Add writeback addressing mode tests.
* gas/arm/thumb32.s: Update expected output.
opcodes/
* arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses.
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number@ppu.
(tc_gen_reloc): Abort if neither addsy or subsy is set.
(md_apply_fix): Don't attempt to resolve SPU_PPU relocs.
* config/tc-spu.h (md_operand): Handle @ppu without sym.
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gas/
* config/tc-arm.c (insns): Allow strex on M profile cores.
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2007-05-29 David S. Miller <davem@davemloft.net>
Jakub Jelinek <jakub@redhat.com>
PR gas/4558
* config/tc-sparc.c (md_apply_fix): Fix relocation overflow checks
for BFD_RELOC_SPARC_WDISP16 and BFD_RELOC_SPARC_WDISP19.
gas/testsuite/
2007-05-29 Jakub Jelinek <jakub@redhat.com>
PR gas/4558
* gas/sparc/sparc.exp: Add v9branch{1,2,3,4,5} tests.
* gas/sparc/v9branch1.d: New test.
* gas/sparc/v9branch1.s: New.
* gas/sparc/v9branch2.d: New test.
* gas/sparc/v9branch2.s: New.
* gas/sparc/v9branch3.d: New test.
* gas/sparc/v9branch3.s: New.
* gas/sparc/v9branch4.d: New test.
* gas/sparc/v9branch4.s: New.
* gas/sparc/v9branch5.d: New test.
* gas/sparc/v9branch5.s: New.
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* config/tc-ppc.c: Likewise.
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top 32 bits of 64 bit value if so doing results in passing
range check. Rewrite sign extension fudges similarly. Enable
fudges for powerpc64 too. Report user value if range check
fails rather than fudged value. Negate PPC_OPERAND_NEGATIVE
range rather than value, also to report user value on failure.
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gas/
* config/tc-arm.c (T2_SUBS_PC_LR): Define.
(do_t_add_sub): Correctly encode subs pc, lr, #const.
(do_t_mov_cmp): Correctly encode movs pc, lr.
gas/testsulte/
* gas/arm/thumb32.s: Add tests for subs pc, lr.
* gas/arm/thumb32.d: Change error-output: to stderr:.
Update expected output.
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containing a comma.
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fixups in error message.
(md_conver_frag_1): Propagate the fix source location and use
as_bad_where rather than fatal, for better error messages.
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