Age | Commit message (Collapse) | Author | Files | Lines |
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TLS relocs for General Dynamic and Local Dynamic models.
bfd/Changelog
* reloc.c: Add new relocations
* bfd-in2.h: Regenerated
* libbfd.h: Regenerated
* elf32-microblaze.c (microblaze_elf_howto_raw):
Add TLS relocations
(microblaze_elf_reloc_type_lookup): Likewise
(elf32_mb_link_hash_entry): define TLS reference types
(elf32_mb_link_hash_table): add TLS Local dynamic GOT entry
#define has_tls_reloc if section has TLS relocs
(dtprel_base), (check_unique_offset): New
(microblaze_elf_output_dynamic_relocation): output simple
dynamic relocation into SRELOC.
(microblaze_elf_relocate_section): Accommodate TLS relocations.
(microblaze_elf_check_relocs): Likewise
(update_local_sym_info): New
(microblaze_elf_copy_indirect_symbol): Add tls_mask.
(allocate_dynrelocs): Handle TLS symbol
(microblaze_elf_size_dynamic_sections): Set size and offset
(microblaze_elf_finish_dynamic_symbol): Use
microblaze_elf_output_dynamic_relocation
gas/Changelog
* config/tc-microblaze.c: Define TLS offsets
(md_relax_table): Add TLS offsets
(imm_types), (match_imm), (get_imm_otype): New to support
TLS offsets.
(tc_microblaze_fix_adjustable): Add TLS relocs.
(md_convert_frag): Support TLS offsets.
(md_apply_fix), (md_estimate_size_before_relax), (tc_gen_reloc):
Add TLS relocs
include/Changelog
* elf/microblaze.h: Add TLS relocs to START_RELOC_NUMBERS
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2012-12-06 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (exp_has_bignum_p): Remove.
(my_get_expression): Not get rid of bignums.
(s_ltorg): Increase the range of 'align'.
(programmer_friendly_fixup): Allow bignum expression.
gas/testsuite/
2012-12-06 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/illegal.s: Add test for unaccepted LDR literal.
* gas/aarch64/illegal.l: Update.
* gas/aarch64/programmer-friendly.s: Add tests for LDR literal with
the auto-generation of literal in pool.
* gas/aarch64/programmer-friendly.d: Update.
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* microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
INST_TYPE_R1_R2_SPECIAL
* microblaze-dis.c (print_insn_microblaze): Same.
gas/Changelog
* gas/config/tc-microblaze.c: Rename INST_TYPE_RD_R1_SPECIAL to
INST_TYPE_R1_R2_SPECIAL, don't set RD for wic.
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* config/tc-arm.c (md_apply_fix): Fix conversion of BL to BLX for
local targets in Thumb mode.
gas/testsuite/
* gas/arm/bl-local-2.s: New test.
* gas/arm/bl-local-2.d: New.
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* ppc.h (ppc_parse_cpu): Update prototype.
opcodes/
* ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits
set from ppc_opts.sticky in it. Delete "retain_mask".
(powerpc_init_dialect): Choose default dialect from info->mach
before parsing -M options. Handle more bfd_mach_ppc variants.
Update common default to power7.
gas/
* config/tc-ppc.c (sticky): New var.
(md_parse_option, ppc_machine): Update ppc_parse_cpu calls.
gas/testsuite/
* gas/ppc/astest2.d: Pass -Mppc to objdump.
ld/testsuite/
* ld-powerpc/plt1.d: Update for default "at" branch hints.
* ld-powerpc/tlsexe.d: Likewise.
* ld-powerpc/tlsexetoc.d: Likewise.
* ld-powerpc/tlsopt1.d: Likewise.
* ld-powerpc/tlsopt1_32.d: Likewise.
* ld-powerpc/tlsopt2.d: Likewise.
* ld-powerpc/tlsopt2_32.d: Likewise.
* ld-powerpc/tlsopt4.d: Likewise.
* ld-powerpc/tlsopt4_32.d: Likewise.
* ld-powerpc/tlsso.d: Likewise.
* ld-powerpc/tlstocso.d: Likewise.
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hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow
binutils/opcodes
* microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
* microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
binutils/gas
* config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas
* gas/microblaze/allinsn.s: Test use of SHR, SLR
* gas/microblaze/allinsn.d: Likewise
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* config/tc-arm.c (arm_symbol_chars): New variable.
* config/tc-arm.h (tc_symbol_chars): New macro, defined to that.
gas/testsuite/
* gas/arm/macro-pld.s: New file.
* gas/arm/macro-pld.d: New file.
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2012-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (first_error_fmt): Add ATTRIBUTE_UNUSED to the
local variable "ret".
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gas/
* config/tc-sparc.c (md_parse_option): Only certain arch
specifications should override the object to be 32-bit
or 64-bit.
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* microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
and increase MAX_OPCODES.
(op_code_struct): add mbar and sleep
* microblaze-opcm.h (microblaze_instr): add mbar
Define IMM_MBAR and IMM5_MBAR_MASK
* microblaze-dis.c: Add get_field_imm5_mbar
(print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
gas/
* config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5
gas/testsuite/
* gas/microblaze/allinsn.s: Add mbar and sleep
* gas/microblaze/allinsn.d: Likewise
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* config/tc-ppc.c (md_apply_fix): Leave field zero when emitting
an ELF reloc on data as well.
gas/testsuite/ChangeLog:
* gas/ppc/astest.d: Update for fixup changes.
* gas/ppc/astest64.d: Likewise.
* gas/ppc/astest2.d: Likewise.
* gas/ppc/astest2_64.d: Likewise.
* gas/ppc/test1elf32.d: Likewise.
* gas/ppc/test1elf64.d: Likewise.
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* config/obj-elf.h (obj_elf_vendor_attribute): ... here.
* read.c (potable): Remove "gnu_attribute".
(skip_whitespace, skip_past_char, skip_past_comma): Delete, move
to config/obj-elf.c.
(s_vendor_attribute): Delete, move to obj_elf_vendor_attribute
in config/obj-elf.c.
(s_gnu_attribute): Delete, move to obj_elf_gnu_attribute in
config/obj-elf.c.
* config/obj-elf.c (elf_pseudo_table): Add "gnu_attribute".
(skip_whitespace, skip_past_char, skip_past_comma): New, moved
from read.c.
(obj_elf_vendor_attribute): New, moved from s_vendor_attribute
in read.c.
(obj_elf_gnu_attribute): New, moved from s_gnu_attribute in
read.c.
* config/tc-arm.c (s_arm_eabi_attribute): Rename
s_vendor_attribute to obj_elf_vendor_attribute.
* config/tc-tic6x.c (s_tic6x_c6xabi_attribute): Likewise.
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* Makefile.am (ALL_MACHINES): Add cpu-v850-rh850.lo.
(ALL_MACHINES_CFILES): Add cpu-v850-rh850.c.
* archures.c (bfd_arch_info): Add bfd_v850_rh850_arch.
* config.bfd: Likewise.
* configure.in: Add bfd_elf32_v850_rh850_vec.
* cpu-v850.c: Update printed description.
* cpu-v850_rh850.c: New file.
* elf32-v850.c (v850_elf_check_relocs): Add support for RH850 ABI
relocs.
(v850_elf_perform_relocation): Likewise.
(v850_elf_final_link_relocate): Likewise.
(v850_elf_relocate_section): Likewise.
(v850_elf_relax_section): Likewise.
(v800_elf_howto_table): New.
(v850_elf_object_p): Add support for RH850 ABI values.
(v850_elf_final_write_processing): Likewise.
(v850_elf_merge_private_bfd_data): Likewise.
(v850_elf_print_private_bfd_data): Likewise.
(v800_elf_reloc_map): New.
(v800_elf_reloc_type_lookup): New.
(v800_elf_reloc_name_lookup): New.
(v800_elf_info_to_howto): New.
(bfd_elf32_v850_rh850_vec): New.
(bfd_arch_v850_rh850): New.
* targets.c (_bfd_targets): Add bfd_elf32_v850_rh850_vec.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* readelf.c (get_machine_flags): Add support for E_FLAG_RX_ABI.
(guess_is_rela): Add EM_V800.
(dump_relocations): Likewise.
(get_machine_name): Update EM_V800.
(get_machine_flags): Add support for RH850 ABI flags.
(is_32bit_abs_reloc): Add support for RH850 ABI reloc.
* config/tc-v850.c (v850_target_arch): New.
(v850_target_format): New.
(set_machine): Use v850_target_arch.
(md_begin): Likewise.
(md_show_usage): Document new switches.
(md_parse_option): Add -mgcc-abi, -mrh850-abi, -m8byte-align and
-m4byte-align.
* config/tc-v850.c (TARGET_ARCH) Use v850_target_arch.
(TARGET_FORMAT): Use v850_target_format.
* doc/c-v850.texi: Document new options.
* v850.h: Add RH850 ABI values.
* Makefile.am: (ALL_EMULATION_SOURCES): Add ev850_rh850.c.
* Makefile.in: Regenerate.
* configure.tgt (v850*-*-*): Make v850_rh850 the default
emulation. Add vanilla v850 as an extra emulation.
* emulparams/v850_rh850.sh: New file.
* scripttempl/v850_rh850.sc: New file.
* configure.in: Add bfd_v850_rh850_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Likewise.
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* elf32-rx.c (describe_flags): New function. Returns a buffer
containing a description of the E_FLAG_RX_... values set.
(rx_elf_merge_private_bfd_data): Use it.
(rx_elf_print_private_bfd_data): Likewise.
(elf32_rx_machine): Skip EF_RX_CPU_RX check.
(elf32_rx_special_sections): Define.
(elf_backend_special_sections): Define.
2012-11-09 Nick Clifton <nickc@redhat.com>
* readelf.c (get_machine_flags): Add support for E_FLAG_RX_ABI.
2012-11-09 Nick Clifton <nickc@redhat.com>
* config/obj-elf.c (obj_elf_change_section): Allow init array
sections to have the SHF_EXECINSTR attribute for the RX target.
* config/tc-rx.c (elf_flags): Initialise with E_FLAG_RX_ABI.
(enum options): Add OPTION_USES_GCC_ABI and OPTION_USES_RX_ABI.
(md_longopts): Add -mgcc-abi and -mrx-abi.
(md_parse_option): Add support for OPTION_USES_GCC_ABI and
OPTION_USES_RX_ABI.
* doc/as.texinfo (RX Options): Add mention of remaining RX
options.
* doc/c-rx.texi: Document -mgcc-abi and -mrx-abi.
2012-11-09 Nick Clifton <nickc@redhat.com>
* rx.h (EF_RX_CPU_RX): Add comment.
(E_FLAG_RX_ABI): Define.
2012-11-09 Nick Clifton <nickc@redhat.com>
* emultempl/rxelf.em (no_flag_mismatch_warnings): Initialise to
true.
(PARSE_AND_LIST_LONGOPTS): Add flag-mismatch-warnings.
(PARSE_AND_LIST_ARG_CASES): Add support for
--flag-mismatch-warnings.
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binutils/bfd/Changelog
2012-11-09 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* config.bfd: Add microblazeel-*-*
* configure.in: Likewise.
* configure: Regenerate.
* elf32-microblaze.c (microblaze_elf_relocate_section):
Add endian awareness.
(microblaze_elf_merge_private_bfd_data): New.
(microblaze_bfd_write_imm_value_32): New.
(microblaze_bfd_write_imm_value_64): New.
(microblaze_elf_relax_section): Add endian awareness.
(microblaze_elf_add_symbol_hook): Define TARGET_LITTLE_NAME,
TARGET_LITTLE_SYM and bfd_elf32_bfd_merge_private_bfd_data.
* targets.c: Add bfd target bfd_elf32_microblazeel_vec.
binutils/gas/Changelog
2012-11-09 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* tc-microblaze.c (md_longopts): Define OPTION_EB and
OPTION_EL for target.
(md_parse_option): Likewise.
* tc-microblaze.h: Set elf32-microblazeel if not
target_big_endian for TARGET_FORMAT.
* configure.tgt: Add microblazeel and set endian per target.
binutils/gas/testsuite/Changelog
2012-11-09 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze/endian.exp: New file - endian
testcase for microblaze / microblazeel.
* gas/microblaze/endian.s: Likewise.
* gas/microblaze/endian_be.d: Likewise.
* gas/microblaze/endian_le.d: Likewise.
* gas/microblaze/endian_le_elf.d: Likewise.
* gas/microblaze/reloc_sym.d: Update to accept targets
other than elf32-microblaze.
* gas/microblaze/special_reg.d: Likewise.
binutils/ld/Changelog
2012-11-09 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* Makefile.am: Add eelf32microblazeel.c and eelf32mbel_linux.c.
* Makefile.in: Regenerated.
* configure.tgt: Add microblazeel and set endian per target.
* emulparams/elf32mb_linux.sh: Add OUTPUT_FORMAT.
* emulparams/elf32microblaze.sh: Likewise.
* emulparams/elf32mbel_linux.sh: New file.
* emulparams/elf32microblazeel.sh: Likewise.
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bfd/
* aout-tic30.c (MY_final_link_callback): Remove trailing
redundant `;'.
* coff-h8500.c (extra_case): Likewise.
(bfd_coff_reloc16_get_value): Likewise.
* dwarf2.c (_bfd_dwarf2_cleanup_debug_info): Likewise.
* elf.c (_bfd_elf_slurp_version_tables): Likewise.
* elf32-frv.c (elf32_frv_relocate_section): Likewise.
* elf32-v850.c (v850_elf_perform_relocation): Likewise.
* opncls.c (bfd_calc_gnu_debuglink_crc32): Likewise.
* plugin.c (add_symbols): Likewise.
* reloc.c (bfd_check_overflow): Likewise.
* vms-lib.c (_bfd_vms_lib_archive_p): Likewise.
binutils/
* coffgrok.c (coff_grok): Remove trailing redundant `;'.
* resrc.c (open_input_stream): Likewise.
gas/
* config/atof-ieee.c (gen_to_words): Remove trailing redundant
`;'.
* config/atof-vax.c (flonum_gen2vax): Likewise.
* config/tc-d10v.c (write_2_short): Likewise.
* config/tc-i386-intel.c (i386_intel_simplify): Likewise.
* config/tc-s390.c (tc_s390_force_relocation): Likewise.
* config/tc-v850.c (md_parse_option): Likewise.
* config/tc-xtensa.c (find_address_of_next_align_frag): Likewise.
* dwarf2dbg.c (out_header): Likewise.
* symbols.c (dollar_label_name): Likewise.
(fb_label_name): Likewise.
ld/
* testplug.c (record_add_file): Remove trailing redundant `;'.
opcodes/
* aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
* ia64-gen.c (fetch_insn_class): Likewise.
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* config/tc-mips.c (mips_ip) <'u'>: Default to BFD_RELOC_LO16.
gas/testsuite/
* gas/mips/lui.d: New test.
* gas/mips/micromips@lui.d: New test.
* gas/mips/lui-1.l: New list test.
* gas/mips/lui-2.l: New list test.
* gas/mips/lui.s: New test source.
* gas/mips/lui-1.s: New test source.
* gas/mips/lui-2.s: New test source.
* gas/mips/mips.exp: Run the new tests.
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* config/tc-m68hc11.c: Fix R_M68HC12_16B relocation for movb/w
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* config/tc-microblaze.c: Remove special register condition check
for INST_TYPE_RFSL related instructions.
2012-11-07 David Holsgrove <david.holsgrove@xilinx.com>
* testsuite/gas/microblaze/special_reg.exp: Add test case.
* testsuite/gas/microblaze/special_reg.s: Likewise.
* testsuite/gas/microblaze/special_reg.d: Likewise.
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style and whitespace fixes. Wrap overly long lines. Format
help message.
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* coff-tic4x.c (tic4x_coff0_vec, tic4x_coff0_beh_vec,
tic4x_coff1_vec, tic4x_coff1_beh_vec, tic4x_coff2_vec,
tic4x_coff2_beh_vec): Allow SEC_CODE and SEC_READONLY in
section flags.
gas/
* config/tc-tic4x.c: Remove alignment TODO comments.
(tic4x_do_align): Enable subseg_text_p test.
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* elf64-ppc.c (struct ppc_link_hash_table): Add dot_toc_dot.
(ppc64_elf_size_stubs): Lookup ".TOC.".
(ppc64_elf_relocate_section): Resolve special symbol ".TOC.".
gas/
* config/tc-ppc.c (ppc_elf_adjust_symtab): New function, split out..
(ppc_frob_file_before_adjust): ..from here.
(md_apply_fix): Set BSF_KEEP on .TOC. if not @tocbase.
* config/tc-ppc.h (ppc_elf_adjust_symtab): Declare.
(tc_adjust_symtab): Define.
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last patch.
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* config/tc-m68hc11.c: Likewise.
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(ppc_setup_opcodes): Assert num_powerpc_operands fit.
(ppc_is_toc_sym): Move earlier in file.
(md_assemble): Move code setting reloc from md_apply_fix. Combine
non-ELF code setting fixup with ELF code. Stash opindex in
fx_pcrel_adjust. Adjust fixup offset for VLE. Don't set
fx_no_overflow here.
(md_apply_fix): Rewrite to use ppc_insert_operand for all
resolved instruction fields. Leave insn field zero when
emitting an ELF reloc in most cases.
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* config/tc-m68k.c (tc_gen_reloc, md_pcrel_from): Remove explicit
sign extendion of fx_pxrel_adjust.
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* config/tc-mips.c (append_insn): Set fx_no_overflow for 16-bit
microMIPS branch relocations.
gas/testsuite/
* gas/mips/micromips-b16.d: New test.
* gas/mips/micromips-b16.s: New test source.
* gas/mips/mips.exp: Run the new test.
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* config/tc-mips.c (is_delay_slot_valid): Don't accept macros
in 16-bit delay slots.
(macro_build_jalr): Emit 32-bit JALR if placed in a 32-bit delay
slot.
(macro) <M_JAL_2>: Likewise
gas/testsuite/
* gas/mips/micromips-branch-delay.l: Update messages for 16-bit
delay slot changes.
* gas/mips/micromips-warn-branch-delay.d: New test.
* gas/mips/micromips-warn-branch-delay.l: Stderr output for the
new test.
* gas/mips/micromips-warn-branch-delay-1.d: New test.
* gas/mips/micromips-warn-branch-delay.s: New test source.
* gas/mips/micromips-warn-branch-delay-1.s: New test source.
* gas/mips/mips.exp: Run the new tests.
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* config/tc-microblaze.c: Check for weak symbols before
emitting relocation.
2012-10-31 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze: New.
* gas/microblaze/reloc_sym.exp: Add test case.
* gas/microblaze/reloc_strongsym.s: Likewise.
* gas/microblaze/reloc_weaksym.s: Likewise.
* gas/microblaze/reloc_sym.d: Likewise.
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* dlltool.c (INIT_SEC_DATA): Move.
(secdata <DLLTOOL_PPC>): Use here too.
binutils/testsuite/
* binutils-all/copy-3.d: Exclude all cygwin and mingw targets,
and rs6000.
gas/
* config/tc-ppc.c (ppc_znop): Remove unused vars.
ld/
* configure.tgt (powerpcle-pe,winnt,cygwin): Add deffilep.o
and pe-dll.o.
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bfd/
* elf32-ppc.c (ppc_elf_reloc_type_lookup): Decode ppc64 _DS
bfd_reloc values. Map to corresponding D-form relocs.
(is_insn_ds_form, is_insn_qs_form): New functions.
(ppc_elf_relocate_section): Validate insn with DS-form or DQ-form
fields using D-form reloc.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Fix comment.
(md_assemble): Translate to _DS relocs for ppc32 as well as ppc64.
(tc_gen_reloc): Handle _DS relocs in ppc32 mode.
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(coff_frob_symbol): Check that function-aux entries are generated for
defined symbols only.
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(pa_get_absolute_expression): Simplify.
(pa_ip): Use pa_get_number instead of pa_get_absolute_expression
to get SOP, SFU and COPR identifiers.
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loads that reference the right half of a floating point register.
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not involving a carry.
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* config/tc-arm.c: Change condition code insertion for
lds[hb] instructions from after the 2nd character to after the 3rd.
(tCM): Remove macro.
(TxCM): Likewise.
(TxCM_): Likewise.
(TCM): Likewise.
2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gas/arm/ldgesb-bad.d: New file.
* gas/arm/ldgesb-bad.l: Likewise.
* gas/arm/ldgesb-bad.s: Likewise.
* gas/arm/ldgesh-bad.d: Likewise.
* gas/arm/ldgesh-bad.l: Likewise.
* gas/arm/ldgesh-bad.s: Likewise.
* gas/arm/ldsgeb.d: Likewise.
* gas/arm/ldsgeb.s: Likewise.
* gas/arm/ldsgeb.l: Likewise.
* gas/arm/ldsgeh.d: Likewise.
* gas/arm/ldsgeh.s: Likewise.
* gas/arm/ldsgeh.l: Likewise.
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gas/
* config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS.
* doc/c-i386.texi: Add -march=bdver3 option.
gas/testsuite/
* gas/i386/i386.exp: Run bdver3 test cases.
* gas/i386/nops-1-bdver3.d: New.
* gas/i386/arch-10-bdver3.d: New.
* gas/i386/x86-64-nops-1-bdver3.d: New.
* gas/i386/x86-64-arch-2-bdver3.d: New.
opcodes/
* i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
* i386-init.h: Regenerated.
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register operand of clr1, not1, set1 and tst1 instructions.
* config/tc-v850.c (v850_insert_operand): Use a static buffer for
the error message.
* gas/v850/v850e1.d: Fix expected disassembly of clr1, not1, set1
and tst1 insns.
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* config/tc-s390.c (s390_parse_cpu): Add new option zEC12.
* doc/as.texinfo: Document new option zEC12.
* doc/c-s390.texi: Likewise.
2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/s390.exp: Run zEC12 tests.
* gas/s390/zarch-zEC12.d: New file.
* gas/s390/zarch-zEC12.s: New file.
2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-mkopc.c: Support new option zEC12.
* s390-opc.c: Add new instruction formats.
* s390-opc.txt: Add new instructions for zEC12.
2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
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be used in expressions.
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* config/tc-mips.h (TC_FORCE_RELOCATION): Remove comment.
* config/tc-mips.c (calculate_reloc): New function.
(append_insn): Use it. Do not resolve compound relocations here.
(mips16_macro_build, mips16_ip): Use calculate_reloc.
(mips16_immed_extend): New function, split out from...
(mips16_immed): ...here.
(mips_frob_file): Handle null symbols.
(mips_force_relocation): Remove NEWABI handling.
(read_reloc_insn, write_reloc_insn): New functions.
(md_apply_fix): Report TLS relocations against constants.
Use read_reloc_insn, calculate_reloc and write_reloc_insn.
Report relocations against constants that can't be resolved
at assembly time.
gas/testsuite/
* gas/mips/elf-rel22.s, gas/mips/elf-rel22.d: Add more tests.
* gas/mips/elf-rel29.s, gas/mips/elf-rel29.d,
gas/mips/micromips@elf-rel29.d, gas/mips/elf-rel30.s,
gas/mips/elf-rel30.l: New tests.
* gas/mips/mips.exp: Run them.
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2012-09-23 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (append_insn) <BFD_RELOC_MIPS_JMP>: Don't
mark as incomplete for constant expressions.
<BFD_RELOC_MIPS16_JMP>: Likewise.
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2012-09-23 Richard Sandiford <rdsandiford@googlemail.com>
Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.h (mips_record_label): Delete.
(mips_add_dot_label): Declare.
(tc_new_dot_label): Use it.
* config/tc-mips.c (mips_assembling_insn): New variable.
(md_assemble): Call mips_mark_labels. Set mips_assembling_insn
while the main part of the function is executing.
(mips_compressed_mark_label): New function, split out from...
(mips_compressed_mark_labels): ...here.
(append_insn): Don't call mips_mark_labels here.
(mips_record_label): Make local.
(mips_add_dot_label): New function.
gas/testsuite/
* gas/mips/dot-1.s, gas/mips/dot-1.d, gas/mips/micromips@dot-1.d,
gas/mips/mips16@dot-1.d: New test.
* gas/mips/mips.exp: Run it.
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* config/tc-mips.c (SEXT_16BIT): New macro.
(mips16_immed): Take the reloc type as a parameter. Do not impose
a signed vs. unsigned distinction on the value when a relocation
operator was used.
(mips16_macro_build, mips16_ip, md_convert_frag): Pass the reloc
type to mips16_immed.
(macro): Use SEXT_16BIT.
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* config/tc-mips.c (read_insn, write_insn, read_compressed_insn):
New functions.
(install_insn, md_apply_fix, md_convert_frag, mips_handle_align):
Use them, and write_compressed_insn.
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* config/tc-mips.c (mips_cl_insn): Remove use_extend and extend.
(MIPS16_EXTEND): New macro.
(mips16_opcode_length): New function.
(insn_length): Use it.
(create_insn): Update after mips_cl_insn change.
(write_compressed_insn): New function.
(install_insn): Use it.
(append_insn): Use insn_length to check for unextended MIPS16
instructions.
(mips16_macro_build): Update call to mips16_immed.
(mips16_ip): Likewise. Use MIPS16_EXTEND to force an extended
instruction.
(mips16_immed): Remove use_extend and extend; install EXTEND
opcodes in the upper 16 bits of *INSN instead. Keep the
instruction extended if it already is. Replace warn, small
and ext with a forced_insn_length-like parameter.
(md_convert_frag): Update call mips16_immed.
Use write_compressed_insn.
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gas/
* config/tc-i386.c (cpu_arch): Add .cx16.
* doc/c-i386.texi: Document .cx16.
gas/testsuite/
* gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b.
* gas/i386/x86-64-arch-2.d: Update correspondingly.
* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
* gas/i386/x86-64-arch-2-btver1.d: Likewise.
* gas/i386/x86-64-arch-2-btver2.d: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
(cpu_flags): Add CpuCX16.
* i386-opc.h (CpuCX16): New.
(i386_cpu_flags): Add cpucx16.
* i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
* i386-tbl.h: Regenerate.
* i386-init.h: Likewise.
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