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AgeCommit message (Expand)AuthorFilesLines
2017-03-22Sanitize RISC-V GAS help text, documentationPalmer Dabbelt1-7/+2
2017-03-22gas: xtensa: make trampolines relaxation work with jumps in slots other than 0Max Filippov1-4/+16
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-4/+2
2017-03-20[arm] Document missing -mfpu entries.Richard Earnshaw1-3/+3
2017-03-20[arm] Add neon-vfp3 as an alias for neon to -mfpu.Richard Earnshaw1-0/+1
2017-03-16gas/arc: Limit special handling of t/nt flag to ARCv2Rinat Zelig1-5/+13
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng1-0/+8
2017-03-15Fix building riscv targets with gcc v6.3.1Nick Clifton1-1/+1
2017-03-14RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.Kuan-Lin Chen1-0/+3
2017-03-14RISC-V: Fix DW_CFA_advance_loc relocation.Kuan-Lin Chen1-0/+2
2017-03-14RISC-V: Fix the offset of CFA relocation.Kuan-Lin Chen1-10/+10
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AA...Nick Clifton1-6/+6
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-44/+114
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+2
2017-02-28Nios2 dynobj handling fixesAlan Modra1-0/+8
2017-02-28PowerPC addpcis fixAlan Modra2-81/+61
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-3/+10
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-0/+3
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel1-2/+6
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-7/+46
2017-02-22GAS: Consistently fix labels at the `.end' pseudo-opMaciej W. Rozycki1-4/+4
2017-02-20Downgrade powerpc register error to warningAlan Modra1-3/+3
2017-02-17GAS: Add ECOFF `.aent' pseudo-op supportMaciej W. Rozycki2-2/+4
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu1-9/+32
2017-02-14PowerPC register expression checksAlan Modra2-484/+548
2017-02-13[ARM] Allow immediate without prefix in unified syntax for VCMPThomas Preud'homme1-3/+7
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-0/+4
2017-01-30MIPS: Add options to control branch ISA checksMaciej W. Rozycki1-0/+22
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton68-355/+355
2017-01-20Fix potential array overrun in x86 assembler.Nick Clifton1-1/+1
2017-01-18PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sectionsMaciej W. Rozycki1-5/+6
2017-01-18Add support for processing lex source files with flex v 2.6.3Bernhard Rosenkranzer1-9/+2
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+3
2017-01-09RISC-V/GAS: Support more relocs against constant addressesAndrew Waterman1-3/+2
2017-01-09RISC-V/GAS: Improve handling of invalid relocsAndrew Waterman1-1/+9
2017-01-09RISC-V/GAS: Correct branch relaxation for weak symbols.Andrew Waterman1-0/+1
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-0/+2
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-2/+12
2017-01-03Fix PRU GAS for 32-bit hostsDimitar Dimitrov1-7/+12
2017-01-02Update year range in copyright notice of all files.Alan Modra242-242/+242
2016-12-31PRU GAS PortDimitar Dimitrov3-0/+2104
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki1-1/+1
2016-12-23MIPS16/GAS: Clean up invalid unextended operand handlingMaciej W. Rozycki1-2/+5
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-5/+5
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+2
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki1-8/+1
2016-12-23MIPS16/GAS: Fix forced size suffixes with argumentless instructionsMaciej W. Rozycki1-10/+15
2016-12-23[msp430] Sync tc-msp430.c with devices.csvJoe Seymour1-6/+5
2016-12-22Support aligning text section from odd addressesAndrew Waterman1-6/+16
2016-12-22Fix a const-safety issue on GCC-4.9 and aboveTim Newsome1-1/+1
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