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2010-11-10gas/Richard Sandiford1-2/+4
* config/tc-arm.c (do_t_branch): Treat (PLT) branches as wide. gas/testsuite/ * gas/arm/plt-1.s, gas/arm/plt-1.d: New test.
2010-11-05 * config/tc-cr16.c (getprocreg_image): Fix typo MAX_PREG ->Nick Clifton1-2/+2
MAX_REG. (getprocregp_image): Likewise.
2010-11-05 * config/obj-coff.c (weak_altname2name): Don't infer from the presenceDave Korn1-11/+1
of a period that the symbol has been already uniquify-d. (weak_uniquify): Don't worry that the symbol might have been already uniquify-d.
2010-11-04 * config/tc-ppc.c (nop_limit): New var.Alan Modra1-0/+42
(OPTION_NOPS): Define. (md_longopts): Add --nops. (md_parse_option): Handle it. (md_show_usage): Publish. (ppc_handle_align): Pad with a branch followed by nops if more than nop_limit nops.
2010-11-03Properly fold _GLOBAL_OFFSET_TABLE_ in Intel syntax.H.J. Lu1-1/+6
gas/ 2010-11-03 H.J. Lu <hongjiu.lu@intel.com> PR gas/12186 * config/tc-i386-intel.c (i386_intel_fold): Properly fold _GLOBAL_OFFSET_TABLE_. gas/testsuite/ 2010-11-03 H.J. Lu <hongjiu.lu@intel.com> PR gas/12186 * gas/i386/gotpc.s: Add more _GLOBAL_OFFSET_TABLE_ test. * gas/i386/gotpc.d: Updated.
2010-11-02bfd:Joseph Myers1-0/+72
* elf32-tic6x.c (elf32_tic6x_obj_attrs_arg_type): Except for Tag_ABI_compatibility, treat odd tags as strings and even ones as integers. (elf32_tic6x_obj_attrs_order, elf32_tic6x_tag_to_array_alignment, elf32_tic6x_array_alignment_to_tag): New. (elf32_tic6x_merge_attributes): Handle more attributes. Set type for merged attributes. (elf_backend_obj_attrs_order): Define. binutils: * readelf.c (display_tic6x_attribute): Handle more attributes. gas: * config/tc-tic6x.c (OPTION_MPID, OPTION_MPIC, OPTION_MNO_PIC): New enum values. (md_longopts): Add options mpid, mpic and mno-pic. (tic6x_pid_type, tic6x_pid, tic6x_pic, tic6x_pid_type_table, tic6x_pid_types, tic6x_use_pid): New. (md_parse_option): Handle new options. (md_show_usage): Output help text for new options. (tic6x_set_attributes): Set PID and PIC attributes. * doc/as.texinfo: Document -mpid=, -mpic and -mno-pic. * doc/c-tic6x.texi (TIC6X Options): Likewise. gas/testsuite: * gas/tic6x/attr-array-directive-1.d, gas/tic6x/attr-array-directive-1.s, gas/tic6x/attr-array-directive-2.d, gas/tic6x/attr-array-directive-2.s, gas/tic6x/attr-array-directive-3.d, gas/tic6x/attr-array-directive-3.s, gas/tic6x/attr-array-directive-4.d, gas/tic6x/attr-array-directive-4.s, gas/tic6x/attr-conformance-directive-1.d, gas/tic6x/attr-conformance-directive-1.s, gas/tic6x/attr-conformance-directive-2.d, gas/tic6x/attr-conformance-directive-2.s, gas/tic6x/attr-pic-directive-1.d, gas/tic6x/attr-pic-directive-1.s, gas/tic6x/attr-pic-directive-2.d, gas/tic6x/attr-pic-directive-2.s, gas/tic6x/attr-pic-opts-mno-pic.d, gas/tic6x/attr-pic-opts-mpic.d, gas/tic6x/attr-pid-directive-1.d, gas/tic6x/attr-pid-directive-1.s, gas/tic6x/attr-pid-directive-2.d, gas/tic6x/attr-pid-directive-2.s, gas/tic6x/attr-pid-opts-mpid-far.d, gas/tic6x/attr-pid-opts-mpid-near.d, gas/tic6x/attr-pid-opts-mpid-no.d, gas/tic6x/attr-stack-directive-1.d, gas/tic6x/attr-stack-directive-1.s, gas/tic6x/attr-stack-directive-2.d, gas/tic6x/attr-stack-directive-2.s, gas/tic6x/attr-wchar-directive-1.d, gas/tic6x/attr-wchar-directive-1.s, gas/tic6x/attr-wchar-directive-2.d, gas/tic6x/attr-wchar-directive-2.s: New tests. include/elf: * tic6x-attrs.h (Tag_ABI_wchar_t, Tag_ABI_stack_align_needed, Tag_ABI_stack_align_preserved, Tag_ABI_PID, Tag_ABI_PIC, Tag_ABI_array_object_alignment, Tag_ABI_array_object_align_expected, Tag_ABI_conformance): Define. ld/testsuite: * ld-tic6x/attr-array-16-16.d, ld-tic6x/attr-array-16-4.d, ld-tic6x/attr-array-16-416.d, ld-tic6x/attr-array-16-48.d, ld-tic6x/attr-array-16-8.d, ld-tic6x/attr-array-16-816.d, ld-tic6x/attr-array-16.s, ld-tic6x/attr-array-4-16.d, ld-tic6x/attr-array-4-4.d, ld-tic6x/attr-array-4-416.d, ld-tic6x/attr-array-4-48.d, ld-tic6x/attr-array-4-8.d, ld-tic6x/attr-array-4-816.d, ld-tic6x/attr-array-4.s, ld-tic6x/attr-array-416-16.d, ld-tic6x/attr-array-416-4.d, ld-tic6x/attr-array-416-416.d, ld-tic6x/attr-array-416-48.d, ld-tic6x/attr-array-416-8.d, ld-tic6x/attr-array-416-816.d, ld-tic6x/attr-array-416.s, ld-tic6x/attr-array-48-16.d, ld-tic6x/attr-array-48-4.d, ld-tic6x/attr-array-48-416.d, ld-tic6x/attr-array-48-48.d, ld-tic6x/attr-array-48-8.d, ld-tic6x/attr-array-48-816.d, ld-tic6x/attr-array-48.s, ld-tic6x/attr-array-8-16.d, ld-tic6x/attr-array-8-4.d, ld-tic6x/attr-array-8-416.d, ld-tic6x/attr-array-8-48.d, ld-tic6x/attr-array-8-8.d, ld-tic6x/attr-array-8-816.d, ld-tic6x/attr-array-8.s, ld-tic6x/attr-array-816-16.d, ld-tic6x/attr-array-816-4.d, ld-tic6x/attr-array-816-416.d, ld-tic6x/attr-array-816-48.d, ld-tic6x/attr-array-816-8.d, ld-tic6x/attr-array-816-816.d, ld-tic6x/attr-array-816.s, ld-tic6x/attr-conformance-10-10.d, ld-tic6x/attr-conformance-10-11.d, ld-tic6x/attr-conformance-10-none.d, ld-tic6x/attr-conformance-10.s, ld-tic6x/attr-conformance-11-10.d, ld-tic6x/attr-conformance-11-11.d, ld-tic6x/attr-conformance-11-none.d, ld-tic6x/attr-conformance-11.s, ld-tic6x/attr-conformance-none-10.d, ld-tic6x/attr-conformance-none-11.d, ld-tic6x/attr-conformance-none-none.d, ld-tic6x/attr-conformance-none.s, ld-tic6x/attr-pic-0.s, ld-tic6x/attr-pic-00.d, ld-tic6x/attr-pic-01.d, ld-tic6x/attr-pic-1.s, ld-tic6x/attr-pic-10.d, ld-tic6x/attr-pic-11.d, ld-tic6x/attr-pid-0.s, ld-tic6x/attr-pid-00.d, ld-tic6x/attr-pid-01.d, ld-tic6x/attr-pid-02.d, ld-tic6x/attr-pid-1.s, ld-tic6x/attr-pid-10.d, ld-tic6x/attr-pid-11.d, ld-tic6x/attr-pid-12.d, ld-tic6x/attr-pid-2.s, ld-tic6x/attr-pid-20.d, ld-tic6x/attr-pid-21.d, ld-tic6x/attr-pid-22.d, ld-tic6x/attr-stack-16-16.d, ld-tic6x/attr-stack-16-8.d, ld-tic6x/attr-stack-16-816.d, ld-tic6x/attr-stack-16.s, ld-tic6x/attr-stack-8-16.d, ld-tic6x/attr-stack-8-8.d, ld-tic6x/attr-stack-8-816.d, ld-tic6x/attr-stack-8.s, ld-tic6x/attr-stack-816-16.d, ld-tic6x/attr-stack-816-8.d, ld-tic6x/attr-stack-816-816.d, ld-tic6x/attr-stack-816.s, ld-tic6x/attr-wchar-0.s, ld-tic6x/attr-wchar-00.d, ld-tic6x/attr-wchar-01.d, ld-tic6x/attr-wchar-02.d, ld-tic6x/attr-wchar-1.s, ld-tic6x/attr-wchar-10.d, ld-tic6x/attr-wchar-11.d, ld-tic6x/attr-wchar-12.d, ld-tic6x/attr-wchar-2.s, ld-tic6x/attr-wchar-20.d, ld-tic6x/attr-wchar-21.d, ld-tic6x/attr-wchar-22.d: New tests.
2010-11-01 * config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Use the offsetMaciej W. Rozycki1-2/+9
reloc supplied. (mips_ip)['o']: Initialise offset_reloc.
2010-10-29bfd:Joseph Myers1-1/+19
2010-10-29 Bernd Schmidt <bernds@codesourcery.com> Joseph Myers <joseph@codesourcery.com> * elf32-tic6x.c (elf32_tic6x_merge_attributes): Check for mismatch of DSBT attributes. binutils: 2010-10-29 Bernd Schmidt <bernds@codesourcery.com> Joseph Myers <joseph@codesourcery.com> * readelf.c (display_tic6x_attribute): Handle Tag_ABI_DSBT. gas: 2010-10-29 Bernd Schmidt <bernds@codesourcery.com> Joseph Myers <joseph@codesourcery.com> * config/tc-tic6x.c (OPTION_MDSBT, OPTION_MNO_DSBT): New enum values. (md_longopts): Add mdsbt and mno-dsbt. (tic6x_dsbt): New static variable. (md_parse_option): Handle OPTION_MDSBT and OPTION_MNO_DSBT. (md_show_usage): Output help text for -mdsbt and -mno-dsbt. (TAG): Add comma at the end. (tic6x_set_attributes): Set Tag_ABI_DSBT. * doc/as.texinfo: Document -mdsbt and -mno-dsbt. * doc/c-tic6x.texi (TIC6X Options): Likewise. (TIC6X Directives): Mention Tag_ABI_DSBT. gas/testsuite: 2010-10-29 Bernd Schmidt <bernds@codesourcery.com> Joseph Myers <joseph@codesourcery.com> * gas/tic6x/attr-dsbt-directive-1.d, gas/tic6x/attr-dsbt-directive-1.s, gas/tic6x/attr-dsbt-directive-2.d, gas/tic6x/attr-dsbt-directive-2.s, gas/tic6x/attr-dsbt-opts-mdsbt.d, gas/tic6x/attr-dsbt-opts-mno-dsbt.d: New tests. include/elf: 2010-10-29 Bernd Schmidt <bernds@codesourcery.com> Joseph Myers <joseph@codesourcery.com> * tic6x-attrs.h (Tag_ABI_DSBT): New. ld/testsuite: 2010-10-29 Bernd Schmidt <bernds@codesourcery.com> Joseph Myers <joseph@codesourcery.com> * ld-tic6x/attr-dsbt-0.s, ld-tic6x/attr-dsbt-00.d, ld-tic6x/attr-dsbt-01.d, ld-tic6x/attr-dsbt-1.s, ld-tic6x/attr-dsbt-10.d, ld-tic6x/attr-dsbt-11.d: New tests.
2010-10-282010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel1-6/+11
* config/tc-s390.c (md_begin): Only add to hash table if cpu and mode mask fit. 2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
2010-10-28 * config/tc-d30v.c (d30v_cons_align): Don't align .eh_frame.Alan Modra1-1/+2
2010-10-26 * config/obj-coff.c (coff_format_ops): Fix typo.Alan Modra1-1/+1
2010-10-25gas/Richard Sandiford1-63/+0
* config/tc-mips.c (macro2): Delete.
2010-10-25 bfd/Nathan Sidwell1-0/+2
* elf32-tic6x.c: Add attribution. gas/ * config/tc-tic6x.c: Add attribution. opcodes/ * tic6x-dis.c: Add attribution.
2010-10-25 * obj.h (struct format_ops): Add adjust_symtab.Alan Modra5-7/+16
* config/obj-multi.h (obj_adjust_symtab): Define. * config/obj-aout.c (aout_format_ops): Init new field. * config/obj-coff.c (coff_format_ops): Likewise. * config/obj-ecoff.c (ecoff_format_ops): Likewise. * config/obj-elf.c (elf_format_ops): Likewise.
2010-10-232010-10-23 Mark Mitchell <mark@codesourcery.com>Mark Mitchell3-24/+36
* config/obj-elf.c (elf_adjust_symtab): New. Move group section processing here from elf_frob_file. Ensure that group signature symbols have the name of the group. (elf_frob_file): Move group section processing to elf_adjust_symtab. * config/obj-elf.h (elf_adjust_symtab): Declare. (obj_adjust_symtab): Define. * config/tc-arm.c (arm_adjust_symtab): Call elf_adjust_symtab. 2010-10-23 Mark Mitchell <mark@codesourcery.com> * gas/elf/elf.exp: Add group0c test. * gas/elf/group0c.d: New. * gas/elf/group0a.d: Expect ".group" for the name of group sections. * gas/elf/group0b.d: Likewise. * gas/elf/group1a.d: Likewise. * gas/elf/group1b.d: Likewise. * gas/elf/groupautoa.d: Likewise. * gas/elf/groupautob.d: Likewise. * gas/elf/section4.d: Likewise. * gas/ia64/group-1.d: Likewise. Adjust hard-coded constants. 2010-10-22 Mark Mitchell <mark@codesourcery.com> * binutils-all/group-5.d: Expect ".group" for the name of group sections. * binutils-all/strip-2.d: Likewise. 2010-10-23 Mark Mitchell <mark@codesourcery.com> * ld-elf/group10.d: Expect ".group" for the name of group sections. * ld-elf/group2.d: Likewise. * ld-elf/group7.d: Likewise.
2010-10-22 ld:Rainer Orth1-1/+6
* emulparams/elf32_sparc_sol2.sh (OUTPUT_FORMAT): Set to elf32-sparc-sol2. * emulparams/elf64_sparc_sol2.sh (OUTPUT_FORMAT): Set to elf64-sparc-sol2. gas: * config/tc-sparc.h [TE_SOLARIS] (ELF_TARGET_FORMAT): Define as elf32-sparc-sol2. (ELF64_TARGET_FORMAT): Define as elf64-sparc-sol2. bfd: * elfxx-sparc.c (tpoff): Define bed, static_tls_size. Consider static_tls_alignment. * elf32-sparc.c (TARGET_BIG_SYM): Redefine to bfd_elf32_sparc_sol2_vec. (TARGET_BIG_NAME): Redefine to elf32-sparc-sol2. (elf32_bed): Redefine to elf32_sparc_sol2_bed. (elf_backend_static_tls_alignment): Redefine to 8. Include elf32-target.h. (elf_backend_static_tls_alignment): Undef again for VxWorks. * elf64-sparc.c (TARGET_BIG_SYM): Redefine to bfd_elf64_sparc_sol2_vec. (TARGET_BIG_NAME): Redefine to elf64-sparc-sol2. (ELF_OSABI): Undef. (elf64_bed): Redefine to elf64_sparc_sol2_bed. (elf_backend_static_tls_alignment): Redefine to 16. Include elf64-target.h. * config.bfd (sparc-*-solaris2.[0-6]): Split from sparc-*-elf*. Set targ_defvec to bfd_elf32_sparc_sol2_vec. [BFD64] (sparc-*-solaris2*): Set targ_defvec to bfd_elf32_sparc_sol2_vec. Replace bfd_elf64_sparc_vec by bfd_elf64_sparc_sol2_vec in targ_selvecs. * configure.in: Handle bfd_elf32_sparc_sol2_vec, bfd_elf64_sparc_sol2_vec. * configure: Regenerate. * targets.c (bfd_elf32_sparc_sol2_vec): Declare. (bfd_elf64_sparc_sol2_vec): Declare. (_bfd_target_vector): Add bfd_elf32_sparc_sol2_vec, bfd_elf64_sparc_sol2_vec.
2010-10-21bfd:Joseph Myers1-22/+22
* elf32-tic6x.c (elf32_tic6x_merge_arch_attributes): Update for attribute renaming. (elf_backend_obj_attrs_section): Change to ".c6xabi.attributes". binutils: * readelf.c (display_tic6x_attribute): Update for attribute renaming. gas: * config/tc-tic6x.c (tic6x_arch_attribute, tic6x_arches, md_assemble, tic6x_set_attributes): Update for attribute renaming. * doc/c-tic6x.texi: Update for attribute renaming. gas/testsuite: * gas/tic6x/attr-arch-directive-1.d, gas/tic6x/attr-arch-directive-2.d, gas/tic6x/attr-arch-directive-3.d, gas/tic6x/attr-arch-directive-4.d, gas/tic6x/attr-arch-directive-4.s, gas/tic6x/attr-arch-directive-5.d, gas/tic6x/attr-arch-directive-5.s, gas/tic6x/attr-arch-opts-c62x.d, gas/tic6x/attr-arch-opts-c64x+.d, gas/tic6x/attr-arch-opts-c64x.d, gas/tic6x/attr-arch-opts-c674x.d, gas/tic6x/attr-arch-opts-c67x+.d, gas/tic6x/attr-arch-opts-c67x.d, gas/tic6x/attr-arch-opts-none-1.d, gas/tic6x/attr-arch-opts-none-2.d, gas/tic6x/attr-arch-opts-override-1.d, gas/tic6x/attr-arch-opts-override-2.d: Update for attribute renaming and renumbering. include/elf: * tic6x-attrs.h (Tag_C6XABI_Tag_CPU_arch): Change to Tag_ISA, value 4. * tic6x.h (Values for Tag_C6XABI_Tag_CPU_arch): Rename for attribute renaming. ld: * emulparams/elf32_tic6x_le.sh (ATTRS_SECTIONS): Use .c6xabi.attributes, not __TI_build_attributes. ld/testsuite: * ld-tic6x/attr-arch-c62x-c62x.d, ld-tic6x/attr-arch-c62x-c64x+.d, ld-tic6x/attr-arch-c62x-c64x.d, ld-tic6x/attr-arch-c62x-c674x.d, ld-tic6x/attr-arch-c62x-c67x+.d, ld-tic6x/attr-arch-c62x-c67x.d, ld-tic6x/attr-arch-c64x+-c62x.d, ld-tic6x/attr-arch-c64x+-c64x+.d, ld-tic6x/attr-arch-c64x+-c64x.d, ld-tic6x/attr-arch-c64x+-c674x.d, ld-tic6x/attr-arch-c64x+-c67x+.d, ld-tic6x/attr-arch-c64x+-c67x.d, ld-tic6x/attr-arch-c64x-c62x.d, ld-tic6x/attr-arch-c64x-c64x+.d, ld-tic6x/attr-arch-c64x-c64x.d, ld-tic6x/attr-arch-c64x-c674x.d, ld-tic6x/attr-arch-c64x-c67x+.d, ld-tic6x/attr-arch-c64x-c67x.d, ld-tic6x/attr-arch-c674x-c62x.d, ld-tic6x/attr-arch-c674x-c64x+.d, ld-tic6x/attr-arch-c674x-c64x.d, ld-tic6x/attr-arch-c674x-c674x.d, ld-tic6x/attr-arch-c674x-c67x+.d, ld-tic6x/attr-arch-c674x-c67x.d, ld-tic6x/attr-arch-c67x+-c62x.d, ld-tic6x/attr-arch-c67x+-c64x+.d, ld-tic6x/attr-arch-c67x+-c64x.d, ld-tic6x/attr-arch-c67x+-c674x.d, ld-tic6x/attr-arch-c67x+-c67x+.d, ld-tic6x/attr-arch-c67x+-c67x.d, ld-tic6x/attr-arch-c67x-c62x.d, ld-tic6x/attr-arch-c67x-c64x+.d, ld-tic6x/attr-arch-c67x-c64x.d, ld-tic6x/attr-arch-c67x-c674x.d, ld-tic6x/attr-arch-c67x-c67x+.d, ld-tic6x/attr-arch-c67x-c67x.d: Update for attribute renaming.
2010-10-18 * config/tc-mips.c (macro)[ldd_std]: Fix the relaxation variantMaciej W. Rozycki1-20/+1
for absolute addressing.
2010-10-18 opcodes/Maciej W. Rozycki1-5/+8
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB macros before their corresponding MIPS III hardware instructions. gas/ * config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs. gas/testsuite/ * gas/mips/lineno.s: Convert to o32. * gas/mips/lineno.d: Adjust patterns accordingly. Force the o32 ABI.
2010-10-18 * config/tc-mips.c (mips_pseudo_table): Add "sbss".Maciej W. Rozycki1-0/+14
(s_change_sec): Handle it.
2010-10-15gas: blackfin: fix encoding of BYTEOP2M insnMike Frysinger1-2/+2
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode. Once we've fixed that, it's easy to see that the disassembler also likes to decode this insn incorrectly. So fix that and then add some tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-14Add CheckRegSize to instructions which require register size check.H.J. Lu1-3/+2
gas/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Check checkregsize instead of w for register size check. gas/testsuite/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run inval-reg. * gas/i386/inval-reg.l: New. * gas/i386/inval-reg.s: Likewise. opcodes/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add CheckRegSize. * i386-opc.h (CheckRegSize): New. (i386_opcode_modifier): Add checkregsize. * i386-opc.tbl: Add CheckRegSize to instructions which require register size check. * i386-tbl.h: Regenerated.
2010-10-14Add .d32 encoding suffix.H.J. Lu1-7/+17
gas/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (_i386_insn): Add disp32_encoding. (md_assemble): Don't call optimize_disp if disp32_encoding is set. (parse_insn): Support .d32 to force 32bit displacement. (output_branch): Use BIG if disp32_encoding is set. * doc/c-i386.texi: Document .d32 encoding suffix. gas/testsuite/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/disp32.d: New. * gas/i386/disp32.s: Likewise. * gas/i386/x86-64-disp32.d: Likewise. * gas/i386/x86-64-disp32.s: Likewise. * gas/i386/i386.exp: Run disp32 and x86-64-disp32.
2010-10-11gas: blackfin: reign in overeager insn flag handlingMike Frysinger1-7/+8
Currently, trying to declare single letter variables in Blackfin assembly can sometimes lead to parser errors if that letter is used for insn flags. For example, X, Z, S, M, and T are used to change the behavior of insns: R0 = 1; R0 = 1 (X); R0 = 1 (Z); But the current parser just looks for single letter tokens rather than ones that show up in the (FLAGS) field. So only match these letters as flags when they're in parentheses. Not a complete fix, but it at least lets gcc tests pass now (the test gcc/testsuite/gcc.c-torture/compile/mangle-1.c to be exact). A complete fix would require a significant parser rewrite in order to handle: R0 = (x) (x); /* zero extend the address of the symbol "x" */ R0 = W; R0 = W[P0]; Signed-off-by: Steve Kilbane <steve.kilbane@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-11gas: blackfin: support numeric local labels with LOOP_BEGIN/LOOP_END pseudo ↵Mike Frysinger3-0/+32
insns The current LOOP_BEGIN/LOOP_END pseudo insns hit parser errors when trying to use numeric local labels. So add support for them. Signed-off-by: David Gibson <david.gibson@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-11gas: blackfin: fix LOOP_BEGIN/LOOP_END pseudo insns handling of local labelsMike Frysinger1-2/+5
The current LOOP_BEGIN/LOOP_END pseudo insns hit "Internal errors" when using local labels as the loop names due to attempts at removing them. Signed-off-by: David Gibson <david.gibson@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-08Fix build with -DDEBUG=7Alan Modra1-0/+4
2010-10-07gas/Bernd Schmidt1-1/+8
* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field in SPKERNEL instructions. opcodes/ * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field in SPKERNEL instructions. gas/testsuite/ * gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests. * gas/tic6x/insns-c674x-sploop.s: Likewise.
2010-10-06 bfd/Nathan Sidwell1-8/+7
* elf32-arm.c (elf32_arm_stub_long_branch_any_arm_pic, elf32_arm_stub_long_branch_any_arm_pic): Use a consistent name for ip/r12. (arm_type_of_stub): Remove superfluous braces. gas/ * config/tc-arm.c (encode_branch): Remove superfluous braces. (do_t_branch): Move reloc setting to end of routine.
2010-10-042010-10-04 David Daney <ddaney@caviumnetworks.com>David Daney1-1/+36
* config/tc-mips.c (mips_fix_cn63xxp1): New variable. (mips_ip): Add errata work around when mips_fix_cn63xxp1 set. (OPTION_FIX_CN63XXP1, OPTION_NO_FIX_CN63XXP1): New enum options enumerations. (md_longopts): Add options for -mfix-cn63xxp1 and -mno-fix-cn63xxp1. (md_parse_option): Handle OPTION_FIX_CN63XXP1 and OPTION_NO_FIX_CN63XXP1. (md_show_usage): Add documentation for -mfix-cn63xxp1. * doc/c-mips.texi (-mfix-cn63xxp1, -mno-fix-cn63xxp1): Document the new options. 2010-10-04 David Daney <ddaney@caviumnetworks.com> * gas/mips/mips.exp (octeon-pref): Run the new test. * gas/mips/octeon-pref.s: New test. * gas/mips/octeon-pref.d: New expected results for the new test.
2010-09-27gas/Bernd Schmidt2-0/+22
* config/tc-tic6x.c (tic6x_fix_adjustable): New function. * config/tc-tic6x.h (tic6x_fix_adjustable): Declare. (tc_fix_adjustable): New macro. gas/testsuite/ * gas/tic6x/got-reloc.s: New test. * gas/tic6x/got-reloc.d: New test.
2010-09-272010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel1-0/+2
* s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196. (main): Recognize the new CPU string. * s390-opc.c: Add new instruction formats and masks. * s390-opc.txt: Add new z196 instructions. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/tc-s390.c: (md_parse_option): New option -march=z196. * doc/c-s390.texi: Document new option. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/s390.exp: Run the zarch-z196 test. * gas/s390/zarch-z196.d: Add new instructions. * gas/s390/zarch-z196.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise.
2010-09-272010-09-27 Tejas Belagod <tejas.belagod@arm.com>Matthew Gretton-Dann1-0/+12
* gas/config/tc-arm.c (do_neon_ldr_str): Deprecate ARM-mode PC-relative VSTR, issue an error in THUMB mode. * opcodes/arm_dis.c (print_insn_coprocessor): Apply off-by-alignment correction to unaligned PCs while printing comment. * gas/testsuite/gas/arm/vldr.s: New test for pc-relative VLDR disassembly comment. * gas/testsuite/gas/arm/vldr.d: Likewise. * gas/testsuite/gas/arm/vstr-bad.s: New test for PC-relative VSTR. * gas/testsuite/gas/arm/vstr-thumb-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-thumb-bad.d: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.d: Likewise.
2010-09-23 * bfd/bfd-in2.h (BFD_RELOC_ARM_HVC): New enum value.Matthew Gretton-Dann1-31/+152
* gas/config/tc-arm.c (arm_ext_virt): New variable. (arm_reg_type): Add REG_TYPE_RNB for banked registers. (reg_entry): Allow registers to be larger than a byte. (reg_alias): Fix type warning. (parse_operands): Parse banked registers when appropriate. (do_mrs): Add support for Virtualization Extensions. (do_hvc): New function. (do_t_mrs): Add support for Virtualization Extensions. (do_t_msr): Likewise. (do_t_hvc): New function. (SPLRBANK): New define. (reg_names): Add banked registers. (insns): Add support for Virtualization Extensions. (md_apply_fixup): Likewise. (arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions. (arm_extensions): Add 'virt' extension. (aeabi_set_public_attributes): Add support for Virtualization Extensions. * gas/doc/c-arm.texi: Document 'virt' extension. * gas/testsuite/gas/arm/armv7-a+virt.d: New test. * gas/testsuite/gas/arm/armv7-a+virt.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions. * gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test. * gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise. * include/opcode/arm.h (ARM_EXT_VIRT): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization Extensions. * opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. (thumb32_opcodes): Likewise. (banked_regname): New function. (print_insn_arm): Add Virtualization Extensions support. (print_insn_thumb32): Likewise.
2010-09-23 * gas/config/tc-arm.c (arm_ext_adiv): New variable.Matthew Gretton-Dann1-9/+32
(do_div): New function. (insns): Accept UDIV and SDIV in ARM state. (arm_cpus): The cortex-a15 option has all current v7-A extensions. (arm_extensions): Add 'idiv' extension. (aeabi_set_public_attributes): Update Tag_DIV_use values for the Integer Divide extension. * gas/doc/c-arm.texi: Document the idiv extension. * gas/testsuite/gas/arm/armv7-a+idiv.d: New test. * gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension. * gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test. * include/opcode/arm.h (ARM_AEXT_ADIV): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. * opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in ARM state.
2010-09-23 * config/tc-arm.c (arm_ext_v6m): New variable.Matthew Gretton-Dann1-3/+18
(arm_ext_m): Add support for OS extension. (arm_ext_os): New variable. (do_t_swi): In v6-M ensure we have the OS extension. (arm_cpus): The cortex-m1 and cortex-m0 options have the OS extension by default. (arm_archs): Add armv6s-m. (arm_extensions): Add 'os' extension. (cpu_arch_ver): Add support for v6S-M. * gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m architecture options. * gas/testsuite/gas/arm/archv6s-m-bad.d: New test. * gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise. * gas/testsuite/gas/arm/archv6s-m.d: Likewise. * gas/testsuite/gas/arm/archv6s-m.s: Likewise. * gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise. * include/opcode/arm.h (ARM_EXT_OS): New define. (ARM_AEXT_V6SM): Likewise. (ARM_ARCH_V6SM): Likewise.
2010-09-23 * gas/config/tc-arm.c (arm_ext_v6z): Remove.Matthew Gretton-Dann1-7/+23
(arm_ext_sec): New variable. (do_t_smc): In Thumb state SMC requires v7-A. (insns): Make SMC depend on Security Extensions. (arm_cpus): All -mcpu=cortex-a* options have the Security Extensions. (arm_extensions): Add 'sec' extension. (cpu_arch_ver): Reorder. (aeabi_set_public_attributes): Emit Tag_Virtualization_use as appropriate. * gas/doc/c-arm.texi: Document Security Extensions. * gas/testsuite/gas/arm/attr-march-all.d: Update for Security Extensions.. * gas/testsuite/gas/arm/attr-march-armv6k+sec.d: New test. * gas/testsuite/gas/arm/attr-march-armv6z.d: Update for Security Extensions. * gas/testsuite/gas/arm/attr-march-armv6zk.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zkt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv7-a+sec.d: New test. * gas/testsuite/gas/arm/attr-mcpu.d: Update for Security Extensions. * gas/testsuite/gas/arm/thumb32.d: Likewise. * gas/testsuite/gas/arm/thumb32.s: Likewise. * include/opcode/arm.h (ARM_EXT_V6Z): Remove. (ARM_EXT_SEC): New define. (ARM_AEXT_V6Z): Use Security Extensions. (ARM_AEXT_V6ZK): Likeiwse. (ARM_AEXT_V6ZT2): Likewise. (ARM_AEXT_V6ZKT2): Likewise. (ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions. (ARM_ARCH_V7A_SEC): New define. (ARM_ARCH_V7A_MP): Rename... (ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions. * ld/testsuite/ld-arm/attr-merge-6.attr: Update for Security Extensions. * ld/testsuite/ld-arm/attr-merge-7.attr: Likewise. * opcodes/arm-dis.c (arm_opcodes): SMC implies Security Extensions. (thumb32_opcodes): Likewise.
2010-09-23 * gas/config/tc-arm.c (arm_ext_mp): Add.Matthew Gretton-Dann1-5/+20
(do_pld): Update comment. (insns): Add support for pldw. (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support MP extension. (arm_extensions): Add 'mp' extension. (aeabi_set_public_attributes): Emit correct build attribute when MP extension is enabled. * gas/doc/c-arm.texi: Update for MP extensions. * gas/testsuite/gas/arm/arch7a-mp.d: Add. * gas/testsuite/gas/arm/arch7ar-mp.s: Likewise. * gas/testsuite/gas/arm/arch7r-mp.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.l: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for MP extension. * gas/testsuite/gas/arm/attr-march-armv7-a+mp.d: Add. * gas/testsuite/gas/arm/attr-march-armv7-r+mp.d: Likewise. * include/opcode/arm.h (ARM_EXT_MP): Add. (ARM_ARCH_V7A_MP): Likewise. * opcodes/arm-dis.c (arm_opcodes): Add support for pldw. (thumb32_opcodes): Likewise.
2010-09-23 * gas/config/tc-arm.c (md_pseduo_table): Add .arch_extension directive.Matthew Gretton-Dann1-18/+152
(arm_option_extension_value_table): Add. (arm_extensions): Change type. (arm_option_cpu_table): Rename... (arm_option_fpu_table): ...to this. (arm_fpus): Change type. (arm_parse_extension): Enforce alphabetical order. Allow extensions to be removed. (arm_parse_arch): Allow extensions to be specified with -march. (s_arm_arch_extension): Add. (s_arm_fpu): Update for type changes. * gas/doc/c-arm.texi: Document changes to infrastructure.
2010-09-23 * config/tc-mn10300.c (tc_gen_reloc): Replace absolute symbolsAlan Modra1-8/+9
with the absolute section symbol.
2010-09-22gas: blackfin: fix typo in BYTEOP16P commentMike Frysinger1-1/+1
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: reject multiple store insns in parallel insnsMike Frysinger1-0/+33
Check for & reject attempts to use multiple store insns in a single parallel insn combination. These are illegal per the Blackfin ISA. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: add missing register move insnsMike Frysinger2-2/+5
The Blackfin ISA supports moving just about anything to/from EMUDAT, so make sure the assembler accepts these insns too. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: clarify some errors with register usage in insnsMike Frysinger1-3/+3
Using "Register mismatch" everywhere can be a bit vague, so clarify why exactly we're barfing on these unsupported insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: fix DBG/DBGCMPLX insn encodingMike Frysinger1-2/+2
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are not encoded properly. So fix them, fix the display of them when being disassembled, and add testcases. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: handle multibyte symbolsMike Frysinger1-1/+1
Accept any 8bit char with the high bit set so as to support multibyte characters. Also use the locale safe regular expressions to match chars/digits. This brings the Blackfin assembler inline with the behavior of other assemblers. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes/gas: blackfin: handle more ASTAT flagsMike Frysinger2-1/+7
Support a few more ASTAT bits with the standard insns that operate on ASTAT bits directly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes/gas: blackfin: support OUTC debug insnMike Frysinger3-0/+27
The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: support ABORT debug insnMike Frysinger2-1/+7
There is a pseudo debug insn named ABORT that is commonly used in simulation, so support it in the assembler too. The disassembler already supports it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: add support for BF51x-0.2 processorsMike Frysinger1-0/+4
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
generated by cgit v1.1 at 2025-01-29 19:51:35 +0000